JP3995737B2 - Embedded gate type electrostatic induction thyristor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an embedded gate type electrostatic induction thyristor (hereinafter referred to as SI thyristor) having a cathode junction structure effective for increasing the turn-off speed without impairing the ignition sensitivity, the on-voltage, the gate-cathode breakdown voltage, and the like. )).
[0002]
[Prior art]
As a method for increasing the turn-off switching speed of an SI thyristor, an anode short-circuit structure, a cathode short-circuit structure, and a double short-circuit structure SI thyristor using both of them are known. As an example of such a conventional technique, an SI thyristor having a double short circuit structure disclosed in Japanese Patent Laid-Open No. 4-257266 is shown, and FIG. 5 is a sectional view thereof.
[0003]
In FIG. 5, this SI thyristor is formed with a p-type gate region 1 as a buried structure. On the cathode surface of the SI thyristor, a p-type low resistance region 2 is formed on the upper surface of the p-type gate region 1, and other regions are formed. The n-type cathode region 3 is configured, and a common cathode electrode 4 is connected to the p-type low resistance region 2 and the n-type cathode region 3 to form a cathode short-circuit structure.
[0004]
On the anode surface, the p-type anode region 5 and the n-type low resistance region 6 are formed adjacent to each other at a constant occupation area ratio and short-circuited by the anode electrode 7. In the SI thyristor having the above configuration, holes and electrons injected into the n-type base layers 8 and 9 are discharged to the outside by the p-type low resistance region 2 on the cathode side and the n-type low resistance region 6 on the anode side, respectively. High-speed turn-off can be realized.
[0005]
In the SI thyristor having the double short-circuit structure of FIG. 5, holes injected into the n-type base layer 8 in the initial turn-on state and the on-state easily flow out to the p-type low resistance region 2. As the value becomes smaller, the number of holes accumulated on the front surface of the n-type cathode region 3 decreases, and as a result, the efficiency of electron injection from the n-type cathode region 3 decreases.
[0006]
On the other hand, since electrons injected into the n-type base layer 9 easily flow out to the n-type low resistance region 6, electrons accumulated on the front surface of the p-type anode region 5 become smaller as the width of the p-type anode region 5 becomes smaller. As a result, hole injection from the p-type anode region 5 is reduced.
[0007]
Due to the short-circuiting effect, the SI thyristor has a lower ignition sensitivity, a lower turn-on speed, and a higher on-voltage in the middle / small current range as the turn-off speed increases. There are problems such as.
Furthermore, there is a similar problem with an SI thyristor having only a cathode short-circuit structure.
FIG. 6 is a distribution diagram of the impurity concentration in the AA plane cross section of FIG. 5, and the impurity concentration of the n-type base layer 9 increases stepwise toward the surface. Soft recovery is not achieved when the pn junction between the cathodes reversely recovers, and L · (di / dt) cannot be reduced sufficiently. Therefore, the potential of the true gate (* part) of the SI thyristor is lowered and turn-off fails. There is concern about the risk of
[0008]
[Problems to be solved by the invention]
The present invention was devised in view of the above points, and its object is to provide a cathode junction structure effective for speeding up turn-off without losing ignition sensitivity, turn-on speed, on-voltage, etc. It is to provide an SI thyristor having
[0009]
[Means for Solving the Problems]
In other words, the means to achieve that purpose is
In an SI thyristor having a buried gate structure, an n-type cathode region and a p-type low resistance region are arranged in parallel, or a cathode electrode is formed on one surface of a layer in which only the n-type cathode region is arranged, and the other An n-type base layer is formed on the surface of the n-type layer, and a p-type gate region is then embedded in the n-type base layer. The impurity concentration of the n-type layer is n-type. It is larger than that of the base layer and lower than the injected carrier concentration in the ON state, and the impurity concentration is continuously increased from the n-type base layer toward the n-type cathode region.
[0010]
Alternatively, the impurity of the n-type layer is introduced at the time of epitaxial growth, and the concentration thereof is continuously increased toward the element surface within a range of 5 × 10 17 or less per cubic centimeter.
Therefore, the configuration of the present invention is as follows.
[0011]
That is, the n-type cathode region and the p-type low resistance region are alternately arranged in parallel on the same plane, or the cathode electrode is formed on one surface where only the n-type cathode region is arranged, and the other surface is n In an electrostatic induction thyristor having a structure formed so that a p-type gate region is embedded in an n-type base layer via a p-type base layer, a parallel arrangement layer of an n-type cathode region and a p-type low resistance region, or n Between the n-type base layer and the n-type base layer, the impurity concentration is higher than the n-type base layer and lower than the n-type cathode region. It has a structure as an electrostatic induction thyristor characterized by interposing an n-type layer that becomes higher.
Alternatively, the n-type layer is formed of an epitaxial layer, and has a configuration as an electrostatic induction thyristor.
When the epitaxial layer of silicon is formed on the silicon substrate, the ratio of the flow rate of the n-type impurity source gas such as phosphine to the flow rate of the silicon source gas such as silane is continuously increased during the growth time. The structure may be formed by an increasing method, and the structure can be manufactured without any increase in the number of steps.
[0012]
Alternatively, the anode electrode is formed on one surface of the layer in which the p-type anode region and the n-type low resistance region are arranged in parallel, and the p-type layer and the n-type base layer are sequentially formed on the other surface. It has the structure as an electrostatic induction thyristor.
[0013]
In the initial turn-on stage and the stage where the main current is small, the carrier concentration injected into the n-type base layer is smaller than the carrier concentration of the n-type layer, and the n-type layer prevents holes from flowing out to the p low resistance region. Therefore, the operation of the SI thyristor with good ignition characteristics, high turn-on speed and low on-voltage is realized.
[0014]
Next, in the case of the cathode short-circuit structure, when the on-current increases and the injected carrier concentration reaches or exceeds the impurity concentration of the n-type layer, holes flow out through the n-type layer to the p-type low resistance region. As a result, the cathode is substantially short-circuited, the increase of holes accumulated in the front surface of the n-type cathode region is suppressed, and the electron injection from the n-type cathode region is suppressed, thereby increasing the turn-off speed, The operation of suppressing the main current from concentrating on the channel or segment is expected because the turn-off is spatially slow in the SI thyristor.
[0015]
Furthermore, when a negative reverse bias voltage is applied to the negative electrode of the gate electrode and the positive electrode of the cathode electrode, the depletion layer that extends to the n-type base layer as the reverse bias voltage increases reaches the n-type layer having a relatively high impurity concentration. The spread is suppressed. As a result, the punch-through phenomenon in which the depletion layer reaches the p-type low resistance region is prevented, and the gate-cathode falling voltage is easily increased as compared with the case where there is no n-type layer.
Since the n-type layer continuously increases from the n-type base layer toward the n-type cathode region, soft recovery is performed when the pn junction between the gate and cathode at the time of turn-off of the element reversely recovers and is included in the connection loop. Since the decrease in the bias applied to the true gate (* portion) due to the decrease in the gate negative voltage due to the wiring inductance is suppressed, the turn-off failure is eliminated. In addition, since the true gate portion has a high resistance, it is normally off and the usability is increased.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional structure diagram showing a first embodiment of the present invention, FIG. 2 is an impurity concentration distribution diagram of the AA plane of FIG. 1, and FIG. 3 is a schematic diagram showing a second embodiment of the present invention. FIG. 4 is a schematic cross-sectional structure diagram showing a third embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 5 denote parts having the same configuration and function.
In the present invention, n-type cathode regions and p-type low resistance regions are alternately arranged in parallel on the same plane, or a cathode electrode is formed on one surface where only the n-type cathode region is disposed, and the other surface. In an electrostatic induction thyristor having a structure formed so that a p-type gate region is embedded in an n-type base layer via an n-type base layer, a parallel arrangement layer of an n-type cathode region and a p-type low resistance region Alternatively, an n-type layer in which the impurity concentration continuously increases from the n-type base layer toward the n-type cathode region is interposed between the arrangement layer of only the n-type cathode region and the n-type base layer. .
The n-type layer is formed by epitaxial growth. Further, an anode electrode is formed on one surface of the layer in which the p-type anode region and the n-type low resistance region are arranged in parallel, and a p-type layer and an n-type base layer are sequentially formed on the other surface.
[0017]
Examples of the SI thyristor thus configured will be described below with reference to Examples 1 to 3.
In FIG. 1, 11 is an n-type cathode region, 12 is an n-type layer, 13 is a base layer, 14 is a p-type gate region, and 15 is a p-type layer. In the first embodiment, the turn-on initial stage and the main current are small. In some cases, carriers injected into the base layer 13 are accumulated on the front surfaces of the n-type layer 12 and the p-type layer 15, so that they are easily turned on and the on-voltage is low.
On the base layer 13 made of an epitaxial layer in FIG. 1, the impurity concentration is continuously higher toward the element surface as shown by the point c-e in FIG. 2 in the range of 5 × 10 17 or less per cubic centimeter. An n-type cathode region 11 and an n-type cathode region 11 are formed on the surface on which the n-type epitaxial layer is formed by selective diffusion or ion implantation. Therefore, in this example, the n-type layer 12 is formed of an epitaxial layer, and the impurity diffusion depth for forming the n-type cathode region 11 can be reduced, so that the heat treatment process is shortened. There is an advantage that the pn junction structure of the SI thyristor can be miniaturized.
[0018]
When the epitaxial layer of silicon is formed on the silicon substrate, the ratio of the flow rate of the n-type impurity source gas such as phosphine to the flow rate of the silicon source gas such as silane is continuously increased during the growth time. The structure can be manufactured without any increase in the number of steps.
As a result, the gate-cathode current at turn-off becomes soft recovery, and even if the gate circuit is not changed, L · (di / dt) is reduced and the bias applied to the true gate (* part) is reduced. Can be kept small. Further, since the true gate portion is i-layered, the ignition sensitivity is improved and the normally-off state is achieved, which makes it easy to use.
[0019]
Next, Examples 2 and 3 will be described with reference to FIGS. 3 and 4. The impurity concentration on the AA plane in FIGS. 3 and 4 has been described with reference to FIG.
In FIG. 2, the impurity concentration increases from the base layer 13 toward the n-type cathode region 11 in the same manner as described above, so that punch-through is difficult to occur, and the breakdown voltage between the gate and the cathode is reduced. There is no decline.
1, 3 and 4 can be anything, and normal type, anode short type, with n buffer, type, n buffer and anode short type are also applicable.
In FIG. 4, a p-region is formed between n + (diffusion or ion implantation method) to form a cathode short structure stronger than that of the second embodiment.
[0020]
Thus, when the on-current increases and the injected carrier concentration reaches or exceeds the concentration of the n-type layer 12 and the p-type layer 15, a high-speed turn-off is obtained by a substantial cathode short-circuit and anode short-circuit, respectively.
The cathode junction structure of the present invention can be applied to the case where the p-type layer 15 of the anode junction structure of the SI thyristor of FIG. The present invention can be applied without being restricted by the structure on the anode side, including the case where an n-type buffer layer is provided between the base layers 13.
In addition, when the present invention is applied to a buried gate type static induction transistor in which the p-type layer 15 is changed to an n-type, it is possible to improve the characteristics in terms of speeding up and high breakdown voltage.
Furthermore, the cathode junction structure of the present invention can also be applied to a configuration in which the p-type and the n-type in the above-described embodiment are interchanged.
[0021]
【The invention's effect】
As described above, according to the present invention, unlike the conventional cathode short-circuit structure, when the turn-on is early and when the main current is small, the accumulation of holes on the front surface of the n-type cathode region is large, so the ignition sensitivity is good. The turn-on speed can be increased and the on-voltage can be lowered. Further, when the cathode short-circuit structure is applied, if the on-current is increased, the cathode is substantially short-circuited, so that the turn-off speed is increased. In addition, by forming an n-type epitaxial layer in front of the n-type cathode region, heat treatment can be reduced after the p-type gate region is buried, and as a result, the device structure is improved by miniaturizing the junction structure. It is valid.
When the gate electrode is negative and the cathode electrode is applied with a positive reverse bias voltage, the depletion layer extending to the n-type base layer is suppressed when reaching the n-type layer. There is an effect of preventing the resistance region from being reached, and there is an effect that the voltage drop between the gate and the cathode can be increased as compared with the case where there is no n-type layer.
Since the n-type layer continuously increases toward the device surface, when the pn junction between the gate and cathode at the time of turn-off of the device reversely recovers, it is soft-recovered and the gate negative due to the wiring inductance included in the connection loop A decrease in bias applied to the true gate (* portion) due to a decrease in voltage can be suppressed to a small level. In addition, since the true gate portion has a high resistance, it is normally off, which increases usability.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a first embodiment of the present invention.
FIG. 2 is an impurity concentration distribution diagram similar to FIG. 6 on the BB plane of FIG. 1;
FIG. 3 is a schematic cross-sectional structure diagram showing a second embodiment of the present invention.
FIG. 4 is a schematic cross-sectional structure diagram showing a third embodiment of the present invention.
FIG. 5 is a schematic sectional view showing an example of a conventional structure.
[Explanation of symbols]
1 p-type gate region 2 p-type low resistance region 3 n-type cathode region 4 cathode electrode 5 p-type anode region 6 n-type low resistance region 7 anode electrode 8 n-type base layer 9 n-type base layer
10 Gate electrode
11 n-type cathode region
12 n-type layer
13 n-type layer
14 p-type gate region
15 p-type layer
16 p-type low resistance region

Claims (2)

or n-type cathode region and the p-type low-resistance regions are arranged in parallel in the same plane alternately, or the cathode electrode is formed on one surface only a placed n-type cathode region, n-type on the other surface In an electrostatic induction thyristor having a structure formed so that a p-type gate region is embedded in an n-type base layer via a layer, a parallel arrangement layer of an n-type cathode region and a p-type low resistance region, or an n-type cathode An embedded gate type in which an n-type layer whose impurity concentration continuously increases from the n-type base layer toward the n-type cathode region is interposed between the region-only arrangement layer and the n-type base layer Static induction thyristor.   2. The buried gate type electrostatic induction thyristor according to claim 1, wherein the n-type layer is formed by epitaxial growth.

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