JP3996355B2 - Multiprocessor system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a communication control technique in a multiprocessor system, and more particularly to a technique effective when applied to a communication control technique for speeding up lock / unlock processing.
[0002]
[Prior art]
In order to perform efficient multi-process control or parallel process control in a multi-processor system, high-speed synchronization, exclusion, and communication control between processors are necessary. Therefore, a shared register called a communication register that is faster than the main memory may be used.
[0003]
Japanese Patent Application Laid-Open No. 2000-187852 discloses an example of high-speed synchronization between processors using a communication register having the configuration shown in FIG. 8 in the multiprocessor system shown in FIG.
[0004]
The N communication register modules 400 to 402 are connected to the N processors 10 to 12 on a one-to-one basis via signal lines L80 to L82. Each of the processors 10 to 12 outputs a load store request and a main memory real address to the signal lines L80 to L82. The communication register modules 400 to 402 have communication register groups 500 to 502 including a plurality of registers, and the communication register modules are coupled to each other via a communication module bus 700. Registers with numbers corresponding to each other in each of the communication register groups 500 to 502 are controlled so as to hold the same value between the communication register modules (this is referred to as “the communication register is mirrored”). The load store requests on the signal lines L80 to L82 are decoded by the decoders 430 to 432 in the communication register module. When the request is an access request to the main memory 30, the main memory 30 is stored via the interconnection network 20. When access is controlled and the request is an access request to the communication register, the communication register group 500 to 502 is controlled to be accessed via the inter-communication module bus 700.
[0005]
Specifically, when a write request is received from the processor, the interconnection network 20 or the inter-communication module bus 700 controls to write the same value to all the communication register modules, and the reading from the processors 10 to 12 is performed. In response to the request, values are read from the registers in the communication register modules 400 to 402 corresponding to the processors 10 to 12.
[0006]
Each communication register is mapped on the memory address space by a memory mapped register method (MMR method). In this conventional example, when a lock request is made and a fixed value indicating an unlocked state is set in the communication register, the processor number of the processor that issued the lock request is set in the communication register, and the reply data is also set in the reply data. The same processor number is returned. On the other hand, if a value other than a fixed value indicating an unlocked state is set in the communication register, the contents of the communication register (in this case, the other processor number that is locked) are returned as reply data. If the value of the reply data is the own processor number, the processor can detect the lock success, and if the other processor number, the lock failure can be detected, and lock / unlock processing can be performed by load / store requests without changing the conventional processor architecture. become.
[0007]
Also, the lock value is not a processor number, but a process number uniquely assigned to identify each of a plurality of processes operating in parallel within each processor, and lock / unlock processing is performed in units of processes during multi-process. It can also be realized.
[0008]
[Problems to be solved by the invention]
When the process number is used as a lock value in the multiprocessor system disclosed in the above Japanese Patent Laid-Open No. 2000-187852, it is necessary to increase the number of communication registers in the communication register module in accordance with the number of processes that are lock request sources. There is. In addition, since the communication register is mirrored, the influence of the increase in the communication register on the physical quantity of the entire system is great.
[0009]
On the other hand, it is also conceivable to perform control so that the communication register has individual contents between the communication register modules without mirroring (this is referred to as “laying the communication register flat”). In this way, the increase in the amount can be suppressed, but the access signal to the communication register existing in the different communication register module and the report signal of the lock success / failure must be relayed through the communication module bus, and the access speed decreases. To do.
[0010]
An object of the present invention is to provide a large number of locks / unlocks for synchronization, exclusion, and communication control between processors in a multiprocessor system in which a main memory is shared by a plurality of processors without increasing a circuit or a logical amount. The object is to provide a technology capable of accurately realizing the processing of a request.
[0011]
Another object of the present invention is to provide a large number of locks for synchronization, exclusion, and communication control between processors without reducing the access speed to the main memory in a multiprocessor system in which a plurality of processors share the main memory. An object of the present invention is to provide a technique capable of accurately realizing processing of an unlock request.
[0012]
Another object of the present invention is a multiprocessor system in which a plurality of processors share a main memory, and the parallel operation of individual processors without causing an increase in circuit or logical quantity or a decrease in access speed to the main memory. It is an object of the present invention to provide a technique capable of accurately realizing processing of a large number of lock / unlock requests for synchronization, exclusion, and communication control among a plurality of processes.
[0013]
Another object of the present invention is that in a multiprocessor system in which a main memory is shared by a plurality of processors, a number of units for synchronization, exclusion, and communication control between processors or between processes without changing the processor architecture or the like. An object of the present invention is to provide a technique capable of accurately realizing processing of a lock / unlock request.
[0014]
[Means for Solving the Problems]
According to the present invention, in a multiprocessor system having a configuration in which a communication register is interposed between a main memory and each of a plurality of processors sharing the main memory, the communication register holds a locked / unlocked state. In this configuration, a first register and a second register for holding lock / unlock information are provided. The first register that holds the locked / unlocked state is mirrored between the communication register modules. That is, the communication register modules are controlled to hold the same value. On the other hand, the second register holding the lock / unlock information is placed flat between the communication register modules. That is, individual contents are held for each communication register module.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a conceptual diagram showing an example of the overall configuration of a multiprocessor system according to an embodiment of the present invention, and FIGS. 2, 3 and 4 are conceptual diagrams illustrating an example of the configuration in more detail. It is.
[0017]
The multiprocessor system according to the present embodiment is configured such that a plurality of processors 10 (N from # 1 to #N) share the main memory 30 via the communication register 40 and the interconnection network 20. The communication register 40 includes a plurality of communication register modules 400 (N of # 1 to #N).
[0018]
Each of the plurality of communication register modules 400 is connected to each of the plurality of processors 10 on a one-to-one basis via a signal line L80. Each processor 10 outputs the load store request and the real address of the main memory 30 to the signal line L80.
[0019]
As illustrated in FIG. 2, each communication register module 400 includes a communication register group 500 (# 1 to #N) including a plurality of registers, and a communication module bus 700 is provided between the communication register modules 400. Combined with The load / store request on the signal line L80 is decoded by the decoder 430 in the communication register module 400. When the request is an access request to the main memory 30, the main memory 30 is connected via the signal line L80 and the interconnection network 20. If the request is an access request to the communication register 40, the communication register group 500 is controlled to be accessed via the inter-communication module bus 700.
[0020]
Note that the inter-communication module bus 700 may be constituted by a coupled network instead of a bus as long as it is guaranteed that broadcast write requests to all the communication register modules 400 reach all the communication register modules at the same time.
[0021]
FIG. 3 shows an example of the configuration of the communication register group 500 in the present embodiment. In the present embodiment, the communication register group 500 includes two types of communication registers, a lock information register 510 and a lock state register 520.
[0022]
The lock information register 510 is a register composed of a plurality of bits, and there are a total of N × M registers throughout the communication register group 500. Each register is assigned a unique number (1 to N × M) as a register number. Each register entity is distributed by M to N communication register modules. Specifically, register numbers 1 to M are set in the communication register module # 1, register numbers M + 1 to 2M are set in the communication register module # 2, and register number (N-1) is set in the communication register module #N. Registers are allocated to each communication register module in the form of M + 1 to N × M.
[0023]
The lock status register 520 is a 1-bit flag register, and there are N × M registers for each communication register group. Register numbers from 1 to N × M are assigned to each communication register group 500. Registers having corresponding register numbers between different communication register modules 400 hold the same value (changes in the lock status register 520 in one communication register module 400 always lock in other communication register modules 400 Is reflected in the status register 520).
[0024]
That is, the lock information register 510 is placed flat between the communication register modules, and the lock status register 520 is mirrored between the communication register modules. All of these are mapped to real addresses, and access to the registers is performed by instructions such as load / store for performing memory access.
[0025]
When the flag of the lock state register 520 is set, it indicates that the communication register is in the lock state, and the process number of the process that requested the lock process is set in the lock information register 510 having the corresponding register number. The When the flag of the lock state register 520 is reset, it indicates that the communication register is unlocked, and the content of the lock information register 510 is Don't care.
[0026]
A register for setting a process number (lock information register 510) exists in a flat manner, and an increase in the amount of material can be suppressed as compared with the case where the entire communication register is mirrored. In addition, since only the flag register (lock status register 520) is mirrored, it is possible to return a lock success / failure report for the lock request to the processor 10 without going through the inter-communication module bus 700.
[0027]
In order to access the lock information register 510 and the lock status register 520 and actually perform the lock / unlock process, an instruction used in the lock / unlock process when the lock flag is on the main memory 30 in the conventional architecture is used. use. In this embodiment, as an example, a lock flag operation instruction in the PowerPC architecture is used.
[0028]
Note that the memory synchronization instruction and the like in the PowerPC architecture are described in documents such as “Inside PowerPC” P181 issued on and after December 10, 1994, SOFTBANK CORP.
[0029]
In the PowerPC architecture, the lock / unlock process when the lock flag exists in the main memory is realized by the instruction sequence shown in FIG.
[0030]
The meaning of each command in FIG. 5 is shown below. Note that r3 is a register that contains an address on the main memory where the lock flag exists, r5 is a register that stores the read lock flag value, and r4 is a register that contains a newly set lock value.
[0031]
lwarx r5, 0, r3: The value of the lock flag is read and stored in the register r5. At the same time, reservation (described later) is established.
[0032]
Compare the value of cmp r5,0: r5 with zero.
[0033]
bc loop: If the value of r5 is not zero, return to loop.
[0034]
stwcx. r4, 0, r3: If the reservation remains, the value r4 is successfully written to the lock flag. If the reservation has been discarded, writing the lock flag fails.
[0035]
bc loop: Return to loop if the lock flag writing has failed. If successful, execute the instruction sequence in the critical region after the next line.
[0036]
sync: guarantees that all instruction execution in the critical region is complete.
[0037]
stw 0,0 (r3): Write zero to the lock flag.
[0038]
The instruction sequence over the first five lines indicates the lock process, the last line indicates the unlock process, and the rest indicates the critical region.
[0039]
lwarx instruction, stwcx. The instructions are referred to as a load and reserve instruction and a store conditional instruction, respectively, and are always used as a pair when realizing atomic processing in the PowerPC architecture.
[0040]
The load and reserve instruction performs an operation of reading the contents for a specified address and establishes a protection area called reservation. If the reservation established by the preceding load and reserve instruction has not been discarded, the store conditional instruction performs a write operation to the specified address, and reports the “success” of the store operation to the processor. If a reservation exists and another processor issues a store instruction to update the contents of the address, the reservation is discarded. In this state, when the processor that first issued the load and reserve instruction issues a store conditional instruction, the store operation is not performed, and a reply indicating “failure” is reported to the processor.
[0041]
When realizing the lock processing, the processor first issues a load and reserve instruction to the lock flag in the main memory. If the read flag value is not zero, the other processor is locked, so that the own processor returns to loop and repeats the load and reserve instruction until the flag value becomes zero. When the flag value becomes zero, the lock flag is set by a store conditional instruction. At this time, if the lock flag setting of the other processor is earlier than the own processor, the reservation is discarded. Therefore, the flag value setting fails, and it returns to loop again and waits for the lock value to become zero. If the flag value is set successfully, the critical region is executed. After executing the critical region, store zero in the lock flag and perform unlock processing.
[0042]
FIG. 6 shows an example of an instruction sequence when lock / unlock processing is performed using the lock information register 510 and the lock state register 520 in the present embodiment.
[0043]
The meaning of each command in FIG. 6 is shown below. Note that r3 is a register storing a real address to which the lock information register R0 is mapped, and r4 is a register containing a lock value to be newly set.
[0044]
stwcx. r4, 0, r3: When the value of the lock state register F0 is zero, the lock state register F0 is set to 1, and the value of r4 is successfully written to the lock information register R0. When the value of the lock state register F0 is 1, the write operation fails.
[0045]
bc loop: If flag writing is “failure”, return to loop. If “success”, move to the critical region after the next line.
[0046]
sync: guarantees that all instruction execution in the critical region is complete.
[0047]
stw 0,0 (r3): Zero is written to the lock information register R0 and simultaneously zero is set to the lock state register F0.
[0048]
The instruction sequence for the first two lines is the lock process, the last one is the unlock process, and the other is the critical region.
[0049]
The operation of the store conditional instruction here is completely different from the operation of the example of FIG. Only the lock information register 510 is explicitly shown in the operand, but when issued, the flag value of the corresponding lock state register 520 is also referred to / updated. If the flag value is zero, the flag is set, the lock value is set in the lock information register 510, and a “success” report is sent to the processor. If the flag value is 1, neither the flag nor the lock value is set, and a “failure” report is sent to the processor.
[0050]
When realizing the lock processing, first, a store conditional instruction is issued to the lock information register 510. Then, the flag value of the corresponding lock state register 520 is referred to. If the flag value is zero, the lock state register 520 is in an unlocked state. If the flag value is 1, the state is locked by another process, so the loop is returned and the store-conditional instruction is repeated again. If the lock value is set successfully, the critical region is executed. After executing the critical region, a store instruction is issued to the lock information register 510. Then, the flag value of the corresponding lock state register 520 is unconditionally set to zero, the value is written in the lock information register 510, and unlock processing is performed.
[0051]
As described above, in the present embodiment, the operation of the instruction that operates the existing lock flag is switched between when the main memory 30 is accessed and when the communication register 40 is accessed. If the switching control is performed in the communication register module 400, high-speed lock processing using the communication register 40 can be realized without changing the conventional processor architecture. The high speed is also clear from the fact that the execution time can be shortened by reducing the number of instructions required for the lock processing, as shown by the difference in the number of instruction strings between FIG. 5 and FIG.
[0052]
FIG. 4 shows an example of the configuration of each communication register module 400 in the multiprocessor system of the present embodiment.
[0053]
The request input from the signal line L80 is analyzed by the decoder 430. If the request is a load / store request, if the access address is outside the range mapped to the communication register 40, the request is connected to the signal line L80. The data is sent to the main memory 30 via the network 20. If the access address is within the range mapped to the communication register 40, the request is sent to the request control circuit 410. The operation for each request will be described below.
[0054]
In the description of the present embodiment, the communication register module 400 directly connected to the requesting processor 10 via the signal line L80 is referred to as “master module”, and the other communication register modules 400 are referred to as “slave modules”. Are defined respectively.
[0055]
(A) Store conditional request (lock request)
When a store conditional request is input, the request control circuit 410 sends the request to the selector 480, and based on this, the bus output control circuit 490 provides a bus for broadcast output to all communication register modules on the inter-communication module bus 700. Secure the right. When the bus right is secured and the broadcast is executed, a request is simultaneously made to the bus input control circuit 420 of all the communication register modules 400 including the own module.
[0056]
The bus input control circuit 420 analyzes the request and checks whether the lock information register 510 is in its own module. Then, the request is sent to the register input circuit 440. Based on this, the contents of the lock state register 520 to be written are read and output from the register output circuit 450. At that time, the register input circuit 440 has a write value to the lock information register 510 (in this case, the process number value of the lock request source) and a write value to the lock state register 520 (in this case, a value 1 to be written when the lock is successful). Until the instruction signal is received from the signal line L70. If the lock information register 510 to be written does not exist in its own module, only the value written to the lock status register 520 is held. The output of the register output circuit 450 is sent to the comparator 460, and the read value is checked.
[0057]
Subsequent operations differ as follows depending on whether the own module is a master module or a slave module.
[0058]
(A) -1: Master module
When the read value is 1, it is locked by another process, so that the lock fails, and a reply report indicating “failure” of the lock is sent to the reply control circuit 470 via the signal line L80. Instruct to return. At the same time, the write value held in the register input circuit 440 is discarded.
[0059]
If the value is zero, the lock state is not locked, and the reply control circuit 470 is instructed to return a reply report indicating “success” to the processor 10 via the signal line L80. At the same time, the comparator 460 instructs the register input circuit 440 to write the write value to the lock information register 510 and the write value to the lock state register 520 to the register through the signal line L70. When the lock information register 510 to be written does not exist in the own module, writing is performed only to the lock state register 520.
[0060]
Since the lock status register 520 is mirrored, the lock success / failure report to the processor 10 can be performed without going through the inter-communication module bus 700, and the lock process can be speeded up. In addition, since the lock information register 510 is placed flat, it is possible to suppress the influence of the physical quantity on the system due to the increase in the number of communication registers required when the process number is set as the lock value.
[0061]
(A) -2: Slave module
When the read value is 1, the lock is failed because it is locked by another process, the value in the register input circuit 440 is discarded, and the process ends.
[0062]
Further, when the value is zero, since it is in the unlocked state, the comparator 460 instructs the register input circuit 440 to write the write value to the lock information register 510 and the write value to the lock state register 520 to the register through the signal line L70. To do. When the lock information register 510 to be written does not exist in the own module, writing is performed only to the lock state register 520.
[0063]
An access request to the communication register 40 is once broadcast via the inter-communication module bus 700 and accessed via the bus input control circuit 420. For this reason, even if a plurality of processes issue a lock request to the same communication register 40 almost simultaneously, the requests are serialized on the inter-communication module bus 700, and the lock request does not pass through.
[0064]
(B) Store request (unlock request)
When a store request is input, the request control circuit 410 sends the request to the selector 480, and based on this, the bus output control circuit 490 writes the write value to the lock information register 510 in the inter-communication module bus 700 (in this case, a store instruction). A bus right for outputting a specified store data) and a write value to the lock state register 520 (in this case, a flag reset value) is secured. When the bus right is secured and the write value is broadcast, a write request is simultaneously loaded in the bus input control circuit 420 of all the communication register modules including the own module. The bus input control circuit 420 analyzes the request and checks whether the lock information register 510 exists in the own module. In some cases, the write value to both the lock information register 510 and the lock state register 520 is sent to the register input circuit 440, and in the other case, only the write value to the lock state register 520 is sent to the register input circuit 440. Based on this, writing to the communication register group 500 is performed.
[0065]
(C) Load request
When a load request is input, the request control circuit 410 sends the request to the selector 480, and based on this, the bus output control circuit 490 sends a read request to the lock information register 510 or the lock status register 520 to the inter-communication module bus 700. Secure the bus right to output. When the bus right is secured and the request is broadcast, a read request is simultaneously loaded in the bus input control circuit 420 of all the communication register modules 400 including the own module.
[0066]
The bus input control circuit 420 analyzes the request, and when an access destination register exists in the own module, the bus input control circuit 420 sends the request to the register input circuit 440. Based on this, the value of the register in the communication register group 500 is read and output from the register output circuit 450. The read value is sent to the selector 480, and the bus output control circuit 490 secures the bus right to output the read value to the inter-communication module bus 700. When the bus right is secured, the value is sent to the bus input control circuit 420 of the communication register module 400 of the load request source through the bus.
[0067]
The bus input control circuit 420 of the load request source communication register module 400 instructs the reply control circuit 470 to reply the value to the load request issuer processor via the signal line L90, and the reply value is sent to the processor 10 via the signal line L80. Returned to
[0068]
As described above, according to the multiprocessor system of the present embodiment, the following is possible.
[0069]
The communication register 40 is divided into a lock information register 510 and a lock state register 520, and the lock information register 510 is held flat between the communication register modules 400, and the lock state register 520 is mirrored. Since it is possible to suppress an increase in the amount of a multiprocessor system that performs lock processing in units of processes, and a lock success / failure report to the processor 10 at the time of lock processing can be performed without using the inter-communication module bus 700, The lock process can be speeded up.
[0070]
Since an access request to the communication register 40 is broadcast and serialized via the inter-communication module bus 700, even if a plurality of processes issue a lock request to the same communication register 40 at the same time, the lock request is prevented from passing through. be able to.
[0071]
By using a conventional lock flag operation instruction and controlling the operation of the instruction in the communication register module 400 depending on whether the lock flag exists in the main memory 30 or in the communication register 40, the processor 10 of the conventional architecture is controlled. Can be used to realize high-speed lock / unlock processing.
[0072]
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0073]
For example, the processor is not limited to the PowerPC architecture and can be widely applied to general processors.
[0074]
【The invention's effect】
According to the present invention, in a multiprocessor system in which a main memory is shared by a plurality of processors, a large number of locks / unlocks for synchronization, exclusion, and communication control between processors without increasing the circuit and the amount of logical objects. The effect that the processing of the request can be accurately realized is obtained.
[0075]
According to the present invention, in a multiprocessor system in which a main memory is shared by a plurality of processors, a large number of locks / unlocks for synchronization, exclusion, and communication control between processors without reducing the access speed to the main memory. The effect that the processing of the request can be accurately realized is obtained.
[0076]
According to the present invention, in a multiprocessor system in which a main memory is shared by a plurality of processors, a plurality of processors that operate in parallel in each processor without causing an increase in circuits, logical quantities, etc. or a decrease in access speed to the main memory. It is possible to accurately realize processing of a large number of lock / unlock requests for synchronization, exclusion, and communication control between the processes.
[0077]
According to the present invention, in a multiprocessor system in which a main memory is shared by a plurality of processors, a number of locks for synchronization, exclusion, and communication control between processors or between processes without changing the processor architecture or the like. There is an effect that the processing of the unlock request can be accurately realized.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing an example of the overall configuration of a multiprocessor system according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram illustrating a part of a configuration of a multiprocessor system according to an embodiment of the present invention in more detail.
FIG. 3 is a conceptual diagram illustrating a part of the configuration of a multiprocessor system according to an embodiment of the present invention in more detail.
FIG. 4 is a conceptual diagram illustrating a part of a configuration of a multiprocessor system according to an embodiment of the present invention in more detail.
FIG. 5 is an explanatory diagram showing an example of a command sequence for lock processing by a processor when a lock flag is placed on the main memory;
FIG. 6 is an explanatory diagram showing an example of an instruction sequence for lock processing by a processor in a multiprocessor system according to an embodiment of the present invention;
FIG. 7 is a conceptual diagram showing a configuration of a conventional multiprocessor system.
FIG. 8 is a conceptual diagram showing a part of a configuration in a conventional multiprocessor system in more detail.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Processor, 20 ... Interconnection network, 30 ... Main memory, 40 ... Communication register, 400 ... Communication register module, 410 ... Request control circuit, 420 ... Bus input control circuit, 430 ... Decoder, 440 ... Register input circuit, 450 ... register output circuit, 460 ... comparator, 470 ... reply control circuit, 480 ... selector, 490 ... bus output control circuit, 500 ... communication register group, 510 ... lock information register (second register), 520 ... lock status register (First register), 700 ... communication module bus, L70 ... signal line, L80 ... signal line, L90 ... signal line.

Claims (3)

A plurality of processors, a main memory shared by the processors, an interconnection network for coupling the processors and the main memory, a plurality of communication register modules corresponding to each of the plurality of processors, and a plurality of the communications Each of the communication register modules is a multiprocessor system having a plurality of communication registers,
The communication register includes a first register that holds a lock / unlock state and a second register that holds lock / unlock information.
The first register holding the locked / unlocked state holds the same contents as the corresponding register in the different communication register module;
The second register holding lock / unlock information holds individual contents for each of the communication register modules,
In response to a lock processing request from the processor, the request is broadcast to all the communication register modules via the interface, and the lock / unlock state in the communication register in the communication register module corresponding to the processor is broadcast. The success / failure of the lock is reported to the processor with reference to the value of the first register that holds the first register, and the lock / unlock state in all the communication register modules is held when the lock is possible. A multiprocessor system in which the same lock flag is set in a register, and the process number in the processor that issued a lock processing request is set in the second register that simultaneously holds corresponding lock / unlock information .   2. The multiprocessor system according to claim 1, wherein, when a lock processing is executed, when an instruction for operating a lock flag existing in a conventional processor architecture is issued, the lock flag is on the main memory and on the communication register. A multiprocessor system characterized by switching an instruction operation depending on a case. 3. The multiprocessor system according to claim 2 , wherein when the instruction accesses the second register holding the lock / unlock information, the first register holding the lock / unlock state is simultaneously accessed. A multiprocessor system characterized by:

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