JP4009656B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a lithography technique suitable for manufacturing a semiconductor element such as a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor device .

  In a semiconductor device manufacturing process such as a large-scale integrated circuit, a lithography technique is used to form a fine pattern. Among them, the reduction projection exposure method using ultraviolet rays is actively used as a main force in the mass production process of semiconductor integrated circuit elements. The reduction projection exposure method is a method in which a pattern formed on a mask or reticle (hereinafter also referred to as “mask”) is imaged and transferred onto a semiconductor substrate using an imaging optical system.

  When the pattern exposure is completed, the substrate is taken out from the exposure apparatus, a resist pattern is formed by a predetermined development processing step, and further transferred to element manufacturing processing (impurity diffusion, film deposition, etching, etc.). When the predetermined process is completed, the substrate is returned to the exposure apparatus again, and another mask pattern is transferred for the next manufacturing process. In this way, generally, pattern transfer and processing are reciprocated ten or more times to complete a semiconductor element. In a production site where a pattern transfer process is performed, usually, a plurality of exposure apparatuses are installed, and a vacant apparatus is used each time.

  If the exposure apparatus to be used is changed, an error may occur in pattern superposition due to distortion (distortion based on aberration) of the imaging optical system of the exposure apparatus, which may cause deterioration in accuracy. In such a case, an exposure apparatus whose overlay error is within an allowable value is selected and used. Further, when particularly strict accuracy is required, the same exposure apparatus may be specified and used.

  When using an exposure apparatus, if a substrate is introduced after a manufacturing process for depositing a material (hereinafter simply referred to as “impurity material”) that may cause deterioration of the operating characteristics of the semiconductor element, exposure is performed after the pattern transfer is completed. Strict cleaning is performed on the device. Materials that cause impurity contamination include heavy metals containing noble metals such as platinum, piezoelectric ceramics such as PZT containing heavy metals, and alkali metals. For example, platinum is used as an electrode material of a capacitor of a semiconductor memory device, and PZT is used as a memory element material of a nonvolatile memory, for example. For example, the MOS transistor structure is formed at the initial stage of the semiconductor memory element, but the substrate is contaminated by the impurity material slightly remaining in the exposure apparatus, which may deteriorate the operating characteristics of the MOS transistor. .

  On the other hand, since the vacant apparatus is used as described above, the exposure apparatus used for the substrate after the impurity material is deposited is subsequently used for the substrate in the initial process stage of another lot. There are often. In this case, the above-described strict cleaning is performed. However, such cleaning is not only troublesome but also takes time, so that there is a problem that the process is delayed and the production efficiency is lowered.

An object of the present invention is to provide an improved method of manufacturing a semiconductor device that solves the above-described problems of the prior art and can avoid troublesome cleaning for removing impurity materials.

  The object of the present invention is to divide a plurality of exposure apparatuses into a first group of exposure apparatus groups and a second group of exposure apparatus groups, and to the substrate before the step of depositing the impurity material. This can be effectively solved by using an exposure apparatus in the first group and using an exposure apparatus in the second group for the substrate that has undergone the process. This is because the exposure apparatus to be used is divided into two parts before and after the impurity material deposition step, so that the substrate before the step is not contaminated and cleaning is unnecessary.

  If high accuracy is required for the pattern to be formed, the difference in distortion of the imaging optical system between the first group exposure apparatus and the second group exposure apparatus is maintained in order to maintain the overlay accuracy. It is desirable to set a combination such that is less than or equal to a predetermined value and use the combination for a series of lithography processes in the same lot.

  In addition, the object of the present invention is to use an exposure apparatus provided with two sample stands on which a substrate is placed, wherein one sample stand is for a substrate before impurity material deposition, and the other sample stand is an impurity material. This can be effectively solved by using the substrate after deposition. This is because the contamination is mainly caused by the impurity material remaining on the sample stage. Therefore, the contamination can be prevented by separating the sample stage before and after the impurity material deposition.

  According to the present invention, troublesome cleaning for removing impurity materials can be avoided in a lithography process using an exposure apparatus, so that the production efficiency of semiconductor element manufacturing can be increased. Impurity contamination can be avoided by eliminating the need for cleaning, and further, deterioration in overlay accuracy of circuit patterns formed in each process can be suppressed, so that high-performance semiconductor elements can be manufactured with high yield. it can.

  The exposure method and exposure apparatus according to the present invention will be described below in more detail with reference to some embodiments shown in the drawings. 3 and FIGS. 6 to 10 indicate the same object, the same process, the similar object, and the similar process.

<Example 1>
The exposure method of the present invention was applied to the manufacture of a large-scale integrated circuit device using a 256 megabit dynamic random access memory (hereinafter referred to as “DRAM”) having a chip size of 20 mm square. Platinum was used as the wiring electrode material of the DRAM, and a minimum design dimension of 0.25 μm was adopted.

  The implemented exposure method will be described with reference to the process flow chart shown in FIG. First, a plurality of exposure apparatuses were provided, which were divided into two groups, a first group and a second group. Then, the mask pattern is transferred using the exposure apparatus in the first group (step 11). Next, the transferred circuit pattern is processed using a manufacturing apparatus (step 12). Subsequently, the next process of manufacturing is performed (step 13). As a result of the treatment, a material made of heavy metals (platinum in the present embodiment) is deposited on the substrate, and whether or not the same material adheres. Transfer is performed using an exposure apparatus. If so, transfer is performed using a second group exposure apparatus (step 14).

  The second group exposure apparatus used will be described in detail later, but is combined with the first group exposure apparatus so that the overlay error due to distortion is not more than a predetermined value (allowable value). Note that the semiconductor elements to be manufactured are not highly integrated as in the case of the present embodiment, and even if the overlay accuracy is deteriorated due to the distortion error that the exposure apparatus normally has, the overlay error in the semiconductor element manufacturing process is acceptable. In the case where it is sufficiently within the overlay error range, the exposure apparatus can be arbitrarily taken out from the first group and the second group and used without selecting a combination.

  After step 14, the circuit pattern is processed using the manufacturing apparatus (step 15), and the process proceeds to the next step. A second group exposure apparatus is used for pattern transfer in the subsequent steps.

  In order to set a combination of the first group exposure apparatus and the second group exposure apparatus, the process shown in FIG. 2 was performed using a distortion measurement apparatus. An exposure apparatus to be measured is selected from the plurality of exposure apparatuses installed (step 1), and distortion of the apparatus is measured (step 2). A result is memorize | stored in a measuring apparatus (process 3).

  Next, for the exposure apparatus used in step 11 of FIG. 1, it is determined whether or not the measurement has already been completed. If the measurement has not been completed, the measurement is performed and the value is stored. If it has already been measured, the stored distortion value is read (step 4). The read value is compared with the values of other exposure apparatuses, and a combination of exposure apparatuses in which the overlay error due to distortion is within an allowable range is determined (step 5).

  Distortion was measured using a well-known method. That is, in this measurement method, a substrate coated with a photosensitive resin is placed on a precise substrate stage having a position measuring means using a laser interferometer, and placed at the center of the exposure field corresponding to the optical axis of the imaging optical system. The projected measurement reference pattern image is exposed to a large number of measurement positions on the substrate by stepping driving the substrate stage. Next, a large number of reference pattern images for measurement are collectively exposed so as to be close to the measurement reference pattern at each measurement position in the exposure field, and measurement is performed on the measurement reference pattern position at each measurement position in the exposure field after development processing. The relative position of the reference pattern is obtained, and the difference between the relative positions is set as a distortion error.

  FIG. 3 shows the configuration of the exposure apparatus employed in this embodiment. Since this configuration is general, a detailed description is avoided, but the outline is as follows. The light emitted from the light source 31 illuminates the mask 36 via the fly-eye lens 32, the condenser lenses 33 and 35, and the mirror 34. Immediately after the fly-eye lens 32, an illumination system stop 30 that defines the shape of the illumination light source is provided.

  On the mask 36, a pellicle 37 (an extremely thin transparent film) is provided to prevent pattern transfer failure due to adhesion of foreign matter. The pattern drawn on the mask 36 is projected onto a wafer 39 that is a sample substrate via a projection lens 38. The mask 36 is placed on the mask stage 48 controlled by the mask position control means 47, and the center thereof and the optical axis of the projection lens 38 are accurately aligned.

  The wafer 39 is vacuum-sucked on the sample stage 40. The sample stage 40 is installed on a Z stage 41 that can move in the optical axis direction of the projection lens 38, that is, the Z direction, and the Z stage 41 is installed on an XY stage 42. Since the Z stage 41 and the XY stage 42 are driven by the respective driving means 43 and 44 in accordance with a control command from the main control device 49, they can be moved to a desired exposure position. The position is accurately monitored by the laser length measuring device 45 as the position of the mirror 46 fixed to the Z stage 41. Further, the surface position of the wafer 39 is measured by the focal position detection means. By driving the Z stage 41 according to the measurement result, the surface of the wafer 39 can be made to coincide with the imaging surface of the projection lens 38.

  The exposure apparatus A in the first group and the exposure apparatus B in the second group are obtained as a result of measuring a distortion error by dividing the exposure apparatus into a first group and a second group. It was found that the difference in distortion was minimized. In this embodiment, in order to manufacture the DRAM, the tolerance for overlay error was set to 85 nm. On the other hand, in the combination of the exposure apparatuses A and B, the maximum distortion difference was 65 nm. This value was smaller than the allowable amount and within a desired range.

  From the above results, in this embodiment, the exposure apparatus A was used in the lithography process before the platinum deposition process, and the exposure apparatus B was used in the lithography process after the platinum deposition process. Using exposure apparatuses A and B, a DRAM was manufactured as follows. FIG. 4 shows a cross-sectional structure of the DRAM in each process.

  First, as shown in FIG. 4a, a P-type Si semiconductor 71 was used as a substrate, and an element isolation region 72 was formed on the surface thereof. Next, a word line 73 having a structure in which polycrystalline silicon having a thickness of 150 nm and silicon oxide having a thickness of 200 nm is deposited is formed, and further, silicon oxide having a thickness of 150 nm is deposited by chemical vapor deposition. The side spacers 74 of silicon oxide were formed on the side walls of the word lines by processing in the lateral direction. Next, an n diffusion layer 75 was formed.

  Subsequently, as shown in FIG. 4B, a data line 76 made of polycrystalline silicon was formed. In addition, the material of the data line 76 can be refractory metal silicide or a deposited film thereof. Next, platinum was deposited to form a film, and the film was processed to form a storage electrode 78 as shown in FIG. 4c. Thereafter, tantalum pentoxide was deposited, and a capacitor insulating film 79 was formed. In addition, the material of the capacitor insulating film 79 may be silicon nitride, silicon oxide, ferroelectric, or a composite film thereof. Subsequently, a plate electrode 80 was formed by depositing a conductor made of polycrystalline silicon. In addition, the material of the plate electrode 80 can be a low-resistance conductive material such as a refractory metal, a refractory metal silicide, Al, or Cu.

  Next, as shown in FIG. 4d, the wiring 81 was formed. Thereafter, the DRAM was completed using a normal wiring layer forming process and a passivation process.

  FIG. 5 shows a pattern of a memory portion formed by lithography based on the exposure method in the manufacturing process of such a DRAM. Two types of patterns were adopted, and two types of DRAMs with different patterns were manufactured. FIG. 5a shows the first pattern. In the figure, 84 is an active region composed of two transistors, 86 is a pattern of electrode extraction holes, storage electrodes 78 are arranged on both sides of the active region 84, and word lines 73 and data lines 76 are arranged in an intersecting manner. Has been.

  FIG. 5b shows the second pattern. In the figure, an active region 84 is formed in a rectangular shape.

  In the lithography process in this element manufacturing process, first, the exposure apparatus A is used in the lithography process prior to the process of laminating materials that may cause impurity contamination (pattern processing of the storage electrode 78 using platinum). In the lithography process, the mask pattern was transferred using the exposure apparatus B.

  As a result of measuring the overlay error between the pattern formed in the process before depositing platinum (heavy metals) and the pattern formed in the process after depositing heavy metals using a predetermined method, the above desired overlay is obtained. It was found that accuracy (85 nm) was obtained. Furthermore, as a result of measuring the characteristics of the element manufactured by the above method by a predetermined method, it was confirmed that there was no influence of impurity contamination and that the element characteristic variation in the wafer substrate surface was small.

  The exposure method described above is not limited to the DRAM, and can naturally be applied to the manufacture of various other semiconductor elements. Impurity contamination of heavy metals can be avoided and a desired pattern can be transferred with a desired overlay accuracy, so that a high-performance element can be manufactured with a high yield.

<Example 2>
In this embodiment, first, seven distortions of the exposure apparatuses C, D, E, F, G, H, and I were measured by the same method as in the first embodiment. As a result, it was found that the maximum difference in distortion measurement values between the three exposure apparatuses C, D, and E was 70 nm, which is an allowable value of 85 nm or less for the overlay error. In the following, these three units were used as the former group. Similarly, the maximum value of the difference in distortion measurement values between the four exposure apparatuses F, G, H, and I was 70 nm or less. In the following, these four units were designated as “B” group. The maximum value of the difference in distortion measurement values between the first group exposure apparatus and the second group exposure apparatus was 90 nm, which was more than the allowable amount of overlay deviation. Therefore, in the manufacturing process of the semiconductor device in this embodiment, only the exposure device in the former group or only the exposure device in the second group is used for the transfer of the high-precision pattern designed by using the minimum processing dimension. It was decided.

  In addition, when comparing the number of lithography processes before depositing a material containing heavy metals with the number of lithography processes after the process of depositing materials containing heavy metals, it was found that the number of the former processes was larger. . From the above, in the former group, the exposure apparatuses C and D are used in the lithography process before the process of depositing the material containing heavy metals, and the exposure apparatus E is used in the lithography process after the process of depositing the material containing heavy metals. It was decided to. In the second group, the exposure apparatuses F and G are used in a lithography process before the process of depositing the material, and the exposure apparatuses H and I are used in a lithography process after the process of depositing the material.

  In other words, in the former group, the exposure apparatuses C and D are the first group, the exposure apparatus E is the second group, and in the second group, the exposure apparatuses F and G are the first group, and the exposure apparatuses H and I are the second group. It becomes a device.

  In the second group, it was desirable to increase the number of exposure apparatuses used in the lithography process before the process of depositing the material. When the stage is used in the lithography process after the process of depositing the above materials, the processing capacity of the latter is one third of that of the former, and the difference in the processing capacity is larger than the difference in the number of lithography processes. In the example, two units were used.

  Table 1 shows the relationship between the main lithography process and the used exposure apparatus in this example.

表１において、転写するパターンの内、素子分離、ワード線、データ線コンタクト、データ線、蓄積電極、蓄積電極取り出し孔、配線１、コンタクトの各パターン幅を最小加工寸法とした。従って、これらは、要求重ね合せ精度が最も厳しい。また、リセスアレー、配線２のパターンは、最小加工寸法よりも大きな寸法としたので、要求重ね合せ精度は上記パターンよりも緩い。

In Table 1, among the patterns to be transferred, each pattern width of element separation, word line, data line contact, data line, storage electrode, storage electrode take-out hole, wiring 1 and contact is defined as the minimum processing dimension. Therefore, they have the strictest required overlay accuracy. Further, since the pattern of the recess array and the wiring 2 is larger than the minimum processing dimension, the required overlay accuracy is looser than the above pattern.

  When the former pattern using the minimum processing dimension is transferred, the above-described exposure device in the same group is used in order to suppress deterioration in overlay accuracy. Also, since the required overlay accuracy is lower than the above pattern at a pattern size larger than the minimum processing size and there is a margin in overlay accuracy, exposure of the latter pattern transfer is performed to suppress a decrease in production efficiency (throughput). Classify the exposure apparatus for lithography process before the process of depositing heavy metals and the exposure apparatus for lithography process after the process of depositing heavy metals, without considering the distortion difference between apparatuses, and use them separately. It was.

  In the example of the first lot (Lot- # 1) shown in Table 1, the exposure apparatus C of the former group is used for pattern transfer of each layer of element isolation, word line, data line contact and data line, The exposure apparatus E of the former group was used for pattern transfer of each layer of the electrode extraction hole, the wiring 1 and the contact.

  In the example of the second lot (Lot- # 2), the group exposure apparatus G is used for element separation, word line, data line contact, and pattern transfer of each layer of the data line. The group B exposure apparatus H was used for pattern transfer of each layer, and the group B exposure apparatus I was used for pattern transfer of each layer of the wiring 1 and the contact.

  Further, in the pattern transfer of the recess array and the wiring 2, the required overlay accuracy is looser than the above pattern and is 120 nm or less, and the required overlay accuracy can be sufficiently achieved even if the maximum distortion difference (90 nm) occurs. Therefore, for pattern transfer of the recess array, the exposure apparatus C was used in Lot- # 1, and the exposure apparatus F was used in Lot- # 2. For the pattern transfer of the wiring 2, the same exposure apparatus E was used for both Lot- # 1 and Lot- # 2.

  As described above, each exposure apparatus was assigned to each lithography process to manufacture a semiconductor element. As a result of measuring the overlay error between the pattern formed in the process before depositing heavy metals and the pattern formed in the process after depositing heavy metals using a predetermined method for the manufactured element, the error is Was within the above desired value (85 nm). Furthermore, as a result of measuring the characteristics of the element by a predetermined method, it was confirmed that there was no influence of impurity contamination and that the element characteristic variation in the wafer substrate surface was small.

<Example 3>
A new mechanism was introduced into the exposure apparatus to manufacture a large-scale integrated circuit element using a 256 megabit DRAM having a chip size of 20 mm square. Platinum was used as the wiring electrode material of the DRAM, and 0.25 μm was adopted as the minimum design dimension.

  FIG. 6 shows an exposure apparatus of the present invention. In the figure, reference numerals 40-1 and 40-2 denote a first sample stage and a second sample stage, respectively, of two sample stands, and 41a denotes two sample stands 40-1 and 40-2. A Z stage 42a, which is installed and driven, indicates an XY stage in which the Z stage 41a is installed and the sample stage and the stage are driven. The other structure is the same as that shown in FIG.

  The sample stage 40-1 was used in the lithography process before depositing platinum on the wafer, and the sample stage 40-2 was used in the lithography process after depositing platinum on the wafer. The wafer 39 is vacuum-sucked on the sample tables 40-1 and 40-2. Although not shown, the wafer transfer system for taking out the wafer 39 from the wafer cassette and placing it on the sample tables 40-1 and 40-2 is also divided into two systems (first and second systems respectively) for each sample table. ) To separate the portion that contacts the wafer before the platinum adheres and the portion that contacts the wafer that the platinum adheres to.

A process flow according to the present invention is shown in FIG. After the previous step is completed, it is determined whether or not platinum is attached to the substrate (step 21). When the platinum is not attached to the substrate, the first sample stage 40-1 and the first substrate The mask pattern is transferred using the transfer system (step 22), and when the platinum adheres to the substrate, the mask pattern is transferred using the second sample stage 40-2 and the second substrate transfer system ( Step 23). After the transfer was completed, the circuit pattern was processed using a predetermined manufacturing apparatus (step 24).
As described above, by separately using the sample bases 40-1 and 40-2, it is possible to suppress impurity contamination on the substrate before heavy metals are deposited on the substrate. Further, since the same imaging optical system is used, the distortion does not affect the overlay accuracy deterioration, and therefore a desired overlay accuracy can be obtained.

<Example 4>
The structure of the exposure apparatus of the present embodiment is the same as that shown in FIG. 3, but it is replaceable so that the sample stage 40 can be removed. Also in this example, a large-scale integrated circuit element using a 256 megabit DRAM having a chip size of 20 mm square was manufactured. Platinum was used as the wiring electrode material of the DRAM, and 0.25 μm was adopted as the minimum design dimension.

  Two sample stands having equivalent performance are prepared as sample stands, one is used in a lithography process before depositing heavy metals on the substrate, and the other is lithography after depositing heavy metals on the substrate. Used in the process. As a result, it was possible to suppress impurity contamination on the substrate before heavy metals were deposited on the substrate. In this method, since the same imaging optical system is used, the distortion does not affect the deterioration of the overlay accuracy, and a desired overlay accuracy can be obtained.

<Example 5>
The exposure apparatus of the present embodiment is provided with a sample stage exchange apparatus for exchanging a removable sample stage and two wafer transfer systems. In FIG. 8, reference numeral 53 denotes a sample stage exchange device for exchanging the sample stage 40-1 and the sample stage 40-2 in accordance with the transfer pattern. In FIG. 9, reference numerals 57-1 and 57-2 denote two wafer transfer systems, and 56 denotes a substrate cassette table.

  The sample stage 40-1 was used for a wafer on which a material containing heavy metals was not attached, and the sample stage 40-2 was used for a wafer on which a material containing heavy metals was attached. A function for controlling the operation of the sample stage changing device 53 is added to the main control device 49. In response to an instruction from the main controller 49, the sample stage changing device 53 transfers the pattern onto the wafer before the material containing the heavy metal is attached, or the wafer after the material containing the heavy metal is attached. Depending on whether the pattern is transferred to the top, the sample stage is exchanged.

  The type of transfer pattern, process name, etc. are set on the main controller 49, and the sample stage is selected according to the designated conditions. The sample stage that has been placed on the Z stage 41 is removed, and the selected sample stage is automatically placed on the Z stage 41.

  Further, as shown in FIG. 9, two wafer transfer systems 57-1 and 57-2 are used for the sample tables 40-1 and 40-2, respectively.

  In the above description, the case where each of the sample bases 40-1 and 40-2 is one has been described. When a foreign object adheres to one sample stage and cleaning becomes necessary, the other sample stage is immediately used to prevent delay of the process due to the sample stage cleaning.

<Example 6>
In the present embodiment, the same exposure apparatus as in the fifth embodiment is used, and information relating to the wafer is input to the main controller 49 (see FIG. 8) of the apparatus. Thus, the apparatus 49 determines whether or not the wafer contains a material containing heavy metals, and the sample stage exchanging apparatus 53 so as to automatically select and use a predetermined sample stage and wafer transfer system. Also, the wafer transfer systems 57-1 and 57-2 are controlled.

  The process flow of the present invention is shown in FIG. First, an identifier related to the wafer is recorded on the wafer. A character string representing a lot name, lot number, wafer number, etc. was used as an identifier. The identifier may be recorded on the wafer cassette as well as on the wafer, and the wafer can be managed using the wafer cassette identifier. In addition to a character string, a barcode or the like can be used. The character string is read using an image input means using a CCD camera and input to the exposure apparatus (step 25). The main controller 49 uses the input identifier data to determine whether or not a material containing heavy metals is attached to the substrate, and the combination of the first sample stage and the first substrate transport system or the first It is determined which one of the combination of the sample stage 2 and the second substrate transport system is used (step 21). In accordance with the determination, a predetermined sample stage is placed on the stage 41 (steps 26 and 27). The wafer is placed on the same sample stage by a predetermined substrate transfer system, and the mask pattern is transferred (steps 22 and 23). Subsequently, the circuit pattern is processed by the manufacturing apparatus (step 24).

  In addition to the above, the input of identifier data to the main control device 49 can be performed via a network device 55 (see FIG. 8) provided outside the exposure device. A control device (not shown) for managing lot progress is connected to the network device 55. The progress management control device grasps the process progress state of each wafer, and notifies the exposure device through the network device 55 of information relating to the processing history of the lot to be exposed and the substrate. In addition, the process processor may input such information and information on which sample stage and substrate transport system are used to the exposure apparatus.

The process flowchart for demonstrating the 1st Example of the exposure method which concerns on this invention. The process flowchart for demonstrating selection of the exposure apparatus used in 1st Example. FIG. 2 is an arrangement configuration diagram for explaining an exposure apparatus used in the first embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor element in a 1st Example. The element top view which shows the main patterns of the semiconductor element used by description of FIG. FIG. 6 is an arrangement view of an exposure apparatus for explaining a third embodiment of the present invention. The process flowchart for demonstrating the 3rd Example of this invention. FIG. 10 is an arrangement view of an exposure apparatus for explaining a fifth embodiment of the present invention. The sample stand for demonstrating the 5th Example of this invention and the arrangement block diagram of its periphery. The process flowchart for demonstrating the 6th Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 31 ... Light source, 36 ... Mask, 38 ... Projection lens, 39 ... Wafer, 40 ... Sample stand, 41 ... Z stage, 42 ... XY stage, 48 ... Mask stage, 49 ... Main controller, 53 ... Sample stand exchange device, 55 ... Network device, 56 ... Substrate cassette stand, 57 ... Substrate transport system, 73 ... Word line, 76 ... Data line, 78 ... Storage electrode.

Claims (1)

(A) performing a plurality of lithography steps on the wafer using a plurality of exposure apparatuses belonging to the first group;
After the step (a), in response to whether or not a material containing heavy metals is adhered on the wafer, if not, using a plurality of exposure apparatuses belonging to the first group, A step (b) of performing a plurality of lithography steps using a plurality of exposure apparatuses belonging to a second group different from the first group if a plurality of lithography steps are performed and adhered; A method for manufacturing a semiconductor device, comprising:

Images