JP4016928B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

Since silicon carbide (SiC) can form an insulating film made of silicon dioxide (SiO ₂ ) by thermal oxidation, a high breakdown voltage insulated gate field effect transistor (MOSFET) in which such SiO ₂ is applied to the gate insulating film can be obtained.

  However, since there are a large number of interface states (traps) at the MOS interface formed by the conventional thermal oxidation method, the channel conductance (channel mobility) is very small and the on-time loss increases, that is, the on-resistance There was a problem that would increase. In order to improve the quality of the MOS interface, for example, Non-Patent Document 1 discloses a method in which a wafer is annealed in a nitrogen monoxide (NO) atmosphere to form a nitridation process on the MOS interface when forming a gate insulating film.

Non-Patent Document 2 discloses a method of annealing a wafer in an oxygen dinitride (N ₂ O) atmosphere, and oxygen (O ₂₎ before high-temperature annealing at 1200 ° C. or after nitridation after the formation of the SiO ₂ insulating film. It is reported that the quality of the MOS interface can be improved only when the SiO ₂ insulating film is directly formed in the N ₂ O atmosphere without performing the oxidation in the atmosphere.

G.Y.Chung et al., "Improved Inversion Channel Mobility for 4H-SiC MOSFETs Following High Temperature Anneals in Nitric Oxide", Electron Device Letters, VOL. 22 (2001) No. 4, pp. 176-178 L.A. Lipkin et al., "N2O Processing Improves the 4H-SiC: SiO2 Interface," Materials Science Forum Vols 389-393 (2002) pp. 985-988

  NO gas is highly toxic, and when mass production of silicon carbide MOSFETs, if annealing treatment under an NO atmosphere is used as a routine process, the introduction of incidental equipment such as a NO gas treatment device is indispensable, which increases the manufacturing cost. It was.

In addition, in order to obtain suitable device characteristics by the annealing process in the N ₂ O atmosphere disclosed in Non-Patent Document 2 or the direct oxynitriding method, a high-temperature heat treatment of 1200 ° C. or higher is required. Since a heat treatment apparatus having a special specification that is excellent and can withstand repeated high-temperature heat treatment is required, there is a problem in that the manufacturing cost increases as in the case of the annealing treatment in the NO atmosphere described above.

  Furthermore, there is a concern that impurities are taken into the wafer from the heat treatment apparatus during the wafer annealing process at a high temperature. This is because the reliability of the silicon carbide MOSFET is impaired due to such unintentional incorporation of impurities into the wafer.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a method for manufacturing a silicon carbide semiconductor device that is low in manufacturing cost and excellent in element characteristics.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes a thermal oxidation step of forming a silicon dioxide film on a wafer on which a silicon carbide layer is formed by thermal oxidation in an oxygen atmosphere, and a wafer on which the silicon dioxide film is formed. And a heat treatment step in which the silicon dioxide film formed in the thermal oxidation step and the heat treatment step has a total thickness of 2 nm to 50 nm. It is as follows.

  According to the method for manufacturing a silicon carbide semiconductor device of the present invention, the interface state at the MOS interface is remarkably reduced, so that the quality of the MOS interface is improved. As a result, the carbonization having excellent device characteristics while maintaining a low manufacturing cost. A silicon semiconductor device can be easily obtained.

Embodiment 1 FIG.
FIG. 1 shows an element structure of a silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device of the first embodiment of the present invention. As an example of the silicon carbide semiconductor device, a cross-sectional structure of an n-channel silicon carbide MOSFET is shown. Moreover, the manufacturing method of the silicon carbide semiconductor device of Embodiment 1 of this invention, specifically, the manufacturing method of n channel silicon carbide MOSFET, are shown in FIGS.

In the figure, 1 is an n-type (first conductivity type) substrate, 2 is a drift layer made of n-type (first conductivity type) silicon carbide, 3 is a p-type (second conductivity type) base region, and 4 is n The source region of the type (first conductivity type), 5 is a gate insulating film made of silicon dioxide (SiO ₂ ), 6 is a gate electrode, 7 is a source electrode, and 8 is a drain electrode.

  A method for manufacturing the silicon carbide semiconductor device of the first embodiment of the present invention will be outlined with reference to FIGS. First, a drift layer 2 made of n-type silicon carbide is formed on an n-type (first conductivity type) substrate 1 by an epitaxial crystal growth method (FIG. 2). For example, an n-type silicon carbide substrate is suitable as the n-type substrate 1.

  After the epitaxial crystal growth, a pair of p-type (second conductivity type) base regions 3 are formed by implanting impurities into portions of the drift layer 2 spaced apart by a predetermined distance using a resist as a mask. FIG. 3 shows a cross section of the element after removing the resist. Examples of the impurity that becomes p-type in the drift layer 2 include boron (B) and aluminum (Al).

  Further, an n-type (first conductivity type) source region 4 is formed by implanting impurities into each of the p-type base regions 3 using a resist as a mask. FIG. 4 shows a cross section of the element after removing the resist. Examples of the n-type impurity include phosphorus (P) and nitrogen (N).

  After the n-type and p-type impurity ions are implanted, if the wafer is annealed at a high temperature by a heat treatment apparatus, the implanted ions are electrically activated.

Subsequently, a gate insulating film 5 made of SiO _{2 is} formed on the entire surface of the wafer by thermal oxidation (FIG. 5), and after thermal oxidation, heat treatment is performed in an N ₂ O atmosphere. Since this process is a characteristic process in the present invention, it will be described in detail later.

  A gate electrode 6 is formed and patterned on the gate insulating film 5 (FIG. 6). The gate electrode 6 is patterned in such a shape that the pair of base region 3 and source region 4 are located at both ends, and the drift layer 2 exposed between the base regions 3 is located at the center.

  Further, the insulating film 5 on each source region 4 is removed by a lithography technique and an etching technique (FIG. 7), and after removal, a source electrode 7 is formed and patterned at a portion where the source region 4 is exposed on the surface (FIG. 8). ). When the drain electrode 8 is formed on the back side of the substrate 1, the main part of the element structure as shown in FIG. 1 is completed.

Next, the thermal oxidation step and the heat treatment step (annealing step) in an N ₂ O atmosphere after thermal oxidation, which are characteristic in the method for manufacturing a silicon carbide semiconductor device of the present invention, will be described in detail. 9 to 11 are diagrams showing the temperature profile in the reaction furnace in the thermal oxidation and the annealing process after the thermal oxidation for the purpose of forming the gate insulating film 5 described above.

  The thermal oxidation for forming the gate insulating film 5 and the annealing process after the thermal oxidation are performed by a common heat treatment apparatus. An example of such a heat treatment apparatus is a reaction furnace. In the following, description will be given by taking the case of using a reactor as an example.

First, the wafer after the formation of the base region 3 and the source region 4 is introduced into a reactor heated to about 700 ° C., and is subjected to thermal oxidation in an argon (Ar) atmosphere or a nitrogen (N ₂ ) atmosphere. Heat up until it reaches.

When the thermal oxidation temperature is reached, the inside of the reaction furnace is switched from an Ar atmosphere or N ₂ atmosphere to an oxygen (O ₂ ) atmosphere containing water vapor or an atmosphere containing only O ₂ , and this state is maintained for a predetermined time. In the process of thermal oxidation, the silicon carbide layer on the wafer surface is oxidized to form a gate insulating film 5 made of SiO ₂ . That is, the thermal oxidation portion is performed in the temperature profiles shown in FIGS.

The thermal oxidation may be performed in an atmosphere containing only O _{2 for the} first fixed time, and the remaining time may be performed in an O ₂ atmosphere containing water vapor, or vice versa.

After the thermal oxidation, the O ₂ atmosphere is switched to an Ar atmosphere or an N ₂ atmosphere, and the temperature is raised or lowered until reaching the temperature required for the annealing process in the next step, the N ₂ O atmosphere. This is because the heat treatment temperatures of the two are usually different. However, this step can be omitted when the temperatures of the two coincide. FIG. 9 shows the case where the thermal oxidation temperature is higher than the annealing temperature in the N ₂ O atmosphere, FIG. 10 shows the case where the thermal oxidation temperature is the same as the annealing temperature in the N ₂ O atmosphere, and FIG. Each temperature profile is shown when the temperature is lower than the annealing temperature in an N ₂ O atmosphere.

When the inside of the reaction furnace reaches a predetermined temperature, the Ar atmosphere or the N ₂ atmosphere is switched to the N ₂ O atmosphere, and the annealing process is started. The annealing treatment in the N ₂ O atmosphere is performed at a temperature of 950 ° C. or higher and 1150 ° C. or lower. In the annealing process at a temperature higher than 1150 ° C., a heat treatment apparatus having a special specification that is excellent in temperature controllability at a high temperature and that can withstand repeated heat treatment at a high temperature is indispensable. This is because there is a rising problem. The annealing time is preferably about 3 hours.

As a result of the oxynitriding of the MOS interface by the annealing process in the N ₂ O atmosphere, the interface state is greatly reduced. Note that, in the annealing process under the N ₂ O atmosphere, the formation of the gate insulating film 5 is continued by oxygen generated from the N ₂ O gas. Therefore, the layer thickness of the gate insulating film 5 is the sum of the amount formed during thermal oxidation and the amount formed during annealing in an N ₂ O atmosphere.

N 2 changeover _O at annealing ends in an atmosphere to N again Ar atmosphere or an N ₂ atmosphere a _{2 O} atmosphere, after an annealing treatment by holding tens minutes temperature, the wafer temperature was lowered to 700 ° C. Take it out of the reactor.

According to the annealing method described above, the interface state of the MOS interface is obtained by performing the annealing process in the N ₂ O atmosphere after the thermal oxidation of the silicon carbide layer on the wafer surface with the O ₂ gas at the time of forming the gate insulating film. As a result, the quality of the MOS interface is improved, and as a result, the device characteristics are improved while maintaining a low manufacturing cost.

FIG. 12 shows the gate characteristics of the silicon carbide MOSFET when annealing is performed at 1100 ° C. in an N ₂ O atmosphere after thermal oxidation with O ₂ gas and when such annealing is not performed. A silicon carbide MOSFET that has been annealed in an N ₂ O atmosphere has a larger drain current value and a steeper slope than a silicon carbide MOSFET without such annealing. Channel mobility mu _ch obtained from the linear region, whereas was annealed without silicon carbide MOSFET in 2.8 cm ² / Vs under _{N 2} O atmosphere, annealing treatment under _{N 2} O atmosphere In the silicon carbide MOSFET which implemented this, 18 cm ² / Vs, which is an improvement of about 6 times. This is because the interface state is nitrided by the annealing treatment in the N ₂ O atmosphere and becomes electrically inactive, so that the interface state density is reduced and the channel mobility is increased.

Furthermore, FIG. 13 shows the gate characteristics of the silicon carbide MOSFET when the annealing process is performed at 1150 ° C. in an N ₂ O atmosphere and when the annealing process is not performed. Channel mobility mu _ch obtained from the linear region, whereas was annealed without silicon carbide MOSFET in 2.8 cm ² / Vs under _{N 2} O atmosphere, annealing treatment under _{N 2} O atmosphere In the silicon carbide MOSFET which implemented this, 22 cm ² / Vs was improved about 8 times.

FIG. 14 shows the results of investigating the relationship between the film thickness of the gate insulating film 5 and the channel mobility when the annealing process is performed in an N ₂ O atmosphere and when the annealing process is not performed. As can be seen from FIG. 14, the channel mobility strongly depends on the presence or absence of the annealing treatment, but the annealing treatment was performed in an N ₂ O atmosphere when the thickness of the gate insulating film 5 was in the range of 20 nm to 50 nm. In this case, good device characteristics were obtained. The effect of the annealing treatment in the N ₂ O atmosphere depends on the film thickness of the gate insulating film 5, and when the gate insulating film 5 is 2 nm or more and 50 nm or less, a sufficient annealing treatment effect is exhibited, but the film outside the range Thickness does not provide a sufficient annealing effect. When the film thickness is greater than 50 nm, there is a problem that the effect of the annealing treatment in the N ₂ O atmosphere is not sufficiently exhibited, and when the film thickness is less than 2 nm, it is difficult to maintain a uniform film thickness, which is practical for device characteristics. This is because a non-negligible variation occurs.

Even in the annealing process under an N ₂ O atmosphere of 1150 ° C. or lower, the quality of the MOS interface can be improved by optimizing the thermal oxidation process conditions when forming the gate insulating film 5 and the process conditions during the annealing process, but 950 At a heat treatment temperature lower than 0 ° C., it is difficult to sufficiently improve the quality of the MOS interface even if annealing is performed in an N ₂ O atmosphere. This is because the heat treatment temperature is too low to obtain a sufficient annealing effect.

  As described above, according to the method for manufacturing a silicon carbide semiconductor device of the present embodiment, a thermal oxidation step of forming a silicon dioxide film on a wafer on which a silicon carbide layer is formed by thermal oxidation in an oxygen atmosphere, and the silicon dioxide film And a heat treatment step of heat-treating the wafer formed with a temperature of 950 ° C. to 1150 ° C. in an oxygen dinitride atmosphere, and the layer thickness of the silicon dioxide film formed by the thermal oxidation step and the heat treatment step Since the interface state of the MOS interface is remarkably reduced, the quality of the MOS interface is improved, and as a result, silicon carbide having excellent device characteristics while maintaining a low manufacturing cost. A semiconductor device can be easily obtained.

Embodiment 2. FIG.
15 and 16 show element structures of a silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device of the second embodiment of the present invention. As an example of the silicon carbide semiconductor device, a cross-sectional structure of an n-channel silicon carbide MOSFET is shown. In the figure, 9 indicates an n-type silicon carbide layer, and 10 indicates a depletion portion provided in the n-type silicon carbide 9, respectively.

  In contrast to the silicon carbide semiconductor device of the first embodiment, that is, the element structure shown in FIG. 1, the element structure that is the object of the method for manufacturing the silicon carbide semiconductor device of the second embodiment is as shown in FIGS. The difference is that n-type silicon carbide layer 9 is provided directly under gate insulating film 5, and depletion portion 10 exists in n-type silicon carbide layer 9 in contact with drift layer 2.

  The n-type silicon carbide layer 9 is formed by ion implantation of n-type impurities or n-type impurity into the wafer after the formation of the base region 3 and the source region 4 shown in the first embodiment, that is, the wafer shown in FIG. The silicon carbide layer is formed by a new epitaxial crystal growth method. It should be noted that the depletion portion 10 can be easily formed by masking a portion corresponding to the depletion portion 10 during ion implantation so that impurities are not ion-implanted. On the other hand, when employing epitaxial growth, after crystal growth of n-type silicon carbide layer 9 over the entire wafer surface, only n-type silicon carbide layer 9 or n-type silicon carbide layer 9 and depletion portion 10 are formed by lithography and etching techniques. An n-type silicon carbide region is formed by epitaxial growth only on the n-type silicon carbide layer 9 formed in a trench shape or in the region of the n-type silicon carbide layer 9 and the depletion portion 10. For the depletion region portion (depletion portion) 10 in which no channel is formed, the n-type layer 9 may or may not be formed.

  When n-type silicon carbide layer 9 is formed by ion implantation, high-temperature annealing is performed. This is because the implanted ions are electrically activated by high-temperature annealing. Note that the pre-process and post-process other than the above-described characteristic steps are the same as those in the first embodiment, and are omitted.

15 or 16, a silicon carbide MOSFET in which annealing is performed at 1100 ° C. in an N ₂ O atmosphere after thermal oxidation with O ₂ gas, and has an extremely excellent channel mobility of 45 cm ² / Vs. Device characteristics were obtained. By using the n region in the channel portion, the influence of electrons passing through the channel from the interface state (trap) existing at the MOS interface is reduced, and further, the MOS is processed by annealing at 1100 ° C. in an N ₂ O atmosphere. This is because high channel mobility can be achieved as a result of the reduction of the interface state density of the interface.

  In the above description, the silicon carbide MOSFET is taken as an example of a silicon carbide semiconductor device. However, the silicon carbide MOSFET shown in the present embodiment has an element structure in which an insulating film is formed on a silicon carbide layer in another silicon carbide semiconductor device. It goes without saying that the same effect can be obtained by applying the manufacturing method.

1 is a cross sectional view of a silicon carbide semiconductor device manufactured by the method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a diagram showing a part of the method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a diagram showing a part of the method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a diagram showing a part of the method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a diagram showing a part of the method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a diagram showing a part of the method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a diagram showing a part of the method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. 5 is a diagram showing a part of the method for manufacturing the silicon carbide semiconductor device of the first embodiment. It is a figure showing the temperature profile in the reaction furnace in the thermal oxidation which is a part of manufacturing method of the silicon carbide semiconductor device of Embodiment 1, and the annealing process after thermal oxidation. It is a figure showing the temperature profile in the reaction furnace in the thermal oxidation which is a part of manufacturing method of the silicon carbide semiconductor device of Embodiment 1, and the annealing process after thermal oxidation. It is a figure showing the temperature profile in the reaction furnace in the thermal oxidation which is a part of manufacturing method of the silicon carbide semiconductor device of Embodiment 1, and the annealing process after thermal oxidation. It is a figure which shows the element characteristic of silicon carbide MOSFET produced by the manufacturing method of the silicon carbide semiconductor device of Embodiment 1. FIG. It is a figure which shows the element characteristic of silicon carbide MOSFET produced by the manufacturing method of the silicon carbide semiconductor device of Embodiment 1. FIG. FIG. 6 is a diagram showing a relationship between a layer thickness of a gate insulating film and channel mobility in the silicon carbide MOSFET manufactured by the method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. 11 is a cross sectional view of a semiconductor device manufactured by the method for manufacturing the silicon carbide semiconductor device of the second embodiment. FIG. 11 is a cross sectional view of a semiconductor device manufactured by the method for manufacturing the silicon carbide semiconductor device of the second embodiment.

Explanation of symbols

1 n-type (first conductivity type) substrate, 2 n-type (first conductivity type) silicon carbide drift layer, 3 p-type (second conductivity type) base region, 4 n-type (first conductivity type) ) Source region, 5 gate insulating film made of silicon dioxide (SiO ₂ ), 6 gate electrode, 7 source electrode, 8 drain electrode, 9 n-type silicon carbide layer, 10 depletion part.

Claims (8)

A method for manufacturing a silicon carbide semiconductor device having a silicon carbide layer,
A thermal oxidation step of forming a silicon dioxide film on the wafer on which the silicon carbide layer is formed by thermal oxidation under an oxygen atmosphere;
A heat treatment step of heat-treating the wafer on which the silicon dioxide film is formed at a temperature of 950 ° C. or higher and 1150 ° C. or lower in an oxygen dinitride atmosphere,
A method for manufacturing a silicon carbide semiconductor device, wherein a total thickness of silicon dioxide films formed in the thermal oxidation step and the heat treatment step is 2 nm or more and 50 nm or less. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the conductivity type of the silicon carbide layer is n-type. A method for manufacturing a silicon carbide semiconductor device having a silicon carbide layer,
Epitaxially growing a drift layer made of silicon carbide of the first conductivity type on a substrate of the first conductivity type;
Forming a pair of second conductivity type base regions spaced apart by a predetermined distance in the drift layer by ion implantation of impurities;
Forming each source region of the first conductivity type in each of the base regions by ion implantation of impurities;
A thermal oxidation step of forming a gate insulating film made of silicon dioxide on the wafer by thermal oxidation in an oxygen atmosphere;
A heat treatment step of heat-treating the wafer after forming the gate insulating film at a heat treatment temperature of 950 ° C. to 1150 ° C. in an oxygen dinitride atmosphere;
Forming a gate electrode in a region where the drift layer is located at a central portion on the gate insulating film and each base region and each source region are located at both ends, and
A method for manufacturing a silicon carbide semiconductor device, wherein a total thickness of a gate insulating film formed in the thermal oxidation step and the heat treatment step is 2 nm or more and 50 nm or less. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein water vapor is contained in an oxygen atmosphere during the thermal oxidation. 4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a nitrogen atmosphere or an argon atmosphere is used when the processing temperature is changed from the processing temperature in the thermal oxidation step to the heat treatment step. Forming a first conductivity type impurity region by ion implantation of impurities in each source region, each base region, and each drift layer located between each base region facing the gate electrode through the gate insulating film; A method for manufacturing a silicon carbide semiconductor device according to claim 3. Forming a first conductivity type silicon carbide layer by epitaxial crystal growth on each source region, each base region, and each drift layer located between each base region facing the gate electrode through the gate insulating film; A method for manufacturing a silicon carbide semiconductor device according to claim 3. 8. The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide semiconductor device is an insulated gate field effect transistor including a gate insulating film made of the silicon dioxide film. Method.

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