JP4018961B2 - Data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing device such as a router, a LAN switch, or a data terminal device connected to a LAN, and more particularly to memory control related to data writing / reading when data received from a LAN is buffered and transmitted to another device. The present invention relates to a data processing apparatus involving
[0002]
[Prior art]
A conventional network device accumulates IP packets received from a LAN such as Ethernet (R) in a buffer memory, and after the CPU reads and confirms the destination, it writes it again in the buffer memory and transmits it to the destination.
[0003]
FIG. 16 shows a schematic configuration of a conventional network device. The network device is connected to the LAN through a physical layer interface (PHY) 1 such as a connector, and buffering when receiving or transmitting an IP packet flowing on the LAN is performed by the LSI internal block 2. The CPU 3 controls reception / transmission of IP packets in the LSI internal block 2. The network device shown in FIG. 16 is configured to be connectable to three networks, LAN1 to LAN3, and is physically connected by connectors 1a, 1b, and 1c. In the LSI internal block 2, network interfaces 4, 5, and 6 are installed for the connectors 1a, 1b, and 1c (LAN1 to LAN3). Buffer memories 7, 8, and 9 are individually provided for the network interfaces 4, 5, and 6. The buffer memories 7, 8, and 9 are each composed of a reception buffer memory and a transmission buffer memory.
[0004]
For example, when packet data received from the LAN 1 is sent to the LAN 2, the packet data received from the LAN 1 is stored in the reception buffer memory of the buffer memory 7, and then read out from the reception buffer memory by the CPU 3 to be buffered in the LAN 2. 8 is sent to the LAN 2 by writing to the transmission buffer memory.
[0005]
In addition, there is a technique for securing a packet area for reception by providing a plurality of reception packet buffers for managing packet areas on a plurality of main memories having different lengths, reducing overhead on software (for example, Patent Document 1).
[0006]
[Patent Document 1]
JP 2002-244517 A (FIG. 2)
[0007]
[Problems to be solved by the invention]
However, in the above-described conventional technology, the dedicated reception buffer memory and the transmission buffer memory are provided corresponding to each LAN 1-3 connected to the network device, so that the CPU 3 receives the packet from the reception buffer memory. There has been a problem that it takes time to transfer data such as reading data and writing it again to the buffer memory for transmission.
[0008]
In addition, a dedicated reception buffer memory and transmission buffer memory are provided corresponding to each LAN 1-3 connected to the network device. However, as a product, only one channel may be used. In this case, there is a problem that the buffer memory for two channels is wasted.
[0009]
Furthermore, if the number of LANs connected to network equipment increases, the buffer memory must be increased accordingly. If the CPU processing speed is not sufficient, the reception buffer memory must be increased. However, the buffer memory tends to increase.
[0010]
Japanese Patent Application Laid-Open No. 2002-244517 has one input communication means and one output communication means, and does not have a plurality of communication means both for input and output. For this reason, it has not been possible to cope with the above problem in the case where a plurality of communication means serving both for input and output are provided.
[0011]
The present invention has been made in view of the above circumstances, and can suppress the increase of the buffer memory, reduce the cost, reduce the size of the apparatus, and perform transmission from the reception buffer memory by the CPU. An object of the present invention is to provide a data processing apparatus that eliminates the work of transferring data to a buffer memory and realizes high-speed processing.
[0012]
[Means for Solving the Problems]
  The present inventionA plurality of network interface means for interfacing with a LAN; a shared buffer memory accessed by the plurality of network interface means for storing data and reading the stored data; and for accessing the shared buffer memory A virtual memory address is converted into an actual real memory address of the shared buffer memory, and an address range of a virtual memory address used for each network interface unit is divided, and the divided address range is used for reception. An address conversion table in which virtual memory addresses are set separately for transmission and a virtual memory address is input from the network interface means to access the shared buffer memory Using said address conversion table converts the virtual memory addresses into real memory addresses, and a control means for accessing the shared buffer memory of the translated real memory address.
[0013]
  The present invention also providesNetwork interfaceSpecified by meansVirtual memoryRead data from address by address conversion tableReal memory addressConverted toNetwork interfaceRegardless of the address specified by the means, the control meansShared bufferIt is configured to be able to arbitrarily set which storage area of memory to read,Shared bufferThe data can be read without performing the process of changing the data in the memory.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
  The first aspect of the present invention is:A plurality of network interface means for interfacing with a LAN; a shared buffer memory accessed by the plurality of network interface means for storing data and reading the stored data; and for accessing the shared buffer memory A virtual memory address is converted into an actual real memory address of the shared buffer memory, and an address range of a virtual memory address used for each network interface unit is divided, and the divided address range is used for reception. An address conversion table in which virtual memory addresses are set separately for transmission and a virtual memory address is input from the network interface means to access the shared buffer memory Using said address conversion table converts the virtual memory addresses into real memory addresses, and intended to comprise a control means for accessing the shared buffer memory of the translated real memory address.
[0015]
  According to the data processing apparatus configured as described above,Network interfaceSpecified by meansVirtual memoryRegardless of the address, the data is actually sent by the control means.Shared bufferWhich memoryAccess areaCan be set arbitrarily,Network interfaceSame from meansVirtual memoryEven if an address is specifiedShared bufferThere is no need to transfer data in memory,Shared bufferMemory can be used effectively and processing can be performed at high speed.
[0017]
  Also memoryWhen writing toNetwork interfaceMeans usedVirtual memoryDifferent from addressVirtual memoryUsing addressNetwork interfaceThe means can specify the read address, and can read the data from the same address without performing the process of moving the data in the memory,Shared bufferMemory can be used effectively and processing can be performed at high speed.
[0020]
  Of the present inventionSecond aspectIsWhen the real memory address corresponding to the virtual memory address is not set in the address conversion table, the control means accesses the minimum address that is an empty area in the real memory address of the shared buffer memory.
[0021]
  According to the data processing apparatus configured as described above,Network interfaceSpecified by meansVirtual memoryRegardless of the address, the data is actually sent by the control means.Shared bufferWhich memoryAccess areaCan be set arbitrarily,Network interfaceSame from meansVirtual memoryEven if an address is specifiedShared bufferThere is no need to transfer data in memory,Shared bufferMemory can be used effectively and processing can be performed at high speed.
[0022]
  Also,Network interfaceSpecified by meansVirtual memoryAddress to actually store the dataShared bufferMemoryReal memoryWhen converting to an address, it is possible to cope with both software and hardware according to the use environment, so that address conversion with high utilization can be realized.
[0023]
  Of the present inventionThird aspectIsFirst aspectIn the data processing apparatus ofShared bufferIn the memory, the data storage area is divided into units smaller than the maximum data amount transferred by packet communication.
[0024]
When the data storage area is configured with a capacity that can accommodate the maximum data amount transferred by packet communication as in the conventional case, when storing data with a data amount smaller than the maximum data amount actually transferred by packet communication, the storage area Unnecessary empty space was generated in the memory, and the memory utilization efficiency was poor.
[0025]
Therefore, according to the present invention, by dividing the data storage area into units smaller than the maximum amount of data transferred by packet communication, there is wasted space when storing data actually transferred by packet communication. It is hard to occur and the memory can be used effectively.
[0026]
  According to a fourth aspect of the present invention, in the data processing device according to the first aspect, the control unit sets a value outside the range of the real memory address of the shared buffer memory as an initial value in the address conversion table, and The address conversion table is rewritten when data is stored in the buffer memory.
  According to this, regardless of the virtual memory address designated by the network interface means, it is possible to arbitrarily set which area of the shared buffer memory the data is actually accessed by the control means. In addition, by setting a value that does not specify any of the memory storage areas as an initial value in the storage area of the address conversion table, the storage area that stores a value that does not specify any of the address conversion table is counted. For example, since most of the storage area of the memory is used and the memory is almost full, it can be easily determined that the unused area of the memory is small.
  Of the present inventionFifth aspectIsFourth aspectIn the data processing apparatus, the control means includes:When the actual memory address converted by the address conversion table is the initial value,Shared bufferMemoryFrom the smallest address that is free in the real memory addressTo be used in orderThe initial value of the address conversion table is rewritten.
[0027]
  According to this, the control means isShared bufferBy setting the value in the storage area of the address conversion table so that the storage area of the memory is used in ascending order of addresses,Shared bufferEven if the storage area in use and the unused storage area are not gathered in the memory and there are scattered unused storage areas,Shared bufferSince unused storage areas in memory are selected in ascending order of addresses,Shared bufferEven if the memory is dotted with unused storage areas, it can be controlled to store data at consecutive addresses when viewed from the processing means side,Shared bufferYou can use memory easily. Also, since unused storage areas that are scattered can be used effectively,Shared bufferMemory can be used efficiently without waste.
[0029]
  Of the present inventionSixth aspectIsFourth or fifth aspectIn the data processing apparatus ofThe control means includes the shared buffermemoryofFree spaceIs below the specified amountIfThe address conversion table is not rewritten.
[0030]
  According to this, saidShared bufferWhen there is no more free space in memory,ThatThereafter, the control means does not rewrite the address in the address conversion table.Shared bufferThe data stored in the memory can be prevented from being overwritten.
[0031]
  Of the present inventionSeventh aspectIsAny of the fourth to sixth aspectsIn the data processing apparatus ofThe control means includesIn the address conversion tableUnused areaIf you run out ofThe address conversion table is not rewritten.
[0032]
  According to this, when there is no more free space in the address translation table,ThatThereafter, the control means does not rewrite the address in the address conversion table, so that data already stored in the address conversion table can be prevented from being overwritten.
[0033]
  Of the present inventionEighth aspectIsFirst or second aspectIn the data processing apparatus ofThe control means uses the address converted by the address conversion table.SaidShared bufferAny of the memoryReal memoryaddressnotIfStop storing and reading data at the real memory address after the conversionIs.
[0034]
  according to this,The address converted by the address conversion table isSaidShared bufferAny of the memoryReal memoryaddressnotCase,dataWill actually stop writing or readingShared bufferEven if no data has been written anywhere in the memory, the process is misjudged as having been completed normally, and the process proceeds.Shared bufferIt is possible to prevent the reading process from being erroneously determined as having been normally completed although no data is read from anywhere in the memory, and the process from proceeding.
[0035]
  In particular,It is possible to specify an address different from the address that should be originally specified due to a software bug. In this case, according to the present invention,,dataSince the writing process or reading process is stopped, it is possible to prevent the malfunction process from proceeding.
[0036]
  Of the present inventionNinth aspectIs1st or 4th aspectIn the data processing apparatus, the control means includes:Separately providing a dedicated hardware circuit for writing the real memory address of the shared buffer memory to the address conversion table,SaidShared bufferWhich memoryReal memoryWhether to store data at the address should be storedReal memoryA command is generated based on the address, and the dedicated hardware circuit analyzes the command to generate the address conversion table.Real memoryThe address is to be written.
[0037]
As in the prior art, when using, for example, four memory storage areas for storing data, the control means needs to write four addresses in the address conversion table. According to this, the control means is occupied during the writing process of the address conversion table.
[0038]
Therefore, according to the present invention, when the size of the memory storage area required by the control means is known, a command is generated based on the address indicating the memory storage area, and the address is written to the address conversion table. A hardware circuit is provided, and this dedicated hardware circuit analyzes the command and writes the address in the address conversion table, so that the control means sends the command once regardless of the size of the required storage area of the memory. Thus, the address conversion table can be rewritten in a plurality of storage areas, so that the load on the control means can be reduced and the processing speed can be increased.
[0039]
  Of the present inventionTenth aspectIsFirst aspectIn the data processing apparatus ofThe control means is read from the buffer memory and transmitted to the LAN via the network interface means.Send data andThe network interface means receives from the LAN and stores it in the buffer memoryReceive data is the same using the same busShared bufferStore or read from memory, andShared buffermemoryVirtual memory to accessDividing addresses for transmission data and reception datamanagementTo do.
[0040]
  According to this, transmission data and reception data are the same using the same bus.Shared bufferBy storing or reading from the memory, reading of the transmission data and storing of the reception data are not performed at the same time.Shared bufferA dedicated address for transmission data for all addresses in the memory is assigned, and for received dataShared bufferIf addresses dedicated to received data for all addresses in the memory are assigned, it can be managed so that there is a capacity that is double the actual memory capacity, and transmission data and received data do not need to be overwritten. Memory capacity can be reduced to less than half. as a result,Network interfaceSince it is possible to pretend that there is a memory capacity more than twice the real memory in advance,Network interfaceMeans sideActuallyCommunication exceeding the capacity of the memory can be performed without hindrance.
[0041]
  Also, the same data is used for transmission data and reception data using the same bus.Shared bufferEven when storing or reading from memory,Network interfaceMeansShared bufferBy holding the address indicating the storage area of the memory separately for transmission data and reception data, even if other data is received during transmission of certain data, data does not collide on the bus, Stable data communication can be ensured.
[0045]
Hereinafter, an embodiment of a network device to which a data processing apparatus according to the present invention is applied will be described in detail with reference to the drawings.
[0046]
FIG. 1 is a functional block diagram of a network device according to the present embodiment. In the present embodiment, a physical layer interface (PHY) 1 for connecting to three LANs 1, 2, 3 (for example, Ethernet (R)) is provided. The physical layer interface (PHY) 1 includes connectors 1a, 1b, and 1c having shapes conforming to the standards of LANs 1, 2, and 3. The LSI internal block 100 is provided with network interfaces 101, 102, 103 corresponding to the connectors 1a, 1b, 1c. The network interfaces 101, 102, and 103 operate based on the specifications (protocols and the like) of the LANs 1, 2, and 3 and serve to interface with the LANs 1, 2, and 3. The network interfaces 101, 102, and 103 perform a memory access operation using the reception address during reception, and perform a memory access operation using the transmission address during transmission operation. One shared buffer memory 104 is provided for these network interfaces 101, 102, and 103. The shared buffer memory 104 can be constituted by a RAM, for example. A memory control circuit 105 is provided to control writing / reading to / from the shared buffer memory 104. The network interfaces 101, 102, 103 and the shared buffer memory 104 are connected by a single internal bus 106. The encryption circuit 107 is a part that decrypts data encrypted according to IPv6 or encrypts transmission data. The encryption circuit 107 performs memory access using the reception address of the encryption module, and performs memory access using the transmission address of the encryption module.
[0047]
In this embodiment, one shared buffer memory 104 is used as a transmission buffer memory and a reception buffer memory by the plurality of network interfaces 101, 102, 103, the encryption circuit 107, and the CPU 200. The memory control circuit 105 performs address conversion described later.
[0048]
FIG. 2 is a block diagram showing functions related to address conversion of the memory control circuit 105. The memory control circuit 105 includes an address conversion table 201, a selector 202, and a command analysis circuit 203.
[0049]
The address conversion table 201 has a 256-stage configuration from Table-0 to Table-255, and a memory address space (hereinafter referred to as a virtual memory address) used by the network interfaces 101 to 103 and the like to access the shared buffer memory 104. Table data for converting a space) into an actual address space of the shared buffer memory 104 (hereinafter referred to as a real memory address space) is stored. In each table of 256 stages constituting the address conversion table 201, the upper 8 bits of the virtual memory address space are fixedly allocated in advance.
[0050]
The selector 202 receives the upper 8 bits of the virtual memory address accessed by the network interfaces 101 to 103, etc., selects one table according to the input address, and sends the table data of the selected table to the shared buffer memory 104. Output as upper 8 bits of real memory address space. Note that the lower 8 bits of the access address of the network interfaces 101 to 103 are output as the lower 8 bits of the actual memory address without being converted as they are.
[0051]
The command analysis circuit 203 analyzes a command given from the CPU 200 via a control line, and executes a process of clearing, copying, moving or resetting the table data of the address conversion table 201 according to the instruction content indicated in the analysis result To do. Further, the command analysis circuit 203 resets the usage status flag of the shared buffer memory 104 according to the instruction content indicated in the analysis result.
[0052]
Here, a virtual memory address used when the network interfaces 101 to 103 and the like access the shared buffer memory 104 will be described.
[0053]
As shown in FIG. 3, each of the network interfaces 101 to 103 can use a 2 Kbyte reception address and a transmission address. Also, the encryption circuit 107 can use the transmission address of the encryption module and the reception address of the encryption module each having 2 Kbytes in correspondence with encryption complying with IPv6. Further, the CPU 200 can use the entire virtual memory address space (0000h to ffffh) to directly access the shared buffer memory 104.
[0054]
As described above, the plurality of network interfaces 101 to 103, the encryption circuit 107, and the CPU 200 write / read the transmission data and the reception data to / from the same shared buffer memory 104 using the same bus, and the shared buffer memory The address for accessing 104 is divided into a transmission address and a reception address. As a result, transmission data and reception data are stored in or read from the same memory using the same bus, so that transmission data reading and reception data storage are not performed at the same time. If an address dedicated to transmission data that covers all addresses of the real memory address is given as a space, and an address dedicated to reception data that covers all addresses of the real memory address is given as an address space for reception, apparently Management can be performed so that there is twice the actual memory capacity, and the required memory capacity can be reduced to half or less without the transmission data and the reception data being overwritten with each other. As a result, the network interface on the writing / reading side can be preliminarily equipped with a memory capacity more than double that of the real memory, so communication over the capacity of the real memory can be performed without any trouble. Can be made.
[0055]
Even when transmission data and reception data are stored in or read from the same memory using the same bus, each network interface or the like uses the address indicating the storage area of the memory for transmission data and reception data. By holding the data separately for each purpose, even if other data is received during transmission of certain data, data does not collide on the bus, so that stable data communication can be ensured.
[0056]
In addition, as described above, the reception address space and the transmission address space are set to 2 K bytes, respectively, because the maximum capacity of one packet is defined as 1.5 K bytes in the standard regarding Ethernet (R). When applied to other types of networks, the maximum capacity of transmission units (packets, etc.) defined in the standard of the network is used.
[0057]
As described above, each of the network interfaces 101 to 103 has a 2 Kbyte reception address space and a transmission address space. However, each 2 Kbyte reception address space and transmission address space further includes 256 bytes. The page is divided in units.
[0058]
FIG. 4 shows the address assignment when the reception address space and the transmission address space are page-divided in units of 256 bytes for the network interface 101. In the figure, the write target address is a reception address, and the read target address is a transmission address. For example, when the network interface 101 receives 500 bytes of data, it accesses 0000h to 01eh as the write target address. When the upper bit is 00, table-0 is selected and the upper address written in table-0 is output. When the upper bit is 01, table-1 is selected and the upper address written in table-1 is output.
[0059]
On the other hand, in the shared buffer memory 104, the data storage area is divided in units of 256 bytes. That is, the minimum unit of the storage area is set to 256 bytes. As described above, in the virtual memory address space and the real memory address space, the data storage area is divided into 256-byte divided areas, and both divided areas (pages) are associated by the address conversion table 201.
[0060]
FIG. 5 is a diagram showing a correspondence relationship between the divided areas (pages) of the virtual memory address space used by the network interfaces 101 to 103 and the like for memory access and the divided areas of the real memory address space of the shared buffer memory 104. is there. In the present embodiment, since the RAM is assumed for the shared buffer memory 104, characters such as virtual RAM and RAM are used instead of virtual memory in FIG.
[0061]
As described above, since the virtual memory address space and the real memory address space are divided into 256-byte divided areas, the shared buffer memory 104 can be effectively used. When the data storage area is configured with a capacity (for example, 1.5 Kbytes) that can accommodate the maximum data amount transferred by packet communication, when storing data having a data amount smaller than the maximum data amount actually transferred by packet communication In this case, useless empty space is generated in the storage area, and the use efficiency of the memory is deteriorated. The present invention divides the divided area into units (for example, 256 bytes) smaller than the maximum amount of data transferred by packet communication, so that there is no wasteful space when storing data actually transferred by packet communication. It is unlikely to occur and the memory can be used effectively. If the divided area is divided into smaller sizes, the memory usage efficiency can be further improved. However, since the number of pages becomes too large and management becomes complicated, it is possible to select an appropriate size according to the purpose of use. desirable.
[0062]
Next, a specific memory control operation of the network device according to the present embodiment configured as described above will be described.
[0063]
First, a reception operation for writing received packet data to the shared buffer memory 104 will be described with reference to FIGS. As an example, an operation when the network interface 101 receives an IP packet having a data size between 768 bytes and 1024 bytes from the LAN 1 will be described.
[0064]
When the network interface 101 receives packet data from the LAN 1, the network interface 101 accesses the memory by specifying a reception address to the memory control circuit 105. At this time, the reception address accessed by the network interface 101 starts from the write target address 0000h as shown in FIG. Then, the write target address is sequentially incremented from 0000h until all the received packet data is written. The packet data is transferred to the shared buffer memory 104 in synchronization with the write target address increment operation.
[0065]
Each table of the address conversion table 201 is controlled so that the upper address of the empty divided area of the shared buffer memory 104 is set when the upper bit of the write target address is selected. Table data write control for the address conversion table 201 is performed by an automatic mode in which the memory control circuit 105 searches for a free divided area and automatically sets the corresponding table, and the CPU 200 manages the free divided area via the command analysis circuit 203. There is a manual mode in which table data is set in the corresponding table.
[0066]
FIG. 6 shows a process of incrementing the write target address shown in FIG. 4 from 0000h to 00ffh. During this time, the write target address [00 **], which is a virtual memory address, indicates 00, so the selector 202 selects the table-0 to which 00 is assigned. In the example shown in FIG. 6, since 02 is set as table data in the table-0, 02 is output as the converted higher address. As a result, the write target address that is the actual memory address is converted to [02 **]. Thereby, the first 256 bytes of the packet data are stored in the real memory addresses 0200h to 02ffh.
[0067]
FIG. 7 shows a process in which writing of 0000h to 00ffh as the write target address is completed and the write target address is continuously incremented within the range of 0100h to 01ffh. During this time, the write target address [01 **], which is a virtual memory address, indicates 01 in the upper bit, so that the selector 202 selects the table-1 to which 01 is assigned. In the example shown in FIG. 7, since 03 is set as table data in Table-1, 03 is output as the converted higher address. As a result, the write target address, which is a real memory address, is converted to [03 **]. As a result, the next 256 bytes of the packet data are stored in 0300h to 03ffh of the real memory addresses.
[0068]
FIG. 8 shows a process in which writing of 0100h to 01ffh as the write target address is completed and the write target address is continuously incremented within the range of 0200h to 02ffh. During this period, the write target address [02 **], which is a virtual memory address, indicates 02 as the upper bit, so the selector 202 selects Table-2 to which 02 is assigned. In the example shown in FIG. 8, since 7e is set as the table data in Table-2, 7e is output as the converted higher address. As a result, the write target address that is the actual memory address is converted to [7e **]. As a result, the next 256 bytes of the packet data are stored in real memory addresses 7e00h to 7effh.
[0069]
FIG. 9 shows a process in which writing of 0200h to 02ffh is completed as the write target address and the write target address is continuously incremented within the range of 0300h to 03ffh. During this time, the write target address [03 **], which is a virtual memory address, indicates that the upper bit is 03, so the selector 202 selects Table-3 to which 03 is assigned. In the example shown in FIG. 9, since 7f is set as the table data in Table-3, 7f is output as the converted higher address. As a result, the write target address in the real memory address space is converted to [7f **]. As a result, the next 256 bytes of the packet data are stored in real memory addresses 7f00h to 7f ** h. ** is the last lower address.
[0070]
As described above, according to the present embodiment, although the addresses output from the network interface 101 as the write target addresses are continuous addresses, the continuous write target addresses can be converted into random real memory addresses by the address conversion table 201. Even if there is a discontinuous empty area in the shared buffer memory 104 accessed by the real memory address, the packet data is stored in the discontinuous empty area by controlling the table data of the address conversion table 201. can do. In the configuration in which the buffer memory of a plurality of network interfaces is shared and the reception buffer memory and the transmission buffer memory are shared as in the present embodiment, it is possible to use a free area even if it is discontinuous. This is very effective from the viewpoint of preventing memory overflow.
[0071]
In addition, the address specified by the network interface 101 in the address conversion table 201 is converted into a real memory address (higher address) that actually stores data, and the data is actually stored in the real memory regardless of the address specified by the network interface 101. Since it is possible to arbitrarily set which address of the address is stored, even when the same address is designated from the network interface 101, it is not necessary to perform processing for transferring data in the shared buffer memory, and the memory can be used effectively. At the same time, the processing speed can be increased.
[0072]
Next, a transmission operation for reading packet data from the shared buffer memory 104 will be described with reference to FIGS. A case where the network interface 101 sends out the data written in the shared buffer memory 104 in the above receiving operation (FIGS. 6 to 9) from the LAN 1 will be described.
[0073]
As described above, the real memory addresses of the shared buffer memory 104 store data in the order of 0200h-02ffh, 0300h-03ffh, 7e00h-7effh, 7f00h-7f ** h. On the other hand, the network interface 101 uses the transmission address space 0800h to 0bffh shown in FIG. 4 as the read target address. The network interface 101 outputs the read target address sequentially incremented from 0800h, which is the start address of the transmission address space.
[0074]
On the other hand, the CPU 200 knows the real memory address that is the storage address of the packet data to be read this time. As shown in FIG. 9, the upper addresses of the real memory addresses where data is stored are 02, 03, 7e, and 7f. The transmission address (virtual memory address) of the network interface 101 is also fixed. As for the transmission address of the network interface 101, the upper address changes to 08, 09, 0a, and 0b. Therefore, the CPU 200 adds the upper addresses 02, 03, 7e, and the higher addresses 02, 03, 7e, 7f are respectively set as table data.
[0075]
FIG. 10 shows a process of incrementing the read target address shown in FIG. 4 within the range of 0800h to 08ffh. During this time, the read target address [08 **], which is a virtual memory address, has an upper bit of 08, so the selector 202 selects the table-8 to which 08 is allocated. At this time, since 02 is set in Table-8, 02 is output as the converted higher address. As a result, the read target address in the real memory address space is converted to [02 **]. As a result, the first 256 bytes of the packet data are read from the actual memory addresses 0200h to 02ffh.
[0076]
FIG. 11 shows a process of incrementing the read target address shown in FIG. 4 within the range of 0900h to 09ffh. During this time, the read target address [09 **], which is a virtual memory address, has a high-order bit of 09, so the selector 202 selects Table-9 to which 09 is assigned. At this time, since 03 is set in Table-9, 03 is output as the converted higher address. As a result, the read target address in the real memory address space is converted to [03 **]. As a result, the first 256 bytes of the packet data are read from the actual memory addresses 0300h to 03ffh.
[0077]
FIG. 12 shows a process of incrementing the read target address shown in FIG. 4 within the range of 0a00h to 0affh. During this time, the read target address [0a **], which is a virtual memory address, indicates that the upper bit indicates 0a, so that the selector 202 selects the table-10 to which 7e is allocated. At this time, since 7e is set in the table-10, 7e is output as the converted higher address. As a result, the read target address in the real memory address space is converted to [7e **]. As a result, the first 256 bytes of the packet data are read from the real memory addresses 7e00h to 7effh.
[0078]
FIG. 13 shows a process of incrementing the read target address shown in FIG. 4 within the range of 0b00h to 0bffh. During this time, the read target address [0b **], which is a virtual memory address, indicates that the upper bit is 0b, so that the selector 202 selects the table-11 to which 7f is allocated. At this time, since 7f is set in the table-11, 7f is output as an upper address after conversion. As a result, the read target address in the real memory address space is converted to [7f **]. As a result, the first 256 bytes of the packet data are read from the real memory addresses 7f00h to 7f ** h.
[0079]
As described above, since the transmission address (virtual memory address) of the network interface 101 is converted into the real memory address where the data is actually stored in the address conversion table 201, the process of transferring the data in the memory is performed. Since there is no need to perform the process and the CPU 200 does not need to read the received data for transmission, the processing speed can be increased.
[0080]
In the above description, the case where the packet data is received by the network interface 101 and the packet data is transmitted by the same network interface 101 has been described. However, writing / reading to / from the shared buffer memory 104 can be executed between the other network interfaces 102 and 103 using the transmission address and the reception address assigned to each other as shown in FIG. Also, when the encryption circuit 107 encrypts or decrypts the data, the encryption circuit 107 accesses the memory using the transmission address and reception address of the encryption module, and the CPU 200 does not transfer the data. Write / read to / from the shared buffer memory 104 can be executed.
[0081]
Next, an automatic mode for automatically setting the table data of the address conversion table 201 will be described. I don't know when the data is received from LAN 1, 2, 3 at any timing. Therefore, by always allowing reception in the automatic mode, it is possible to prepare for reception that does not know when it is received or how large.
[0082]
FIG. 14 is a diagram showing a part relating to the automatic mode extracted from the memory control circuit 105 and the shared buffer memory 104. A table flag 210 indicating whether or not table data is set in each table of the address conversion table 201 composed of 256 tables is prepared in hardware. The table flag 210 is set to 1 when significant table data is set in the corresponding table. Further, when the table data is not set in the table and the value FF indicating that no address is specified is entered, the table is updated so that 0 is set.
[0083]
The output signal of the selector 202 is input to one input terminal of the selector 211 serving as the third selection unit. The other input terminal of the selector 211 receives an output signal from a minimum flag detection circuit 213 serving as second selection means described later. The selector 211 selects and outputs an output signal from the minimum flag detection circuit 213 when FF is input from the selector 202 in the previous stage. The output signal of the selector 211 is configured to indicate the upper bit of the actual memory address.
[0084]
A usage status flag 212 that always reflects the usage status of the real memory address of the shared buffer memory 104 is provided in hardware. The usage status flag 212 is set to 0 as an initial value, but is updated so that 1 is set when data is written to the corresponding real memory address. In this example, since the storage area is used in the divided area unit (256 bytes) specified by the upper address, only the upper address of the real memory address is monitored, but more detailed usage status may be monitored. Monitor to lower addresses.
[0085]
The minimum flag detection circuit 213 scans the usage status flag 212 from the head address side, and outputs an upper address that is initially set to 0 as an output value. In other words, the smallest unused address in the real memory address space is always used as the output value.
[0086]
A specific operation in the automatic mode will be described with reference to FIG. In the state shown in FIG. 14, table data has already been set in the tables-0, 1, and 4 of the address conversion table 201, and as a result, data is stored in 00h, 02h, and 03h of real memory addresses (upper addresses). State.
[0087]
In such a situation, the minimum flag detection circuit 213 outputs the real memory address 01h as the minimum address of the free area. Then, 05h is given to the selector 202 as an upper address of the write address. The selector 202 selects the table-5 based on the upper address 05h, but outputs FF to the subsequent selector 211 as a value in the table-5.
[0088]
Since the selector 211 selects the minimum address input from the minimum flag detection circuit 213 when FF is input from the address conversion table 201, the minimum address is selected as the actual memory address. That is, when the real memory address is not designated by the address conversion table 201, the data is stored at the minimum address that is an empty area in the real memory.
[0089]
As a result, even if the storage area in use and the unused storage area are not gathered in the real memory address and the unused storage areas are scattered, the unused storage areas in the real memory address are arranged in ascending order of the addresses. Since the selected storage areas are effectively used, the shared buffer memory 104 can be used efficiently without waste. In addition, even if the actual memory is dotted with unused storage areas, it can be controlled so that data is stored at consecutive addresses when viewed from the network interface 101, 102, 103 side. Easy to use.
[0090]
In the present embodiment, a value FF that does not designate any storage area of the memory is set as an initial value in each table of the address conversion table 201. When any one of the address conversion tables 201 is designated from the selector 202, the minimum flag detection circuit 213 and the selector 211 are operated so that they are used in ascending order of the real memory addresses.
[0091]
As a result, unless a plurality of network interfaces 101, 102, 103, etc. simultaneously execute transmission / reception operations on the shared buffer memory 104, data for one packet can always be stored together, and an area in which one packet data is stored can be stored. Since the packet data is stored in order from the top address, the CPU 200 can always confirm the data by checking the received data from the top address of the storage area, thereby simplifying and speeding up the processing. it can.
[0092]
On the other hand, the warning generation circuit 214 monitors the output value of the minimum flag detection circuit 213 and outputs an interrupt signal 1 to the CPU 200 when the free area of the shared buffer memory 104 becomes a predetermined amount or less. When receiving the interrupt signal 1 from the warning generation circuit 214, the CPU 200 operates so as not to rewrite the address (table data) in the address conversion table 201 thereafter.
[0093]
As a result, when there is no more free space in the shared buffer memory 104, the CPU 200 does not rewrite the address in the address conversion table 201 by issuing an interrupt signal 1 to the CPU 200, so that it is already stored in the shared buffer memory 104. It is possible to prevent overwritten data being overwritten.
[0094]
Further, the warning generation circuit 214 monitors the table flag 210 of the address conversion table 201, counts the FFs of the address conversion table 201, and outputs an interrupt signal 2 to the CPU 200 when the count value (free area) becomes a predetermined value or less. Output. When receiving the interrupt signal 2 from the warning generation circuit 214, the CPU 200 operates so as not to rewrite the address in the address conversion table 201 thereafter.
[0095]
For example, when receiving data from another LAN 2 is written while data received from the LAN 1 is being written, there is a possibility that a real memory address has a free area but the address conversion table 201 becomes full. There is. According to the present embodiment, when there is no more free area in the address conversion table 201, by issuing an interrupt signal 2 to the CPU 200, the address conversion table 201 is not rewritten thereafter. Data stored in the conversion table 201 can be prevented from being overwritten.
[0096]
In the present embodiment, the alarm generation circuit 214 issues an interrupt signal 3 to the CPU 200 when the output of the selector 211 has not selected any address of the real memory address. When the CPU 200 receives the interrupt signal 3, the CPU 200 stops the data writing or reading process.
[0097]
According to this, when none of the real memory addresses is selected as the output of the selector 211, the data write process or read process is stopped by issuing the interrupt signal 3 to the CPU 200. In some cases, the process proceeds with a misjudgment that the writing process has been completed normally even though no data has been written anywhere in the real memory address. It is possible to prevent the reading process from being erroneously determined to have ended normally even though it has not been read and proceeding.
[0098]
In particular, when the CPU 200 sets the write address / read address in software, it may happen that an address different from the address that should be originally specified is specified due to a software bug. In this case, according to the present embodiment, the data write process or read process is stopped by issuing the interrupt signal 3 to the CPU 200, so that it is possible to prevent the malfunction process from proceeding.
[0099]
Next, an operation in which the command analysis circuit 203 analyzes the command generated by the CPU 200 and operates the table data of the address conversion table 201 will be described. The command analysis circuit 203 constitutes a 32-bit space command register as shown in FIG. In this embodiment, the meaning of each field of the command is as follows. 8 bits of [31:24] is a field indicating a command type. The commands include CLEAR for instructing deletion of table data, COPY for copying table data, MOVE for moving table data, and ALLOCATION for writing table data (for example, 00). 8 bits of [23:16] is a field for inputting the number of pages. 8 bits of [15: 8] is a field indicating the first page of the deletion, movement, or copy target deletion or movement / copy source. 8 bits of [7: 0] is a field indicating the first page of the move / copy destination.
[0100]
The commands as described above are generated by the CPU 200 according to the situation. For example, when the table data of the address conversion table 201 is initialized and changed to FF, a command specifying the command type (CLEAR), the first page (table number), and the number of pages in each field is generated, and the command analysis circuit 203 Give to. The command analysis circuit 203 analyzes the command given from the CPU 200, and deletes the table data by the number of pages designated from the first page designated based on the analysis result to make FF.
[0101]
Conventionally, when, for example, four memory storage areas are used to store data, the CPU 200 needs to write addresses four times to the address conversion table 201. According to this, the CPU 200 is occupied during the writing process of the address conversion table 201.
[0102]
Therefore, according to the present embodiment, when the size of the storage area for the real memory address necessary in the CPU 200 is known, a command is generated based on the address indicating the storage area for the real memory address, and the address conversion table 201 stores the command. When the command analysis circuit 203 analyzes the command and writes the address to the address conversion table 201, the CPU 200 can send the command only once, regardless of the size of the required storage area of the memory. Since rewriting in a plurality of storage areas of the table 201 can be performed, the load on the CPU 200 can be reduced and the processing speed can be increased.
[0103]
Next, a manual mode (during a reception operation) in which the CPU 200 rewrites the table data of the address conversion table by restricting the automatic mode operation of the minimum flag detection circuit 213 and the selector 211 will be described.
[0104]
In an initial state where no data is stored in the shared buffer memory 104, a write target address (any one of 00h to ffh) designated from any one of the network interfaces 101, 102, and 103 is changed to any real memory address (00h to 7fh). Table data to be converted into () is set in the address conversion table 201. In the address conversion table 201, a value FF that does not designate any real memory address is set as an initial value.
[0105]
When the reception operation (storage) for one packet is completed, the real memory address (upper address) where the data is stored in the address conversion table 201 remains as table data. The CPU 200 can recognize the free area of the real memory address from the table data of the address conversion table 201. For example, when one reception operation is completed, the table data of the address conversion table 201 is read to grasp the free area of the real memory address.
[0106]
When starting the next reception operation, the table corresponding to the write target address (upper address) is converted so that the current write target address (upper address) is converted into an empty area of the real memory address known by the CPU 200. Rewrite table data.
[0107]
Thus, even if the writing side such as the network interface always accesses using the same reception address, the reception address is converted into an address indicating a free area of the real memory address by the address conversion table 201 and written. It will be a thing.
[0108]
Further, in the present embodiment, even in the manual mode, the address conversion table 201 sets FF as an initial value, and the table of the address conversion table 201 is used so that storage areas of real memory addresses are used in ascending order of addresses. It is also possible to set data.
[0109]
As a result, even if the storage area in use and the unused storage area are not gathered in the real memory address and the unused storage areas are scattered, the unused storage areas in the real memory address are arranged in ascending order of the addresses. Since the selected storage areas are effectively used, the shared buffer memory 104 can be used efficiently without waste. In addition, even if the actual memory is dotted with unused storage areas, it can be controlled so that data is stored at consecutive addresses when viewed from the network interface 101, 102, 103 side. Easy to use.
[0110]
In the transmission operation, only the manual mode is used. This is because, in the case of the transmission operation, unlike the case of the reception operation, it is necessary to read data from the storage area of the specific memory address in the shared buffer memory 104. The transmission operation in the manual mode is as described above. That is, when starting the transmission operation, the CPU 200 knows the real memory address where the packet data is stored and also knows the transmission address to be used. Therefore, the transmission address (upper address) is the packet data Table data to be converted into the stored real memory address is set in the address conversion table 201. As a result, for example, even if the network interface 102 is accessed using the assigned transmission address, the address conversion table 201 converts the packet data into a real memory address where the packet data is stored, and the data is read out.
[0111]
【The invention's effect】
As described above in detail, according to the present invention, an increase in the buffer memory can be suppressed, the cost can be reduced, the apparatus can be downsized, and the data can be transferred from the reception buffer memory to the transmission buffer memory by the CPU. It is possible to provide a data processing device that eliminates the change work and realizes high-speed processing.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of a network device according to an embodiment of the present invention.
FIG. 2 is a functional block diagram of a memory control circuit in the network device shown in FIG.
FIG. 3 is a diagram showing allocation of reception addresses and transmission addresses.
FIG. 4 is a diagram showing an example of address correspondence for each page when memory is accessed from the network interface.
FIG. 5 is a diagram illustrating an example of conversion from a page division area of an address conversion table to a page division area of a real memory address;
FIG. 6 is a diagram showing an example of address conversion when 00h is specified as a receiving address.
FIG. 7 is a diagram showing an example of address conversion when 01h is designated as a receiving address.
FIG. 8 is a diagram showing an example of address conversion when 02h is specified as a receiving address;
FIG. 9 is a diagram showing an example of address conversion when 03h is designated as a receiving address.
FIG. 10 is a diagram showing an example of address conversion when 08h is designated as the transmission address.
FIG. 11 is a diagram showing an example of address conversion when 09h is specified as a transmission address;
FIG. 12 is a diagram showing an example of address conversion when 0ah is specified as a transmission address;
FIG. 13 is a diagram showing an example of address conversion when 0bh is specified as a transmission address;
FIG. 14 is an operation explanatory diagram of an automatic mode using an address conversion table, a shared buffer memory, and peripheral circuits.
FIG. 15 is a configuration diagram of a command register.
FIG. 16 is a functional block diagram of a conventional network device.
[Explanation of symbols]
1 Physical layer interface
100 LSI internal block
101, 102, 103 Network interface
104 Shared buffer memory
105 Memory control circuit
106 Internal bus
107 Cryptographic circuit
200 CPU
201 Address conversion table
202, 211 selector
203 Command analysis circuit
210 Table flag
212 Usage flag
213 Minimum flag detection circuit
214 Warning generation circuit

Claims (10)

A plurality of network interface means for interfacing with a LAN; a shared buffer memory accessed by the plurality of network interface means for storing data and reading the stored data; and for accessing the shared buffer memory A virtual memory address is converted into an actual real memory address of the shared buffer memory, and an address range of a virtual memory address used for each network interface unit is divided, and the divided address range is used for reception. An address conversion table in which virtual memory addresses are further divided for transmission and a virtual memory address is input from the network interface means to access the shared buffer memory And control means converts the virtual memory addresses into real memory address to access the shared buffer memory of the translated real memory address using the address conversion table,
  A data processing apparatus comprising: The control means includes
When a real memory address corresponding to a virtual memory address is not set in the address conversion table, the smallest address that is an empty area in the real memory address of the shared buffer memory is accessed.
The data processing apparatus according to claim 1. The shared buffer memory is
The data storage area is divided into units smaller than the maximum amount of data transferred by packet communication .
The data processing apparatus according to claim 1 . The control means includes
A value outside the range of the real memory address of the shared buffer memory is set as an initial value in the address conversion table, and the address conversion table is rewritten when data is stored in the shared buffer memory.
The data processing apparatus according to claim 1. The control means includes
When the real memory address converted by the address conversion table is the initial value, the initial value of the address conversion table is rewritten so that it is used in order from the smallest address that is an empty area in the real memory address of the shared buffer memory. The
The data processing apparatus according to claim 4 . The control means includes
When the free area of the shared buffer memory becomes a predetermined amount or less, the address conversion table is not rewritten,
The data processing apparatus according to claim 4 or 5 . The control means includes
When there is no unused area in the address conversion table, the address conversion table is not rewritten.
The data processing apparatus according to any one of claims 4 to 6 . The control means includes
If the address converted by the address conversion table is not any real memory address of the shared buffer memory , stop storing and reading data to the real memory address after conversion,
The data processing apparatus according to claim 1 or 2 . The control means includes
A dedicated hardware circuit for writing the real memory address of the shared buffer memory into the address conversion table is separately provided, and a command based on the real memory address to be stored is stored as to which real memory address of the shared buffer memory is to store data. The dedicated hardware circuit analyzes the command and writes the real memory address to the address conversion table .
The data processing apparatus according to claim 1 or 4 . The control means includes
Transmission data read from the buffer memory and transmitted to the LAN via the network interface means and reception data received by the network interface means from the LAN and stored in the buffer memory are shared using the same bus. The virtual memory address for storing or reading the buffer memory and accessing the shared buffer memory is managed separately for transmission data and reception data .
The data processing apparatus according to claim 1 .

Images