JP4019550B2 - Semiconductor package manufacturing method - Google Patents
Semiconductor package manufacturing method Download PDFInfo
- Publication number
- JP4019550B2 JP4019550B2 JP10191999A JP10191999A JP4019550B2 JP 4019550 B2 JP4019550 B2 JP 4019550B2 JP 10191999 A JP10191999 A JP 10191999A JP 10191999 A JP10191999 A JP 10191999A JP 4019550 B2 JP4019550 B2 JP 4019550B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- semiconductor
- manufacturing
- adhesive
- mounting substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Lead Frames For Integrated Circuits (AREA)
Description
【0001】
【発明の属する技術分野】
本発明は、半導体パッケージの製造法に関する。
【0002】
【従来の技術】
近来、電子機器の小型化、軽量化、多機能化が一段と進み、これに伴い、LSIやチップ部品等の高集積化が進展し、その形態も多ピン化、小型化へと急速に変化している。このため、プリント配線板には、電子部品の実装密度を向上するために、配線パターンの高密度化が一層求められるようになった。
【0003】
また、電子機器の発達に伴い、配線板や電子部品は小型化されているのに対して、半導体チップは回路の機能を追加・進展させるために、規模は大きくなりつつあるが、半導体を搭載するパッケージには、今までのように、メタルパッケージやセラミックスを用いていたのでは高価になり、機器のコストを下げるためにも、有機材料を使用するようになってきている。
【0004】
そこで、半導体チップを搭載するための入れ物として、有機材料による、フィルムキャリア、リードレスチップキャリア、フリップチップ、ピングリッドアレイ、ボールグリッドアレイ等のように配線板に直接半導体チップを搭載するものが開発、市販され始めている。
【0005】
また、配線板においても、層間の薄型化、配線の微細化、層間接続穴の小径化が行われ、隣接する層間の導体のみを接続するインタースティシャルバイアホール(以下、IVHという。)や、ベリードバイアホール(以下、BVHという。)が用いられるようになり、このIVHやBVHも更に小径化されつつある。
【0006】
近年では、ハンダボールを半導体搭載用基板と配線板との接続に用いるボールグリッドアレイパッケージ(以下、BGAという。)において、通常のリードフレームに、半導体搭載用基板を接着固定して、リードフレーム半導体パッケージと同様に量産できる半導体パッケージを用いることが検討されている。
【0007】
これは、はんだボールの装着、半導体チップの搭載・ワイヤボンディング、樹脂による封止などの一連の作業を連続して行うためであり、半導体搭載用基板を接着・固定しているのは、後に不要となる箇所まで半導体搭載用基板の材料を使用すると、材料の無駄が多く経済的でないことから、半導体搭載基板を隙間なく並べて、大きな基板で一度に製造し、切断して、金属製フレームに接着・固定する方が経済的だからである。
【0008】
【発明が解決しようとする課題】
このような半導体パッケージは、はんだボールの装着や半導体チップの搭載・ワイヤボンディングが終了して、樹脂で封止されると、フレームは不要となるので、切断されるが、フレームに半導体搭載用基板を固定した箇所は半導体パッケージに残された状態となっている。
【0009】
ところで、金属製フレームに、接着剤をディスペンサで滴下して、乾燥し、半導体搭載用基板を重ねて、加圧・加熱すると、その接着剤の箇所にボイドが発生し、はんだボールの装着、半導体チップの搭載・ワイヤボンディング、樹脂による封止した後の半導体パッケージを、配線板に搭載するときにはんだボールを溶融するときの温度で、そのボイドが破裂して半導体パッケージを壊すおそれがあるという課題がある。
【0010】
本発明は、ボイドの発生の抑制に優れた半導体パッケージを製造する方法を提供することを目的とする。
【0011】
【課題を解決するための手段】
本発明の半導体パッケージの製造法は、金属製のフレームに、半導体搭載用基板を接着し、リードフレーム上に連続して装着した半導体パッケージの製造法であって、金属製のフレームに半導体搭載用基板を接着する箇所にディスペンサで接着剤を、一定の湿度の下で滴下した後、その湿度を保ったまま乾燥し、半導体搭載用基板を重ね、加圧・加熱して積層一体化することを特徴とする。
【0012】
【発明の実施の形態】
接着剤が、熱可塑性樹脂からなり、滴下するときとその後の乾燥の間保つ湿度は、20〜40%Rhであることが好ましく、25〜35%Rhであることがより好ましい。
【0013】
【実施例】
実施例1
厚さ0.2mmの銅板を打ち抜き、銅フレームを作製した。
【0014】
厚さ12μmの銅箔を貼り合わせた厚さ0.6mmの銅張り積層板であるMCL−E−679(日立化成工業株式会社製、商品名)に穴をあけ、無電解めっきによって穴内壁を金属化した後、不要な銅箔をエッチング除去して、ハンダボール用ランドと半導体接続用端子とその端子とハンダボール用ランドを接続する配線とを形成した後、エッチングレジストを3wt%水酸化ナトリウム水溶液で剥離し、回路を形成して、半導体搭載用基板を得た。
【0015】
金属製フレームの四隅に、ディスペンサで熱可塑性樹脂からなる接着剤であるハイマール(日立化成工業株式会社製、商品名)を、約50μgづつ滴下した。
【0016】
このときの雰囲気は、ドライアを用いて乾燥した空気を供給し、常温で35%Rhとした。
【0017】
さらに、トンネル乾燥炉に搬送するまでの間、ドライアで乾燥した空気を供給し、湿度センサで検出した湿度を、35±3%以内になるように風量を制御した。その後、トンネル乾燥炉に搬送し、140℃で150秒間、乾燥した。
【0018】
金属フレームと、半導体搭載用基板とを重ね、10kgf/cm2の圧力で、温度250℃で、加圧・加熱し、積層一体化した。
【0019】
このようにして作製した半導体パッケージは、加速試験で260℃の溶融はんだ浴に10秒間浮かべたが、ボイドによる破裂はなかった。
【0020】
実施例2
トンネル乾燥炉に搬送するまでの間、ドライアで乾燥した空気を供給し、湿度センサで検出した湿度を、15±3%以内になるように風量を制御した以外は、実施例1と同様にして半導体パッケージを作製した。このようにして作製した半導体パッケージは、加速試験で260℃の溶融はんだ浴に10秒間浮かべたが、ボイドによる破裂はなかった。
【0021】
実施例3
トンネル乾燥炉に搬送するまでの間、ドライアで乾燥した空気を供給し、湿度センサで検出した湿度を、25±3%以内になるように風量を制御した以外は、実施例1と同様にして半導体パッケージを作製した。このようにして作製した半導体パッケージは、加速試験で260℃の溶融はんだ浴に10秒間浮かべたが、ボイドによる破裂はなかった。
【0022】
比較例
比較のために、トンネル乾燥炉に搬送するまでの間、ドライアで乾燥した空気の供給をしない以外は、実施例と同じ条件、同じ材料で半導体パッケージを作製した。このようにして作製した半導体パッケージは、加速試験で260℃の溶融はんだ浴に10秒間浮かべ、100個のうち5個が、ボイドによる破裂が発生した。
【0023】
【発明の効果】
以上に説明したとおり、本発明によって、ボイドの発生の抑制に優れた半導体パッケージを製造する方法を提供することができる。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package.
[0002]
[Prior art]
Recently, electronic devices have become smaller, lighter, and more functional, and with this, higher integration of LSIs and chip parts has progressed, and the form has rapidly changed to multi-pin and miniaturization. ing. For this reason, printed wiring boards are required to have higher wiring patterns in order to improve the mounting density of electronic components.
[0003]
In addition, with the development of electronic equipment, the size of wiring boards and electronic components has been reduced, while semiconductor chips are becoming larger in order to add and advance circuit functions. For the package to be used, it has become expensive if metal packages and ceramics have been used as before, and organic materials have been used to reduce the cost of the equipment.
[0004]
Therefore, as a container for mounting a semiconductor chip, an organic material such as a film carrier, a leadless chip carrier, a flip chip, a pin grid array, a ball grid array, or the like that directly mounts a semiconductor chip on a wiring board has been developed. Are beginning to be marketed.
[0005]
Also in the wiring board, interlayer thinning, wiring miniaturization, and interlayer connection hole diameter reduction are performed, and interstitial via holes (hereinafter referred to as IVH) for connecting only conductors between adjacent layers, are also provided. Very via holes (hereinafter referred to as BVH) are being used, and the diameters of IVH and BVH are also being further reduced.
[0006]
In recent years, in a ball grid array package (hereinafter referred to as BGA) in which solder balls are used to connect a semiconductor mounting substrate and a wiring board, the semiconductor mounting substrate is bonded and fixed to an ordinary lead frame, and the lead frame semiconductor The use of a semiconductor package that can be mass-produced in the same manner as the package has been studied.
[0007]
This is to perform a series of operations such as solder ball mounting, semiconductor chip mounting / wire bonding, and resin sealing, and it is not necessary to attach / fix the semiconductor mounting board later. If the material for the semiconductor mounting substrate is used up to the point where it becomes, the material is wasted and it is not economical, so the semiconductor mounting substrates are arranged without gaps, manufactured at once with a large substrate, cut and bonded to the metal frame・ It is more economical to fix.
[0008]
[Problems to be solved by the invention]
Such a semiconductor package is cut when the solder ball mounting, semiconductor chip mounting and wire bonding are completed and sealed with resin, so that the frame becomes unnecessary, but the semiconductor mounting substrate is attached to the frame. The portion where the is fixed is left in the semiconductor package.
[0009]
By the way, when an adhesive is dropped on a metal frame with a dispenser, dried, and a substrate for mounting a semiconductor is stacked and then pressed and heated, voids are generated at the location of the adhesive, and solder balls are mounted. The problem is that the semiconductor package after chip mounting, wire bonding, and resin sealing may be broken at the temperature at which the solder ball melts when mounting the semiconductor package on the wiring board. There is.
[0010]
An object of this invention is to provide the method of manufacturing the semiconductor package excellent in suppression of generation | occurrence | production of a void.
[0011]
[Means for Solving the Problems]
The semiconductor package manufacturing method of the present invention is a method of manufacturing a semiconductor package in which a semiconductor mounting substrate is bonded to a metal frame and continuously mounted on a lead frame, and the semiconductor package is mounted on a metal frame. After dropping the adhesive with a dispenser to the place where the substrate is to be bonded under a certain humidity, it is dried while maintaining that humidity, and the semiconductor mounting substrate is stacked, and the stacking is integrated by pressing and heating. Features.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The adhesive is made of a thermoplastic resin, and the humidity maintained during the dripping and the subsequent drying is preferably 20 to 40% Rh, and more preferably 25 to 35% Rh.
[0013]
【Example】
Example 1
A copper plate having a thickness of 0.2 mm was punched out to produce a copper frame.
[0014]
A hole is made in MCL-E-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a 0.6 mm thick copper clad laminated with 12 μm thick copper foil, and the inner wall of the hole is formed by electroless plating. After metallization, unnecessary copper foil is removed by etching to form a solder ball land, a semiconductor connection terminal, and a wiring connecting the terminal and the solder ball land, and then an etching resist is added to 3 wt% sodium hydroxide. The substrate was peeled off with an aqueous solution to form a circuit to obtain a semiconductor mounting substrate.
[0015]
About 50 μg of Hymar (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an adhesive made of a thermoplastic resin, was dropped onto the four corners of the metal frame.
[0016]
The atmosphere at this time was 35% Rh at room temperature by supplying dry air using a dryer.
[0017]
In addition, air dried by a dryer was supplied until it was transported to the tunnel drying furnace, and the air volume was controlled so that the humidity detected by the humidity sensor was within 35 ± 3%. Then, it conveyed to the tunnel drying furnace and dried at 140 degreeC for 150 second.
[0018]
The metal frame and the semiconductor mounting substrate were overlapped and laminated and integrated by pressing and heating at a pressure of 10 kgf / cm 2 and a temperature of 250 ° C.
[0019]
The semiconductor package thus produced was floated in a molten solder bath at 260 ° C. for 10 seconds in an accelerated test, but there was no rupture due to voids.
[0020]
Example 2
The same procedure as in Example 1 was performed except that air dried by a dryer was supplied until the air was transported to the tunnel drying furnace, and the air volume was controlled so that the humidity detected by the humidity sensor was within 15 ± 3%. A semiconductor package was produced. The semiconductor package thus produced was floated in a molten solder bath at 260 ° C. for 10 seconds in an accelerated test, but there was no rupture due to voids.
[0021]
Example 3
The same procedure as in Example 1 was performed except that air dried by a dryer was supplied and the air volume was controlled so that the humidity detected by the humidity sensor was within 25 ± 3% until it was transported to the tunnel drying furnace. A semiconductor package was produced. The semiconductor package thus produced was floated in a molten solder bath at 260 ° C. for 10 seconds in an accelerated test, but there was no rupture due to voids.
[0022]
For comparison of comparative examples, a semiconductor package was manufactured under the same conditions and the same materials as in the examples except that the air dried by the dryer was not supplied until it was transferred to the tunnel drying furnace. The semiconductor package thus produced floated in a molten solder bath at 260 ° C. for 10 seconds in an accelerated test, and 5 out of 100 semiconductors were ruptured by voids.
[0023]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor package excellent in suppressing generation of voids.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10191999A JP4019550B2 (en) | 1999-04-09 | 1999-04-09 | Semiconductor package manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10191999A JP4019550B2 (en) | 1999-04-09 | 1999-04-09 | Semiconductor package manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000294683A JP2000294683A (en) | 2000-10-20 |
| JP4019550B2 true JP4019550B2 (en) | 2007-12-12 |
Family
ID=14313327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10191999A Expired - Fee Related JP4019550B2 (en) | 1999-04-09 | 1999-04-09 | Semiconductor package manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4019550B2 (en) |
-
1999
- 1999-04-09 JP JP10191999A patent/JP4019550B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000294683A (en) | 2000-10-20 |
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