JP4020196B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor element that improves the operating voltage of a semiconductor element having a metal-oxide film-semiconductor (MOS) structure constituting a semiconductor device such as an information processing device or a power device.
[0002]
[Prior art]
A semiconductor device as a conventional MOS field effect transistor (FET) using silicon carbide (SiC) has a boron (B) layer on the surface layer of an n-type drift layer (pressure-resistant layer) deposited by epitaxial growth on an n-type substrate. A p-type base (body) region formed by ion implantation, and an n-type source region formed by phosphorus (P) ion implantation therein.
[0003]
Furthermore, a gate electrode of polycrystalline silicon is provided on the surface of the p-type base region between the two n-type source regions and the surface of the n-type drift layer between them via a gate insulating film. It has the source electrode which contacts the surface with a base region in common, and the drain electrode which contacts the back surface of an n-type substrate (for example, refer patent document 1).
[0004]
Another conventional semiconductor element includes an n-type drift layer, a p-type base region disposed on or in the surface of the n-type drift layer, and an n-type that is separated from the n-type drift layer by the p-type base region. A source region, a source electrode that electrically connects the n-type source region and the p-type base region, a channel region of the p-type base region that connects the n-type source region and the n-type drift layer, It has a gate insulating film that controls an electrical resistance and is on an insulator region formed by an oxide film disposed between the channel region and the gate electrode.
[0005]
In this conventional semiconductor device, the n-type drift layer and the n-type source region are each made of n-conductivity type silicon carbide, the p-type base region is made of p-conductivity type silicon carbide, and boron is formed in the channel region. Is doped. Further, the p-type base region is provided with a partial region that partially extends below the n-type source region and directly contacts the n-type source region. This partial region is doped with aluminum and has a higher carrier concentration than the channel region of the base region (see, for example, Patent Document 2).
[0006]
[Patent Document 1]
Japanese Patent No. 3206727 (page 4, Fig. 1)
[Patent Document 2]
Japanese Patent No. 3022598 (first page, FIG. 2)
[0007]
[Problems to be solved by the invention]
According to the semiconductor element according to Patent Document 1, the formation of a channel region in which electrons flow near the interface between the gate electrode and the p-type base region can be controlled by the voltage applied to the gate electrode. It is possible to control conduction and interruption of current between the drain electrode.
[0008]
However, in this configuration, when a high voltage is applied between the source electrode and the drain electrode, the p-type base region is only formed by epitaxial growth, so that the depletion layer becomes n-type source region and n-type. It penetrates between drift layers. Therefore, there is a problem that it is impossible to cut off at a high voltage.
[0009]
To work around this issue, p-type base in a region a region which is doped with a high concentration of 10 ¹⁷ units per 1 cm ³ is formed by epitaxial growth, and depletion region with a high concentration of 1 cm ³ per 10 ¹⁸ single ion implantation Will be formed.
[0010]
In this case, the problem that the depletion layer penetrates between the n-type source region and the n-type drift layer can be avoided, but the depletion region where the electric field strength becomes maximum when a high voltage is applied can be formed by high-concentration ion implantation. Therefore, there is a problem that damage introduced by implantation adversely affects device characteristics.
[0011]
In addition, according to the semiconductor device according to Patent Document 2, aluminum (Al) is used as an impurity when forming a heavily doped region in the p-type base region, and the interface with the gate insulating film in the p-type base region. Boron (B) is used in the vicinity, but boron has a large activation energy as an acceptor compared with aluminum, and there is a problem that it is difficult to control the conductivity distribution in the semiconductor element.
[0012]
The present invention has been made to solve the above-described problems, and realizes a semiconductor device having high-performance device characteristics by avoiding high-concentration ion implantation in the formation of a depletion region serving as a high electric field portion. For the purpose.
[0013]
[Means for Solving the Problems]
According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a first step of forming a first conductive type withstand voltage layer and a second conductive type body region on a first conductive type semiconductor substrate by epitaxial growth; and the second conductive type. A second step of selectively forming a depletion region of the first conductivity type in the body region of the mold to a depth reaching the breakdown voltage layer of the first conductivity type by ion implantation; and a body of the second conductivity type by ion implantation using an implantation mask on both sides of the first conductivity type depletion region within the region, the source region of the first conductivity type, formed in a shallower depth than the body region of the second conductivity type In order to prevent a depletion layer when the high voltage is applied between the source electrode and the drain electrode between the first conductivity type source region and the first conductivity type breakdown voltage layer, , before used in the third step Heavily doped by implanting an impurity that gives the second conductivity type to the first conductivity type source region and a region sandwiched between the withstand voltage layer of the first conductivity type in said body region by using the implantation mask and a fourth step of forming a region, seen including a fifth step of forming a drain electrode on the back surface of the source electrode and the semiconductor substrate to be connected to the source region, in the fourth step, the implantation mask The angle formed by the ion implantation direction for implanting the impurity imparting the second conductivity type into the body region of the second conductivity type and the surface of the body region of the second conductivity type is determined by the ion implantation in the third step. The doped region wider than the source region of the first conductivity type is formed by making it smaller than the angle formed by the direction and the surface of the body region of the second conductivity type .
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
A semiconductor element according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 is a partial cross-sectional view of a semiconductor element according to Embodiment 1 of the present invention. In addition, in each figure, the same code | symbol shows the same or equivalent part.
[0015]
In FIG. 1, a silicon carbide n-type breakdown voltage layer (first conductivity type breakdown voltage layer) 2 is deposited on the upper surface of a silicon carbide (SiC) n-type substrate (first conductivity type substrate) 1 by epitaxial growth. A silicon carbide p-type body region (second conductivity type body region) 3 is deposited on the surface layer of the n-type breakdown voltage layer 2 by epitaxial growth.
[0016]
Inside the silicon carbide p-type body region 3 is an n-type source region (first conductivity type source region) 4 formed by ion implantation, and an n-type depletion selectively formed by ion implantation using an implantation mask. There are a region (a first conductivity type depletion region) 5 and a region 13 doped with an acceptor impurity.
[0017]
Further, another n-type source region 4 (not shown) is formed in the silicon carbide p-type body region 3, and on the surface exposed portion of the silicon carbide p-type body region 3 between the two n-type source regions 4. A gate electrode 23 is provided via the gate oxide film 6. Further, the upper surface of the gate electrode 23 is covered with the oxide film 7. A channel region 8 through which electrons flow is formed in the vicinity of the interface between the silicon carbide p-type body region 3 and the gate oxide film 6.
[0018]
A drain electrode 21 is provided on the lower surface of the silicon carbide n-type substrate 1, and a source electrode 22 is provided so as to be in contact with the surfaces of both the n-type source region 4 and the silicon carbide p-type body region 3. ing.
[0019]
Next, a manufacturing process of the semiconductor element having the above configuration will be described.
First, in the semiconductor element according to the first embodiment, silicon carbide n-type breakdown voltage layer 2 and silicon carbide p-type body region 3 are formed on silicon carbide n-type substrate 1 by epitaxial growth.
[0020]
Thereafter, n-type depletion region 5 is selectively formed in silicon carbide p-type body region 3 by ion implantation.
[0021]
Here, the formation of the silicon carbide p-type body region 3 by epitaxial growth is performed by doping with aluminum (Al). This doping is a doped region for preventing penetration of a depletion layer when a high voltage is applied later. Since 13 is formed by ion implantation, the concentration may be about 10 ¹⁶ per cm ³ . Therefore, the implantation of the n-type depletion region 5 can be suppressed to a concentration of about 10 ¹⁶ to 10 ¹⁷ per cm ³ .
[0022]
Next, the n-type source region 4 in the silicon carbide p-type body region 3 is perpendicular to the surface of the semiconductor element by using an implantation mask (ion non-permeable mask) 31 (not shown) on both sides of the n-type depletion region 5. It is formed by ion implantation from the direction.
[0023]
Subsequently, using the implantation mask 31, a region 13 doped with aluminum as an acceptor impurity for preventing penetration of a depletion layer when a high voltage is applied is formed in the silicon carbide p-type body region 3.
[0024]
Thereafter, by forming the gate oxide film 6, the gate electrode 23, the oxide film 7, the source electrode 22, and the drain electrode 21, the semiconductor element structure according to the first embodiment is obtained.
[0025]
Next, FIGS. 2 and 3 are partial cross-sectional views showing a process of forming the region 13 doped in the semiconductor element according to the first embodiment by ion implantation.
As shown in FIG. 2, the angle of ion implantation for forming the doped region 13 is the same as the angle of ion implantation for forming the n-type source region 4 (with respect to the surface of the semiconductor element). The ion implantation for forming the region 13 as shown in FIG. 3 may be oblique implantation with a predetermined angle with respect to the surface of the semiconductor element.
[0026]
In the case of the oblique implantation according to FIG. 3, a doped region 13 wider than the n-type source region 4 can be formed. In this case, ion implantation at a lower concentration than the implantation according to FIG. It becomes possible.
In addition, the ion implantation for forming the n-type source region 4 may be oblique implantation. In this case, the angle formed between the ion implantation direction at the time of acceptor implantation and the surface of the silicon carbide p-type body region 3 is n-type. By making the angle smaller than the angle formed by the ion implantation direction at the time of ion implantation of the source region 4 and the surface of the silicon carbide p-type body region 3, a wide doping region 13 can be formed.
[0027]
FIG. 4 is a step of forming the region 13 in the semiconductor element according to the first embodiment by ion implantation. The implantation mask is brought into contact with the surface of the silicon carbide p-type body region 3 and the implanted ions are substantially omitted. The first implantation mask layer 32b to be completely transmitted and the upper surface of the first implantation mask layer 32b are in contact with each other, and ions are not transmitted through the first implantation mask layer 32b (transmission of implanted ions is substantially complete). FIG. 6 is a partial cross-sectional view of a multilayer structure implantation mask 32 including a second implantation mask layer 32a. That is, the second implantation mask layer 32a blocks the transmission of about 99% of the implanted ions.
[0028]
By using the multilayer structure implantation mask 32 as shown in FIG. 4, the second implantation mask layer 32 a that is less permeable to ions than the first implantation mask layer 32 b is formed from the surface of the silicon carbide p-type body region 3. Since it is separated by the thickness of one implantation mask layer 32b, a wider doping region 13 can be formed than in the case of ion implantation shown in FIGS. Note that the ion-permeable mask layer 32b may have a structure of two or more layers instead of one layer.
[0029]
As described above, according to the method for manufacturing a semiconductor element according to the first embodiment, even when a high voltage is applied between source electrode 22 and drain electrode 21, silicon carbide p-type body region 3 is not formed. Since the highly doped region 13 exists, a semiconductor element in which the depletion layer can prevent penetration between the silicon carbide n-type source region 4 and the silicon carbide n-type breakdown voltage layer 2 can be configured.
[0030]
Furthermore, since the concentration of ion implantation in the n-type depletion region 5 where the electric field strength is greatest when a high voltage is applied is low, damage introduced by implantation does not adversely affect the device characteristics.
[0031]
Further, since aluminum is used as an impurity in both the region 13 doped at a high concentration in the silicon carbide p-type body region 3 and the vicinity of the interface between the silicon carbide p-type body region 3 and the gate oxide film 6. Also, the activation energy of the acceptor is small, and there is no problem in controlling the conductivity distribution in the semiconductor element.
[0032]
In the semiconductor device according to the first embodiment, silicon carbide p-type body region 3 is formed by epitaxial growth and then n-type depletion region 5 is formed by ion implantation. Although the silicon carbide p-type body region 3 is selectively formed on the p-type breakdown voltage layer 2, the p-type body is formed by relatively low concentration ion implantation after the growth of the silicon carbide n-type breakdown voltage layer 2. A configuration in which the region 3 is formed may be used, and a similar effect can be expected.
[0033]
Further, in the case of forming the silicon carbide p-type body region 3 by ion implantation, even if the n-type depletion region 5 is formed by ion implantation as a whole surface implantation, no p-type impurity enters the n-type depletion region 5 as selective implantation. The same effect can be expected with the configuration.
The above shows the method of performing the second step of forming the acceptor-doped region 13 after the first step of forming the silicon carbide n-type source region 4, but the order of these two steps is changed. The same effect can be obtained.
[0034]
Further, in the semiconductor element according to the first embodiment, the channel region 8 has been described with respect to the case where the original conductivity type is p-type, similar to the silicon carbide p-type body region 3, but the channel region 8 is doped with a donor impurity. The same effect can be expected even when the original conductivity type n-type region is thinly formed.
[0035]
Even in this configuration in which the channel region 8 is an n-type, by appropriately controlling the thickness and doping of the channel region 8, the channel region 8 is cut off when no voltage is applied to the gate electrode 23 that is a control terminal. It is possible.
[0036]
Further, in the semiconductor element according to the first embodiment, the case where aluminum is used as the acceptor impurity has been described. However, there is a problem in controlling the conductivity distribution in the element if other impurities have low activation energy. Therefore, the same effect can be expected.
[0037]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, after the p-type body region is formed by epitaxial growth with low concentration doping, the depletion region is formed by relatively low concentration ion implantation. Therefore, it is possible to reduce the influence of damage caused by ion implantation. Further, since an acceptor impurity for preventing penetration of the depletion layer is injected into the p-type body region using an n-type source region implantation mask, a simple fabrication process is achieved without increasing the number of photoengraving steps. Thus, high-performance device characteristics can be realized, and by using one type of acceptor impurity for the p-type body region, conductivity control can be facilitated and high-performance device characteristics can be realized.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view of a semiconductor element according to a first embodiment of the present invention.
FIG. 2 is a partial cross-sectional view showing a step of forming a highly doped region by ion implantation in the semiconductor element according to the first embodiment of the present invention.
FIG. 3 is a partial cross-sectional view showing a step of forming a highly doped region by ion implantation in the semiconductor element according to the first embodiment of the present invention.
FIG. 4 is a partial cross-sectional view in the case where the implantation mask has a multilayer structure in the step of forming a heavily doped region in the semiconductor element according to the first embodiment of the present invention by ion implantation;
[Explanation of symbols]
1 silicon carbide n-type substrate, 2 silicon carbide n-type pressure-resistant layer, 3 silicon carbide p-type body region (second conductivity type body region), 4 n-type source region, 5 n-type depletion region, 6 gate oxide film, 7 Oxide film, 8 channel region, 13 doped region, 21 drain electrode, 22 source electrode, 23 gate electrode, 31 implantation mask, 32 implantation mask of multi-layer structure.

Claims (4)

A first step of forming a first conductivity type withstand voltage layer and a second conductivity type body region on a first conductivity type semiconductor substrate by epitaxial growth;
A second step of selectively forming a depletion region of the first conductivity type in the body region of the second conductivity type to a depth reaching the first withstand voltage layer by ion implantation;
By ion implantation using an implantation mask on both sides of the depletion region of the first conductivity type in the second conductivity type in the body region, the source region of the first conductivity type, than the body region of the second conductivity type A third step of forming at a shallow depth ;
In order to prevent a depletion layer when a high voltage is applied between the source electrode and the drain electrode from penetrating between the first conductivity type source region and the first conductivity type breakdown voltage layer , By implanting an impurity imparting the second conductivity type into a region sandwiched between the first conductivity type source region and the first conductivity type breakdown voltage layer in the body region using the implantation mask used in the process. A fourth step of forming a heavily doped region;
Look including a fifth step of forming a drain electrode on the back surface of the semiconductor substrate and the source electrode connected to the source region,
In the fourth step, an angle formed by an ion implantation direction for implanting an impurity imparting the second conductivity type into the body region of the second conductivity type using the implantation mask and a surface of the body region of the second conductivity type Is made smaller than the angle formed by the ion implantation direction in the third step and the surface of the body region of the second conductivity type, thereby forming the doped region wider than the source region of the first conductivity type. A method for manufacturing a semiconductor device, comprising: The implantation mask includes at least one first implantation mask layer that contacts the surface of the body region of the second conductivity type, and the first implantation mask layer that contacts the upper surface of the first implantation mask layer. A multi-layered implantation mask including a second implantation mask layer that does not transmit ions;
In the fourth step, an ion implantation direction for implanting an impurity imparting a second conductivity type into the body region of the second conductivity type using the multilayer structure implantation mask, a surface of the body region of the second conductivity type, and The doped region wider than the source region of the first conductivity type by making the angle formed by the angle smaller than the angle formed by the ion implantation direction in the third step and the surface of the body region of the second conductivity type. The method of manufacturing a semiconductor device according to claim 1, wherein: Wherein a second conductivity type is p-type, semiconductor according to claim 1 or 2, characterized by using one type of impurity as an impurity which gives a second conductivity type to be implanted into the body region of the second conductivity type Device manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 3 , wherein aluminum is used as the one kind of impurity .

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