JP4023082B2

JP4023082B2 - Semiconductor device and manufacturing method thereof

Info

Publication number: JP4023082B2
Application number: JP2000311720A
Authority: JP
Inventors: 達也大高; 洋杉本; 幸雄鈴木
Original assignee: Hitachi Cable Ltd
Current assignee: Hitachi Cable Ltd
Priority date: 2000-10-05
Filing date: 2000-10-05
Publication date: 2007-12-19
Anticipated expiration: 2020-10-05
Also published as: JP2002118217A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法に関し、特に、配線テープに放熱板を接着したテープＢＧＡ（Ball Grid Array ）型の半導体装置に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
従来、ＢＧＡ型の半導体装置の一つに、ＴＡＢ（Tape Automated Bonding）テープのような薄い配線テープを用いたテープＢＧＡ（以下、Ｔ−ＢＧＡと称する）型の半導体装置がある。
【０００３】
前記Ｔ−ＢＧＡ型の半導体装置は、図１２（ａ）及び図１２（ｂ）に示すように、中心部が開口された絶縁性のテープ状基材１０１の第１主面（表側面）に第１配線１０２Ａ及びその外部接続端子１０２Ｂが形成された配線テープ（ＴＡＢテープ）１を設け、前記配線テープ１の第１主面（表側面）と対向する第２主面（裏側面）に、例えば、エポキシ系樹脂のような熱硬化性樹脂からなる絶縁体（接着材）２を介在させて放熱板３を接着し、前記放熱板３の前記配線テープ１の開口部１Ａ内に半導体チップ４を接着し、前記半導体チップ４の外部電極４０１と前記第１配線１０２Ａとがボンディングワイヤ５で接続されており、前記半導体チップ４、ボンディングワイヤ５、及びそれらの接続部をモールド樹脂６により封止した構成になっている。また、前記第１配線の外部接続端子１０２Ｂ上には、例えば、Ｐｂ−Ｓｎ系はんだ等からなるボール端子７が接続されている。
【０００４】
また、前記Ｔ−ＢＧＡ型の半導体装置では、前記配線テープ（ＴＡＢテープ）１に、例えば、前記テープ基材１０１の第１主面及び第２主面の両方に配線を形成した２メタル構造の配線テープを用いて、図１３（ａ）及び図１３（ｂ）に示すように、前記テープ基材１０１の第１主面（表側面）に信号配線等の第１配線１０２Ａ及びその外部接続端子１０２Ｂを設け、前記テープ基材１０１の第２主面（裏側面）に電源配線などの第２配線１０３を設けている。また、前記テープ基材１０１の第２主面に設けられた前記第２配線１０３の周囲の領域を除く領域には、図１３（ａ）に示すように接地電位層（グランド面）１０４が設けられている。前記第２配線１０３及び接地電位層１０４上には銅めっき層（第１めっき層）１０５が設けられており、前記銅めっき層１０５は、前記テープ基材１０１の所定位置に設けられたビア孔により前記第１配線１０２Ａ及びその外部接続端子１０２Ｂと接続されている。
【０００５】
また、前記第１配線１０２Ａ及び外部接続端子１０２Ｂの接続部分以外の領域は、外部からの汚染物質や傷等から配線を保護するために、例えば、ソルダレジスト（ＳＲ）やフォトソルダレジスト（ＰＳＲ）等の配線保護膜１０６が設けられている。前記第１配線１０２Ａ及びその外部接続端子１０２Ｂの接続部には、前記第１配線１０２Ａのワイヤボンディング性及び前記外部接続端子１０２Ｂのはんだ接続性をよくするために、例えば、ニッケル（Ｎｉ）めっき層及び金（Ａｕ）めっき層を積層させためっき層（第２めっき層）１０７が形成されている。
【０００６】
また、前記２メタル構造の配線テープ（ＴＡＢテープ）では、前記接着剤を貼り付ける際、または前記接着剤を硬化させる際に、各構成材料に残留した酸素もしくは材料を透過した酸素により、接着界面、すなわち第２配線１０３、接地電位層１０４、及びそれらの表面に設けられた銅めっき層１０５の銅表面を酸化させ、酸化スケールの発生につながる事が容易に予測される。酸化スケールそのものは非常に脆弱な酸化物であり、酸化スケール内での剥離が容易に発生するので、装置の信頼性が低下する。そのため、前記第２配線１０３、接地電位層１０４、及び銅めっき層１０５の酸化を防止するために、図１１（ｂ）に示したようなめっき層１０７を設ける必要がある。
【０００７】
前記２メタル構造の配線テープ（ＴＡＢテープ）では、ワイヤボンディング性及びはんだ接続性の向上のために、第１配線１０２Ａ及び外部接続端子１０２Ｂの表面にニッケルめっき及び金めっきを施してめっき層１０７を形成するため、前記めっき層１０７を形成する際に、前記第２配線１０３及び接地電位層１０４の表面にもニッケルめっき及び金めっきを施してめっき層１０７を形成することで、製造工程を増やすことなく安価に、前記第２配線１０３、接地電位層１０４及び銅めっき層１０５の酸化を防ぐことができる。
【０００８】
ここで、前記第２配線１０３及び接地電位層１０４の表面の銅めっき層１０５にめっき層１０７を形成して、その表面を金めっき処理した場合、前記接着剤２との密着性が、銅の場合に比べ一般的に低くなるが、前記接着剤２として用いる材料を適宜選定する事により、信頼性の目安となるピール強度の値２kgf ／cmを十分確保することができる。
【０００９】
前記Ｔ−ＢＧＡ型の半導体装置は、装置の小型化にともない、使用する配線テープ１に形成する配線が微細化されるとともに隣り合う配線間の間隔も狭くなってきており、隣り合う配線間での電磁界結合、言い換えると配線間の相互インダクタンスによるノイズの発生が問題になる。このとき、前記配線間で生じるノイズにもっとも影響があるのは、前記配線の大部分を占める信号配線に印加される電圧との電位差が大きい、前記半導体チップ４の動作電圧を供給する電源配線である。そのため、前記テープ基材の前記信号配線（第１配線１０２Ａ）が形成された第１主面の裏側に電源配線（第２配線１０３）を形成し、前記電源配線を信号配線から遠ざけることにより、前記信号配線と電源配線の間の相互インダクタンスによるノイズを低減させている。
【００１０】
また、前記配線テープ（ＴＡＢテープ）１の第１主面上に設けられる信号配線間でも、隣り合う配線同士の間隔が狭くなると、共振現象が発生してクロックパルスなどの信号波形が乱れるという問題がある。そのため、図１３（ａ）に示すように、前記配線テープ（ＴＡＢテープ）の第２主面の、前記第２配線１０３及びその周囲を除く領域に接地電位層（グランド面）１０４を設ける。前記接地電位層（グランド面）１０４には、前記第１配線１０２Ａに流れる電流により発生する磁束を打ち消すような方向に渦電流が流れるので、第１配線１０２Ａの自己インダクタンスや配線間の相互インダクタンス、誘電性クロストークを見かけ上低減することができるので、例えば、前記第１配線（信号配線）１０２に高周波信号が印加される場合などに有効であり、電気信号の信頼性及び信号の伝送速度の高速化を図ることができる。
【００１１】
【発明が解決しようとする課題】
しかしながら、前記従来の技術では、２メタル構造の配線テープを用いて、前記配線テープ１の第２配線１０３及び接地電位層（グランド面）１０４上に絶縁体（接着材）２を介して放熱板３を接着するときに、シート状の接着材を用いるため、図１３（ｂ）に示すように、前記第２配線１０３と接地電位層１０４の間にボイド１１ができて空気が残ってしまう。そのため、製造工程中における加熱処理や、製品として使用中に半導体チップ４から生じる熱により、前記ボイド１１内に残った空気が膨張して、前記第２配線１０３の周辺の接着材２が剥離するという問題があった。
【００１２】
また、前記第２配線１０３及び接地電位層１０４の表面のめっき層１０７は、前記接着材２との接着性が必ずしもよくないので、前記第２配線１０３の周辺で接着材２が剥離してクラックが生じると、そのクラックが進行して最終的に配線テープ１と接着材２が剥離してしまうため、装置の信頼性が低下するという問題があった。
【００１３】
本発明の目的は、テープ基材の両面に配線が形成された配線テープに接着材を介して放熱板を接着したＴ−ＢＧＡ型の半導体装置において、前記配線テープと接着材の接着面に生じるボイドを低減することが可能な技術を提供することにある。
【００１４】
本発明の他の目的は、テープ基材の両面に配線が形成された配線テープに接着材を介して放熱板を接着したＴ−ＢＧＡ型の半導体装置において、前記配線テープと接着材の接着面での剥離を低減することが可能な技術を提供することにある。
【００１５】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面によって明らかになるであろう。
【００１６】
【課題を解決するための手段】
本発明において開示される発明の概要を説明すれば、以下のとおりである。
【００１７】
（１）中心部が開口された絶縁性のテープ状基材の第1 主面（表側面）に第１配線及びその外部接続端子が形成された配線テープを設け、前記配線テープの第１主面（表側面）と対向する第２主面（裏側面）に絶縁体を介在させて放熱板を設け、前記配線基板の開口部内に半導体チップを設け、前記半導体チップの外部電極と前記第１配線とをボンディングワイヤで接続し、前記半導体チップ、ボンディングワイヤ、及びそれらの接続部を樹脂により封止してなる半導体装置において、前記配線テープの前記第２主面に第２配線を設け、前記第２配線及び前記第２配線の周囲を除く領域に接地電位層（グランド面）を設け、前記テープ基材の所定位置に前記第２配線及び接地電位層と前記第１配線及びその外部接続端子を接続する導通ビアを設け、前記第２配線の周囲に、前記第２配線と前記接地電位層の間を絶縁する絶縁体が設けられている半導体装置である。
【００１８】
前記（１）の手段によれば、前記第１主面及び第２主面の両面に配線が形成された２メタル構造の配線テープ（ＴＡＢテープ）を用いたＴ−ＢＧＡ型の半導体装置において、前記配線テープの第２配線の周囲に絶縁体を設けて前記第２配線と接地電位層の間を絶縁することにより、前記配線テープの第２主面に絶縁体（接着材）を介して放熱板を接着したときに、前記第２配線と接地電位層の間にボイドができることを防げる。そのため、製造工程中における加熱処理や、使用中に半導体チップから発生する熱でボイドが膨張して前記第２配線と第１絶縁体が剥離することを防げる。また、前記第２配線と絶縁体（接着材）の剥離を低減できるため、配線テープと前記第１絶縁体の接着面での剥離を低減させることができ、装置の信頼性を向上することができる。
【００１９】
また、前記２メタル構造の配線テープ（ＴＡＢテープ）では、第２配線１０３及び接地電位層１０４の銅表面の酸化を防ぐためにめっき処理を施す必要がある。前記２メタル構造の配線テープは、第１配線及び外部接続端子の表面にニッケルめっき及び金めっきを施してめっき層を形成するため、前記めっき層を形成する際に、前記第２配線及び接地電位層の表面にもニッケルめっき及び金めっきを施してめっき層を形成することで、製造工程を増やすことなく安価に、前記第２配線及び接地電位層の酸化を防ぐことができる。
【００２０】
ここで、前記第２配線及び接地電位層にめっき層を形成して、その表面を金めっき処理した場合、前記接着剤との密着性が、銅の場合に比べ一般的に低くなるが、前記接着剤として用いる材料を適宜選定する事により、信頼性を十分確保することができる。
【００２１】
（２）中心部が開口された絶縁性のテープ状基材の第１主面（表側面）上に第１配線及びその外部接続端子が形成された配線テープを形成する配線テープ形成工程と、前記配線テープの第１主面（表側面）と対向する第２主面（裏側面）に、前記テープ基材の開口部と平面的に重なる位置に開口部を有するフィルム状の絶縁体を配置する絶縁体配置工程と、前記絶縁体の前記配線テープが配置された面と対向する面に放熱板を配置して、前記配線テープと放熱板を接着する放熱板接着工程と、前記放熱板の、前記配線テープの開口部に半導体チップを搭載する半導体チップ搭載工程と、前記半導体チップの外部電極と前記配線テープの配線をボンディングワイヤにより接続する配線接続工程と、前記配線基板の開口部の半導体チップ、ボンディングワイヤ、及びそれらの接続部を封止する封止工程とを備える半導体装置の製造方法において、前記配線テープ形成工程は、前記テープ基材の第１主面及び第２主面のそれぞれに導電性薄膜を形成し、前記テープ基材の所定位置に前記第２主面側からビア孔を形成し、前記導電性薄膜上及びビア孔内部に第１めっき層を形成し、前記第２主面上の導電性薄膜をエッチングして、第２配線及び接地電位層（グランド面）を形成し、前記配線テープの中心部に開口部を形成し、前記第１主面上の導電性薄膜をエッチングして、第１配線及びその外部接続端子を形成し、前記第１主面上に、前記第１配線及びその外部接続端子が部分的に露出するように配線保護膜を形成し、前記第１配線及びその外部接続端子の露出面、前記第２配線及び接地電位層表面に第２めっき層を形成し、前記第２配線の周辺に液状の絶縁体を塗布して硬化させ、前記第２配線と接地電位層間を絶縁する。
【００２２】
前記（２）の手段によれば、前記第１主面及び第２主面の両面に配線が形成された２メタル構造の配線テープ（ＴＡＢテープ）を形成し、前記２メタル構造の配線テープを用いてＴ−ＢＧＡ型の半導体装置を製造する際に、前記配線テープの第１主面に第１配線、外部接続端子を形成し、前記テープ基材の第２主面に第２配線及び接地電位層（グランド面）を形成した後、前記配線テープの第２配線の周囲に液状の絶縁体を塗布して硬化させることにより、前記第２配線と接地電位層の間を前記絶縁体で埋めることができる。そのため、その後の工程で前記第２配線及び接地電位層上に絶縁体（接着材）を介して放熱板を接着したときに、前記第２配線と接地電位層の間にボイドができないので、製造工程中における加熱処理時のボイドの膨張による前記第２配線と絶縁体（接着材）の剥離を防ぐことができる。
【００２３】
また、前記第１配線及び外部接続端子に、部分的にめっき処理を行う際に、前記第２配線及び接地電位層（グランド面）にも同時にめっき処理を行うことで、前記第２配線及び接地電位層の酸化を防ぎ、前記接着材の剥離を防ぐことができる。また、同時にめっき処理をするので製造工程が増えず、製造コストが増大するのを抑えることができる。
【００２４】
以下、本発明について、図面を参照して実施の形態（実施例）とともに詳細に説明する。
【００２５】
なお、実施例を説明するための全図において、同一機能を有するものは、同一符号をつけ、その繰り返しの説明は省略する。
【００２６】
【発明の実施の形態】
（実施例）
図１乃至図４は、本発明による一実施例の半導体装置の概略構成を示す模式図であり、図１（ａ）は半導体装置の平面図、図１（ｂ）は図１（ａ）のＡ−Ａ’線での断面図、図２（ａ）は配線テープの第１主面側から見た模式平面図、図２（ｂ）は図２（ａ）の裏面図、図３は図２（ｂ）の部分拡大図、図４（ａ）は図３のＢ−Ｂ’線での断面図、図４（ｂ）は図３のＣ−Ｃ’線での断面図である。なお、図１（ｂ）の断面図では、本実施例の半導体装置の構成を把握しやすくするために平行斜線（ハッチング）を省略して示している。
【００２７】
図１乃至図４において、１は配線テープ、１Ａは開口部、１０１はテープ状基材、１０２Ａは第１配線、１０２Ｂは第１配線の外部接続端子、１０３は第２配線、１０４は接地電位層（グランド面）、１０５は銅めっき層（第１めっき層）、１０６は配線保護膜、１０７はめっき層（第２めっき層）、１０８は絶縁体、２は絶縁体（接着材）、３は放熱板、４は半導体チップ、４０１は外部電極、５はボンディングワイヤ、６はモールド樹脂、７はボール端子、８は接着剤である。
【００２８】
本実施例の半導体装置は、図１及び図２に示すように、中心部が開口された絶縁性のテープ状基材１０１の第1 主面（表側面）に第１配線１０２Ａ及びその外部接続端子１０２Ｂが形成された配線テープ１と、前記配線テープ１の第１主面（表側面）と対向する第２主面（裏側面）に絶縁体２を介在させて設けられる放熱板３と、前記配線テープ１の開口部１Ａ内に設けられる半導体チップ４と、前記半導体チップ４の外部電極４０１と前記第１配線１０２Ａとを接続するボンディングワイヤ５と、前記半導体チップ４、ボンディングワイヤ５、及びそれらの接続部がモールド樹脂６により封止されており、前記外部接続端子１０２Ｂ上にボール端子７が設けられたテープＢＧＡ（Ｔ−ＢＧＡ）型の半導体装置である。
【００２９】
また、本実施例の半導体装置で用いる前記配線テープ（ＴＡＢテープ）１は、前記配線テープの第１主面及び第２主面の両面に配線が形成された２メタル構造のＴＡＢテープであり、図３及び図４に示すように、前記配線テープ１の前記第２主面に第２配線１０３が設けられ、前記第２配線１０３及び前記第２配線１０３の周囲を除く領域に接地電位層（グランド面）１０４が設けられている。また、前記第２配線１０３及び接地電位層１０４は、図４に示すように表面に銅めっき層（第１めっき層）１０５が設けられている。前記銅めっき層１０５は、前記テープ基材１０１の所定位置に設けられたビア孔を介して前記第１配線１０２Ａ及びその外部接続端子１０２Ｂと接続される。
【００３０】
また、前記配線テープ１の第１主面上に形成された第１配線１０２Ａ及び外部接続端子１０２Ｂの接続部以外の部分は、例えば、ソルダレジスト（ＳＲ）やフォトソルダレジスト（ＰＳＲ）のような配線保護膜１０６により保護されている。
【００３１】
また、前記第１配線１０２Ａ及びその外部接続端子１０２Ｂの接続部には、例えば、ニッケルめっき層および金めっき層を積層しためっき層（第２めっき層）１０７が設けられている。また、前記第２配線１０３及び接地電位層（グランド面）１０４上の銅めっき層１０５の表面にも前記めっき層１０７が形成されている。また、前記第２配線１０３の周囲には、前記第２配線１０３と前記接地電位層１０４の間を絶縁する絶縁体１０８が設けられている。
【００３２】
また、前記配線テープ１と放熱板３を接着する絶縁体（接着材）２は、例えば、熱硬化性のエポキシ系樹脂などが用いられる。
【００３３】
また、前記放熱板３は、前記半導体チップ４で発生する熱を効率良く放熱するとともに、前記配線テープ１の補強材としても機能させるため、例えば、銅（Ｃｕ）等の材料が用いられる。
【００３４】
本実施例のＴ−ＢＧＡ型の半導体装置では、前記配線テープ１の第２配線１０３の周辺は、図３及び図４に示すように、前記第２配線１０３と前記接地電位層１０４の間を絶縁する絶縁体１０８が設けられている。そのため、前記配線テープ１の第２配線１０３及び接地電位層１０４上に前記絶縁体（接着材）２を介して前記放熱板３を接着するときに、前記第２配線１０３と接地電位層１０４の間にボイドが生じないので、例えば、使用中に半導体チップ４から発生する熱でボイドが膨張して前記第２配線１０３と絶縁体（接着材）２の接着面の剥離が生じることを防げる。また、前記第２配線１０３及び接地電位層（グランド面）１０４上のめっき層１０７と絶縁体（接着材）２の接着面の接着力が弱い場合でも、前記第２配線１０３部分での剥離を防げ、その剥離部分からのクラックの進行による配線テープ１と絶縁体２が剥離することを防げる。
【００３５】
図５乃至図１０は、本実施例の半導体装置の製造方法を説明するための各製造工程における模式図である。なお、図５（ｂ）、図６、図８（ｂ）、及び図９（ｂ）は、図３のＢ−Ｂ’線での断面に相当する断面図を示している。
【００３６】
以下、図５乃至図１０に沿って、本実施例の半導体装置の製造方法について説明する。なお、本実施例で使用する配線テープ（ＴＡＢテープ）１の製造方法は、例えば、文献「Norio Okabe, Yasuhiro Kameyama, Hiroki Tanaka, Katsutoshi Taga, "2 Metal Layer TBGA Tape for High Speed, High Pin Count LSI Packaging", HITACHI CABLE REVIEW, No.16, (August 1997), 49-54 」等に記載されたような、従来の２メタル構造の配線テープの製造方法とほぼ同様であるため、各工程の詳細な説明は省略する。
【００３７】
まず、本実施例の半導体装置で使用する２メタル構造の配線テープ（ＴＡＢテープ）を製造するために、図５（ａ）及び図５（ｂ）に示したような、例えば、ポリイミドのような絶縁性のテープ基材の両面に、銅箔等の導電性薄膜１０９Ａ，１０９Ｂが形成された銅箔付きテープ９を準備する。前記銅箔付きテープは、例えば、圧延銅箔をテープ基材１０１の両面に接着剤で張り合わせたものや、例えば、スパッタリングなどで前記テープ基材１０１上に銅を蒸着して薄膜を形成することにより得られる。前記銅箔付きテープ９は細長いテープ状のものであって、図５（ａ）に示したような配線テープ形成領域１’が複数個連続して設けられている。
【００３８】
次に、図６（ａ）に示すように、前記銅箔付きテープ９の所定位置に、例えば、炭酸ガスレーザにより、一方の主面（第２主面）からもう一方の主面（第１主面）の導電性薄膜に達するビア孔１０を形成した後、図６（ｂ）に示すように、第２主面全面、及び前記ビア孔１０の側面に第１めっき層として、銅（Ｃｕ）めっき層１０５を形成する。前記銅めっきは、例えば、電解めっき法、もしくは無電解めっき法と電解めっき法を組み合わせた方法で形成する。
【００３９】
次に、前記銅箔付きテープ９の第２主面側、言い換えると前記ビア孔１０を開口した面をエッチングして、図６（ｃ）に示すように、第２配線１０３及び前記第２配線１０３の周囲の領域を除く接地電位層（グランド面）１０４を形成する。なお、前記第２配線１０３及び接地電位層１０４は、例えば、図２（ｂ）に示したようなパターンで形成される。
【００４０】
次に、前記配線基板形成領域１’の中央部に、例えば、炭酸ガスレーザ等で、図７（ａ）に示すように、開口部１Ａを形成し、その後、前記導電性薄膜１０９Ａをエッチングして、図７（ａ）及び図７（ｂ）に示すように、第１配線１０２Ａ及びその外部接続端子１０２Ｂを形成する。なお、図７（ａ）では一部省略しているが、各外部接続端子１０２Ｂは、第１配線１０２Ａと直接、もしくは第２配線等を介して前記開口部１Ａの周囲に引き回されている。
【００４１】
次に、図８（ａ）に示すように、前記第１配線１０２Ａ及びその外部接続端子１０２Ｂを外部からの汚染物質や傷から保護するために、例えば、ソルダレジストやフォトソルダレジストのような配線保護膜１０６を形成する。
【００４２】
次に、電解めっき法、無電解めっき法、あるいは電気めっき法などを用いて、図８（ｂ）に示すように、前記第１配線１０２Ａのワイヤボンディング性や外部接続端子１０２Ｂのはんだ接続性をよくするためのめっき層（第２めっき層）１０７を形成する。このとき同時に、前記第２主面の第２配線１０３及び接地電位層１０４上の銅めっき層１０５の表面にも、酸化を防止するためにめっき層１０７を形成する。前記めっき層１０７は、例えば、ニッケル（Ｎｉ）めっき層及び金（Ａｕ）めっき層を積層して形成する。
【００４３】
次に、図９（ａ）及び図９（ｂ）に示すように、前記第２配線１０３の周辺に、例えば、ソルダレジスト（ＳＲ）のような液状の絶縁体１０８を塗布して硬化させると、本実施例のＴ−ＢＧＡ型の半導体装置で用いる２メタル構造の配線テープ（ＴＡＢテープ）１が形成される。
【００４４】
次に、図１０（ａ）及び図１０（ｂ）に示すように、前記配線テープ１の前記第２配線１０３及び接地電位層１０４上に、前記配線テープ１の開口部１Ａと平面的に重なる位置に開口部を有するフィルム状の絶縁体（接着材）２を配置し、前記絶縁体２の前記配線テープ１が配置された面と対向する面に放熱板３を配置して、前記配線テープ１と放熱板３を接着する。このとき、前記絶縁体（接着材）２として、例えば、熱硬化性のエポキシ系樹脂などが用いられるため、前記配線テープ１と放熱板３を接着するために加熱処理をするが、前記配線テープ１の第２配線１０３と接地電位層（グランド面）１０４の間は絶縁体１０８で埋められているためボイドがなく、加熱時のボイドの膨張による前記第２配線１０３と絶縁体（接着材）２の剥離を防ぐことができる。またこのとき、前記絶縁体（接着材）２は、前記第２配線１０３及び接地電位層１０４表面の金めっきとの密着性をよくするために、主材料及び添加物の量を適宜調整して、所定の密着信頼性を得られるようにする。
【００４５】
次に、図１１（ａ）及び図１１（ｂ）に示すように、前記放熱板３の、前記配線テープの開口部１Ａ内に半導体チップ４を搭載し、前記半導体チップ４の外部電極４０１と前記配線テープ１の第１配線１０２Ａをボンディングワイヤ５により接続する。
【００４６】
その後、前記配線テープ１の開口部１Ａ内の半導体チップ４、ボンディングワイヤ５及びそれらの接続部をモールド樹脂６で封止した後、前記外部接続端子１０２Ｂ上にボール端子７を接続すると、図１乃至図４に示したような、本実施例のＴ−ＢＧＡ型の半導体装置を得ることができる。またこのときも、前記ボール端子７を接続する際には、加熱して前記ボール端子７を部分的に融解させるが、前記第２配線１０３と接地電位層１０４の間にボイドがないため、前記第２配線１０３と絶縁体（接着材）２の剥離を防ぐことができる。
【００４７】
以上説明したように、本実施例の半導体装置では、前記配線テープ（ＴＡＢテープ）１の、放熱板３が接着される面に形成される第２配線１０３の周囲に、液状の絶縁体１０５を塗布して硬化させ、前記第２配線１０３と前記第２配線１０３の周囲に設けられる接地電位層（グランド面）１０４の間を前記絶縁体１０５で埋めることにより、前記第２配線１０３及び接地電位層１０４上にシート状の絶縁体（接着材）２を接着したときに、前記第２配線１０３の周囲にボイドができないようにすることができる。そのため、製造工程中の加熱処理により、前記ボイド内に残った空気が膨張して前記第２配線１０３と絶縁体（接着材）２の接着面が剥離することを防げる。また、前記第２配線１０３と絶縁体（接着材）２の接着面での剥離が防げるため、前記配線テープ１と絶縁体２の接着面内でのクラックの発生を少なくすることができるので、前記配線テープ１と絶縁体２の剥離による半導体装置の不良を低減することができる。
【００４８】
また、前記第１配線１０２Ａ及びその外部接続端子１０２Ｂ上に、めっき層を形成する際に、前記第２配線１０３及び接地電位層１０４の表面にも同様のめっき層１０７を形成することで、前記第２配線１０３及び接地電位層１０４の酸化を防げるので、前記第２配線１０３及び接地電位層１０４の酸化による前記接着材２との接着面での剥がれを防げ、半導体装置の不良を防ぐことができる。
【００４９】
以上、本発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることはもちろんである。
【００５０】
【発明の効果】
本発明において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。
【００５１】
（１）テープ基材の両面に配線が形成された配線テープに接着材を介して放熱板を接着したＴ−ＢＧＡ型の半導体装置において、前記配線テープと接着材の接着面にボイドが生じることを防ぐことができる。
【００５２】
（２）テープ基材の両面に配線が形成された配線テープに接着材を介して放熱板を接着したＴ−ＢＧＡ型の半導体装置において、前記配線テープと接着材の接着面での剥離を低減することができる。
【図面の簡単な説明】
【図１】本発明による一実施例の半導体装置の概略構成を示す模式図である。
【図２】本実施例１の半導体装置で用いる配線テープの概略構成を示す模式図である。
【図３】図２（ｂ）の部分拡大図である。
【図４】図３のＢ−Ｂ’線での模式断面図及びＣ−Ｃ’線での模式断面図である。
【図５】本実施例の半導体装置の製造方法を説明するための模式図である。
【図６】本実施例の半導体装置の製造方法を説明するための模式図である。
【図７】本実施例の半導体装置の製造方法を説明するための模式図である。
【図８】本実施例の半導体装置の製造方法を説明するための模式図である。
【図９】本実施例の半導体装置の製造方法を説明するための模式図である。
【図１０】本実施例の半導体装置の製造方法を説明するための模式図である。
【図１１】本実施例の半導体装置の製造方法を説明するための模式図である。
【図１２】従来のＴ−ＢＧＡ型の半導体装置の概略構成を示す模式図である。
【図１３】従来のＴ−ＢＧＡ型の半導体装置の概略構成を示す模式図である。
【符号の説明】
１配線テープ（ＴＡＢテープ）
１Ａ開口部
１０１テープ状基材
１０２Ａ第１配線
１０２Ｂ外部接続端子
１０３第２配線
１０４接地電位層
１０５銅めっき層（第１めっき層）
１０６配線保護膜
１０７めっき層（第２めっき層）
１０８絶縁体
１０９Ａ，１０９Ｂ銅箔
２絶縁体（接着材）
３放熱板
４半導体チップ
４０１外部電極
５ボンディングワイヤ
６モールド樹脂
７ボール端子
８接着剤
９銅箔付きテープ
１０ビア孔
１１ボイド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technology effective when applied to a tape BGA (Ball Grid Array) type semiconductor device in which a heat sink is bonded to a wiring tape.
[0002]
[Prior art]
Conventionally, as one of BGA type semiconductor devices, there is a tape BGA (hereinafter referred to as T-BGA) type semiconductor device using a thin wiring tape such as a TAB (Tape Automated Bonding) tape.
[0003]
As shown in FIGS. 12A and 12B, the T-BGA type semiconductor device is formed on the first main surface (front side) of the insulating tape-like base material 101 whose center is opened. A wiring tape (TAB tape) 1 in which the first wiring 102A and its external connection terminal 102B are formed is provided, and a second main surface (back side surface) opposite to the first main surface (front side surface) of the wiring tape 1 is provided. For example, an insulator (adhesive material) 2 made of a thermosetting resin such as an epoxy resin is interposed, and the heat sink 3 is bonded, and the semiconductor chip 4 is placed in the opening 1A of the wiring tape 1 of the heat sink 3. The external electrode 401 of the semiconductor chip 4 and the first wiring 102A are connected by a bonding wire 5, and the semiconductor chip 4, the bonding wire 5 and their connecting portions are sealed with a mold resin 6. It became the composition There. Further, on the external connection terminal 102B of the first wiring, for example, a ball terminal 7 made of Pb—Sn solder or the like is connected.
[0004]
In the T-BGA type semiconductor device, the wiring tape (TAB tape) 1 has, for example, a two-metal structure in which wiring is formed on both the first main surface and the second main surface of the tape substrate 101. Using a wiring tape, as shown in FIGS. 13A and 13B, the first wiring 102A such as signal wiring and its external connection terminals are provided on the first main surface (front side) of the tape base 101. 102B is provided, and a second wiring 103 such as a power supply wiring is provided on the second main surface (back side surface) of the tape substrate 101. Further, in a region excluding the region around the second wiring 103 provided on the second main surface of the tape substrate 101, a ground potential layer (ground surface) 104 is provided as shown in FIG. It has been. A copper plating layer (first plating layer) 105 is provided on the second wiring 103 and the ground potential layer 104, and the copper plating layer 105 is a via hole provided at a predetermined position of the tape base material 101. Thus, the first wiring 102A and its external connection terminal 102B are connected.
[0005]
In addition, the region other than the connection portion of the first wiring 102A and the external connection terminal 102B is, for example, a solder resist (SR) or a photo solder resist (PSR) in order to protect the wiring from contaminants and scratches from the outside. A wiring protective film 106 is provided. In order to improve the wire bonding property of the first wiring 102A and the solder connection property of the external connection terminal 102B, for example, a nickel (Ni) plating layer is formed on the connection portion of the first wiring 102A and its external connection terminal 102B. And the plating layer (2nd plating layer) 107 which laminated | stacked the gold | metal | money (Au) plating layer is formed.
[0006]
Further, in the two-metal structure wiring tape (TAB tape), when the adhesive is applied, or when the adhesive is cured, an adhesive interface is formed by oxygen remaining in each constituent material or oxygen transmitted through the material. That is, it is easily predicted that the copper surface of the second wiring 103, the ground potential layer 104, and the copper plating layer 105 provided on the surface of the second wiring 103 will be oxidized, resulting in the generation of oxide scale. The oxide scale itself is a very fragile oxide, and peeling within the oxide scale easily occurs, so that the reliability of the apparatus is lowered. Therefore, in order to prevent oxidation of the second wiring 103, the ground potential layer 104, and the copper plating layer 105, it is necessary to provide a plating layer 107 as shown in FIG.
[0007]
In the two-metal wiring tape (TAB tape), the surface of the first wiring 102A and the external connection terminal 102B is subjected to nickel plating and gold plating in order to improve the wire bonding property and the solder connection property, thereby forming the plating layer 107. Therefore, when forming the plating layer 107, the surface of the second wiring 103 and the ground potential layer 104 is also subjected to nickel plating and gold plating to form the plating layer 107, thereby increasing the number of manufacturing steps. Therefore, oxidation of the second wiring 103, the ground potential layer 104, and the copper plating layer 105 can be prevented at low cost.
[0008]
Here, when the plating layer 107 is formed on the copper plating layer 105 on the surface of the second wiring 103 and the ground potential layer 104 and the surface thereof is gold-plated, the adhesion to the adhesive 2 is made of copper. Although generally lower than the case, by appropriately selecting the material used as the adhesive 2, a peel strength value of 2 kgf / cm, which is a measure of reliability, can be sufficiently secured.
[0009]
In the T-BGA type semiconductor device, with the miniaturization of the device, the wiring formed on the wiring tape 1 to be used is miniaturized and the interval between the adjacent wirings is narrowed. In other words, the generation of noise due to mutual inductance between wires becomes a problem. At this time, the noise that occurs between the wirings is most affected by the power supply wiring that supplies the operating voltage of the semiconductor chip 4 that has a large potential difference from the voltage applied to the signal wiring that occupies most of the wiring. is there. Therefore, by forming a power supply wiring (second wiring 103) on the back side of the first main surface on which the signal wiring (first wiring 102A) of the tape base material is formed, and moving the power supply wiring away from the signal wiring, Noise due to mutual inductance between the signal wiring and the power supply wiring is reduced.
[0010]
Further, even between the signal wirings provided on the first main surface of the wiring tape (TAB tape) 1, if the interval between adjacent wirings becomes narrow, a resonance phenomenon occurs and the signal waveform such as a clock pulse is disturbed. There is. Therefore, as shown in FIG. 13A, a ground potential layer (ground surface) 104 is provided on the second main surface of the wiring tape (TAB tape) in a region excluding the second wiring 103 and its periphery. Since an eddy current flows in the ground potential layer (ground surface) 104 in a direction that cancels the magnetic flux generated by the current flowing in the first wiring 102A, the self-inductance of the first wiring 102A and the mutual inductance between the wirings, Since dielectric crosstalk can be apparently reduced, it is effective when, for example, a high-frequency signal is applied to the first wiring (signal wiring) 102, and the reliability of the electrical signal and the signal transmission speed are improved. The speed can be increased.
[0011]
[Problems to be solved by the invention]
However, in the above-described conventional technique, a heat sink is provided on the second wiring 103 and the ground potential layer (ground surface) 104 of the wiring tape 1 via the insulator (adhesive) 2 using a two-metal wiring tape. Since a sheet-like adhesive is used when bonding 3, a void 11 is formed between the second wiring 103 and the ground potential layer 104 and air remains as shown in FIG. 13B. Therefore, air remaining in the void 11 is expanded by heat treatment during the manufacturing process or heat generated from the semiconductor chip 4 during use as a product, and the adhesive 2 around the second wiring 103 is peeled off. There was a problem.
[0012]
Further, since the plating layer 107 on the surface of the second wiring 103 and the ground potential layer 104 does not necessarily have good adhesion to the adhesive 2, the adhesive 2 peels off around the second wiring 103 and cracks occur. When this occurs, the crack progresses and finally the wiring tape 1 and the adhesive 2 are peeled off, resulting in a problem that the reliability of the apparatus is lowered.
[0013]
An object of the present invention is a T-BGA type semiconductor device in which a heat sink is bonded to a wiring tape in which wiring is formed on both surfaces of a tape base material via an adhesive, and occurs on the bonding surface of the wiring tape and the adhesive. The object is to provide a technique capable of reducing voids.
[0014]
Another object of the present invention is to provide a T-BGA type semiconductor device in which a heat radiating plate is bonded to a wiring tape having wirings formed on both sides of a tape base material via an adhesive material. An object of the present invention is to provide a technique capable of reducing the peeling at the substrate.
[0015]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The outline of the invention disclosed in the present invention will be described as follows.
[0017]
(1) A wiring tape on which a first wiring and its external connection terminal are formed is provided on a first main surface (front side surface) of an insulating tape-like base material having an opening at the center, and the first main surface of the wiring tape is provided. A heat sink is provided on the second main surface (back side surface) facing the surface (front side surface) with an insulator interposed therebetween, a semiconductor chip is provided in the opening of the wiring board, the external electrode of the semiconductor chip and the first electrode In a semiconductor device in which wiring is connected with a bonding wire, and the semiconductor chip, the bonding wire, and their connection portion are sealed with a resin, a second wiring is provided on the second main surface of the wiring tape, A ground potential layer (ground surface) is provided in a region excluding the periphery of the second wiring and the second wiring, and the second wiring, the ground potential layer, the first wiring, and its external connection terminals are provided at predetermined positions on the tape base material. Connect the conductive via Only the surrounding of the second wiring, a semiconductor device insulator for insulating between the second wiring and the ground potential layer is provided.
[0018]
According to the means of (1), in the T-BGA type semiconductor device using the two-metal structure wiring tape (TAB tape) in which wiring is formed on both the first main surface and the second main surface, By disposing an insulator around the second wiring of the wiring tape to insulate between the second wiring and the ground potential layer, heat is radiated to the second main surface of the wiring tape via an insulator (adhesive). It is possible to prevent a void from being formed between the second wiring and the ground potential layer when the plates are bonded. Therefore, it is possible to prevent the void from expanding due to heat treatment during the manufacturing process or heat generated from the semiconductor chip during use, and the second wiring and the first insulator are separated. In addition, since the peeling between the second wiring and the insulator (adhesive) can be reduced, the peeling at the bonding surface between the wiring tape and the first insulator can be reduced, and the reliability of the apparatus can be improved. it can.
[0019]
Further, in the two-metal structure wiring tape (TAB tape), it is necessary to perform plating in order to prevent oxidation of the copper surfaces of the second wiring 103 and the ground potential layer 104. The two-metal wiring tape forms a plating layer by performing nickel plating and gold plating on the surfaces of the first wiring and the external connection terminal. Therefore, when forming the plating layer, the second wiring and the ground potential are formed. By forming nickel plating and gold plating on the surface of the layer to form a plating layer, oxidation of the second wiring and the ground potential layer can be prevented at a low cost without increasing the number of manufacturing steps.
[0020]
Here, when a plating layer is formed on the second wiring and the ground potential layer and the surface thereof is gold-plated, the adhesiveness with the adhesive is generally lower than that of copper, By appropriately selecting the material used as the adhesive, the reliability can be sufficiently ensured.
[0021]
(2) a wiring tape forming step of forming a wiring tape in which the first wiring and its external connection terminal are formed on the first main surface (front side surface) of the insulating tape-like base material having an open center; A film-like insulator having an opening at a position overlapping with the opening of the tape base material is disposed on a second main surface (back side) facing the first main surface (front side) of the wiring tape. An insulator arranging step, a radiator plate disposed on a surface of the insulator facing the surface on which the wiring tape is arranged, a radiator plate adhering step of adhering the wiring tape and the radiator plate, and the radiator plate A semiconductor chip mounting step of mounting a semiconductor chip in the opening of the wiring tape, a wiring connection step of connecting an external electrode of the semiconductor chip and a wiring of the wiring tape by a bonding wire, and a semiconductor in the opening of the wiring substrate Chips, bondage In the method of manufacturing a semiconductor device comprising a sealing wire and a sealing step for sealing those connecting portions, the wiring tape forming step is electrically conductive on each of the first main surface and the second main surface of the tape base material. Forming a thin film, forming a via hole at a predetermined position of the tape base material from the second main surface side, forming a first plating layer on the conductive thin film and in the via hole, and on the second main surface; The conductive thin film is etched to form a second wiring and a ground potential layer (ground surface), an opening is formed at the center of the wiring tape, and the conductive thin film on the first main surface is etched. Forming a first wiring and an external connection terminal thereof; forming a wiring protective film on the first main surface so as to partially expose the first wiring and the external connection terminal; and And the exposed surface of the external connection terminal, the second wiring and the ground Second plating layer is formed on the position layer surface, the insulator liquid was cured by applying to the periphery of the second wiring, insulating the second wiring and the ground potential layer.
[0022]
According to the means (2), a two-metal structure wiring tape (TAB tape) in which wiring is formed on both surfaces of the first main surface and the second main surface is formed, and the two-metal structure wiring tape is formed. When manufacturing a T-BGA type semiconductor device using the first tape, the first wiring and the external connection terminal are formed on the first main surface of the wiring tape, and the second wiring and the ground are formed on the second main surface of the tape base material. After forming the potential layer (ground surface), a liquid insulator is applied around the second wiring of the wiring tape and cured to fill the space between the second wiring and the ground potential layer with the insulator. be able to. Therefore, since a void cannot be formed between the second wiring and the ground potential layer when a heat sink is bonded to the second wiring and the ground potential layer via an insulator (adhesive material) in the subsequent process, Peeling of the second wiring and the insulator (adhesive) due to expansion of voids during heat treatment during the process can be prevented.
[0023]
Further, when the plating process is partially performed on the first wiring and the external connection terminal, the second wiring and the grounding are also performed by simultaneously performing the plating process on the second wiring and the ground potential layer (ground surface). Oxidation of the potential layer can be prevented, and peeling of the adhesive can be prevented. In addition, since the plating process is performed at the same time, the number of manufacturing steps is not increased, and an increase in manufacturing cost can be suppressed.
[0024]
Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
[0025]
In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals, and repeated explanation thereof is omitted.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
(Example)
1 to 4 are schematic views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device, and FIG. 1B is a plan view of FIG. FIG. 2A is a schematic plan view seen from the first main surface side of the wiring tape, FIG. 2B is a back view of FIG. 2A, and FIG. 2 (b) is a partially enlarged view, FIG. 4 (a) is a cross-sectional view taken along line BB ′ of FIG. 3, and FIG. 4 (b) is a cross-sectional view taken along line CC ′ of FIG. In the cross-sectional view of FIG. 1B, parallel oblique lines (hatching) are omitted to make it easier to understand the configuration of the semiconductor device of this embodiment.
[0027]
1 to 4, 1 is a wiring tape, 1A is an opening, 101 is a tape-like substrate, 102A is a first wiring, 102B is an external connection terminal of the first wiring, 103 is a second wiring, and 104 is a ground potential. Layer (ground plane), 105 is a copper plating layer (first plating layer), 106 is a wiring protective film, 107 is a plating layer (second plating layer), 108 is an insulator, 2 is an insulator (adhesive), 3 Is a heat sink, 4 is a semiconductor chip, 401 is an external electrode, 5 is a bonding wire, 6 is a mold resin, 7 is a ball terminal, and 8 is an adhesive.
[0028]
As shown in FIGS. 1 and 2, the semiconductor device of the present embodiment has a first wiring 102A and its external connection on the first main surface (front side surface) of an insulating tape-like base material 101 whose center is opened. A wiring tape 1 on which terminals 102B are formed; and a heat radiating plate 3 provided with an insulator 2 interposed between a second main surface (back side surface) opposite to the first main surface (front side surface) of the wiring tape 1, A semiconductor chip 4 provided in the opening 1A of the wiring tape 1, a bonding wire 5 connecting the external electrode 401 of the semiconductor chip 4 and the first wiring 102A, the semiconductor chip 4, the bonding wire 5, and These connecting portions are sealed with a mold resin 6 and are a tape BGA (T-BGA) type semiconductor device in which ball terminals 7 are provided on the external connection terminals 102B.
[0029]
Further, the wiring tape (TAB tape) 1 used in the semiconductor device of the present embodiment is a TAB tape having a two-metal structure in which wiring is formed on both the first main surface and the second main surface of the wiring tape. As shown in FIGS. 3 and 4, a second wiring 103 is provided on the second main surface of the wiring tape 1, and a ground potential layer (2) is provided in a region excluding the periphery of the second wiring 103 and the second wiring 103. Ground plane) 104 is provided. The second wiring 103 and the ground potential layer 104 are provided with a copper plating layer (first plating layer) 105 on the surface as shown in FIG. The copper plating layer 105 is connected to the first wiring 102A and its external connection terminal 102B through a via hole provided at a predetermined position of the tape base material 101.
[0030]
Further, the portions other than the connection portions of the first wiring 102A and the external connection terminal 102B formed on the first main surface of the wiring tape 1 are, for example, a solder resist (SR) or a photo solder resist (PSR). It is protected by the wiring protective film 106.
[0031]
Further, for example, a plating layer (second plating layer) 107 in which a nickel plating layer and a gold plating layer are laminated is provided at the connection portion of the first wiring 102A and its external connection terminal 102B. The plating layer 107 is also formed on the surface of the copper plating layer 105 on the second wiring 103 and the ground potential layer (ground surface) 104. In addition, an insulator 108 that insulates between the second wiring 103 and the ground potential layer 104 is provided around the second wiring 103.
[0032]
The insulator (adhesive) 2 for bonding the wiring tape 1 and the heat sink 3 is made of, for example, a thermosetting epoxy resin.
[0033]
In addition, the heat radiating plate 3 efficiently radiates heat generated in the semiconductor chip 4 and also functions as a reinforcing material for the wiring tape 1. For example, a material such as copper (Cu) is used.
[0034]
In the T-BGA type semiconductor device of this embodiment, the periphery of the second wiring 103 of the wiring tape 1 is between the second wiring 103 and the ground potential layer 104 as shown in FIGS. An insulator 108 is provided for insulation. Therefore, when the heat sink 3 is bonded to the second wiring 103 and the ground potential layer 104 of the wiring tape 1 via the insulator (adhesive material) 2, the second wiring 103 and the ground potential layer 104 are connected. Since voids do not occur in the middle, for example, it is possible to prevent the voids from expanding due to heat generated from the semiconductor chip 4 during use and peeling of the bonding surface between the second wiring 103 and the insulator (adhesive) 2. Further, even when the adhesive force between the bonding surface of the second wiring 103 and the plating layer 107 on the ground potential layer (ground surface) 104 and the insulator (adhesive material) 2 is weak, peeling at the second wiring 103 portion is performed. The wiring tape 1 and the insulator 2 can be prevented from peeling due to the progress of cracks from the peeled portion.
[0035]
5 to 10 are schematic views in each manufacturing process for explaining the method of manufacturing the semiconductor device of this embodiment. 5B, 6, 8 </ b> B, and 9 </ b> B are cross-sectional views corresponding to the cross section taken along line BB ′ in FIG. 3.
[0036]
A method for manufacturing the semiconductor device according to the present embodiment will be described below with reference to FIGS. In addition, the manufacturing method of the wiring tape (TAB tape) 1 used by a present Example is literature "Norio Okabe, Yasuhiro Kameyama, Hiroki Tanaka, Katsutoshi Taga," 2 Metal Layer TBGA Tape for High Speed, High Pin Count LSI, for example. Since it is almost the same as the conventional method for manufacturing a wiring tape having a two-metal structure as described in "Packaging", HITACHI CABLE REVIEW, No. 16, (August 1997), 49-54 The detailed explanation is omitted.
[0037]
First, in order to manufacture a two-metal wiring tape (TAB tape) used in the semiconductor device of this embodiment, as shown in FIGS. 5A and 5B, for example, polyimide. A tape 9 with a copper foil in which conductive thin films 109A and 109B such as a copper foil are formed on both surfaces of an insulating tape base material is prepared. The tape with copper foil is formed by, for example, rolling copper foil pasted on both sides of the tape base material 101 with an adhesive, or, for example, by depositing copper on the tape base material 101 by sputtering or the like to form a thin film. Is obtained. The tape 9 with copper foil is in the form of an elongated tape, and a plurality of wiring tape forming regions 1 ′ as shown in FIG. 5A are continuously provided.
[0038]
Next, as shown in FIG. 6A, at a predetermined position of the tape 9 with copper foil, for example, by a carbon dioxide laser, one main surface (second main surface) to the other main surface (first main surface). After forming the via hole 10 reaching the conductive thin film on the surface), as shown in FIG. 6B, copper (Cu) is used as the first plating layer on the entire second main surface and on the side surface of the via hole 10. A plating layer 105 is formed. The copper plating is formed by, for example, an electrolytic plating method or a method combining an electroless plating method and an electrolytic plating method.
[0039]
Next, the second main surface side of the tape 9 with copper foil, in other words, the surface where the via hole 10 is opened is etched, and as shown in FIG. 6C, the second wiring 103 and the second wiring A ground potential layer (ground surface) 104 excluding a region around 103 is formed. The second wiring 103 and the ground potential layer 104 are formed, for example, in a pattern as shown in FIG.
[0040]
Next, an opening 1A is formed in the central portion of the wiring board formation region 1 ′ with, for example, a carbon dioxide laser as shown in FIG. 7A, and then the conductive thin film 109A is etched. As shown in FIGS. 7A and 7B, the first wiring 102A and its external connection terminal 102B are formed. Although not shown in part in FIG. 7A, each external connection terminal 102B is routed around the opening 1A directly with the first wiring 102A or via the second wiring. .
[0041]
Next, as shown in FIG. 8A, in order to protect the first wiring 102A and its external connection terminal 102B from contaminants and scratches from the outside, for example, wiring such as solder resist or photo solder resist. A protective film 106 is formed.
[0042]
Next, by using an electrolytic plating method, an electroless plating method, or an electroplating method, as shown in FIG. 8B, the wire bonding property of the first wiring 102A and the solder connection property of the external connection terminal 102B are improved. A plating layer (second plating layer) 107 for improving the quality is formed. At the same time, a plating layer 107 is formed on the surfaces of the second wiring 103 on the second main surface and the copper plating layer 105 on the ground potential layer 104 in order to prevent oxidation. The plating layer 107 is formed, for example, by laminating a nickel (Ni) plating layer and a gold (Au) plating layer.
[0043]
Next, as shown in FIGS. 9A and 9B, when a liquid insulator 108 such as a solder resist (SR) is applied and cured around the second wiring 103, for example. A two-metal wiring tape (TAB tape) 1 used in the T-BGA type semiconductor device of this embodiment is formed.
[0044]
Next, as shown in FIGS. 10A and 10B, the opening 1 </ b> A of the wiring tape 1 is planarly overlapped on the second wiring 103 and the ground potential layer 104 of the wiring tape 1. A film-like insulator (adhesive) 2 having an opening at a position is disposed, and a heat radiating plate 3 is disposed on a surface of the insulator 2 opposite to the surface on which the wiring tape 1 is disposed. 1 and the heat sink 3 are bonded together. At this time, since, for example, a thermosetting epoxy resin or the like is used as the insulator (adhesive) 2, heat treatment is performed to bond the wiring tape 1 and the heat radiating plate 3. There is no void between the first second wiring 103 and the ground potential layer (ground surface) 104 because it is filled with the insulator 108, and the second wiring 103 and the insulator (adhesive) due to expansion of the void during heating. 2 peeling can be prevented. Further, at this time, the insulator (adhesive) 2 is prepared by appropriately adjusting the amounts of the main material and additive in order to improve the adhesion between the second wiring 103 and the surface of the ground potential layer 104 with gold plating. The predetermined adhesion reliability can be obtained.
[0045]
Next, as shown in FIGS. 11A and 11B, the semiconductor chip 4 is mounted in the opening 1A of the wiring tape of the heat radiating plate 3, and the external electrodes 401 of the semiconductor chip 4 are connected. The first wiring 102 </ b> A of the wiring tape 1 is connected by the bonding wire 5.
[0046]
Then, after sealing the semiconductor chip 4, the bonding wires 5 and their connecting portions in the opening 1A of the wiring tape 1 with the molding resin 6, the ball terminals 7 are connected to the external connection terminals 102B. The T-BGA type semiconductor device of this embodiment as shown in FIG. 4 can be obtained. Also at this time, when the ball terminal 7 is connected, the ball terminal 7 is partially melted by heating, but there is no void between the second wiring 103 and the ground potential layer 104. The second wiring 103 and the insulator (adhesive material) 2 can be prevented from peeling off.
[0047]
As described above, in the semiconductor device of this embodiment, the liquid insulator 105 is provided around the second wiring 103 formed on the surface of the wiring tape (TAB tape) 1 to which the heat sink 3 is bonded. The second wiring 103 and the ground potential are filled by applying and curing, and filling the space between the second wiring 103 and the ground potential layer (ground surface) 104 provided around the second wiring 103 with the insulator 105. When the sheet-like insulator (adhesive material) 2 is bonded onto the layer 104, voids can be prevented from forming around the second wiring 103. For this reason, it is possible to prevent the air remaining in the void from expanding due to the heat treatment during the manufacturing process and peeling off the bonding surface of the second wiring 103 and the insulator (adhesive) 2. Moreover, since peeling at the bonding surface between the second wiring 103 and the insulator (adhesive material) 2 can be prevented, occurrence of cracks within the bonding surface between the wiring tape 1 and the insulator 2 can be reduced. Defects in the semiconductor device due to peeling of the wiring tape 1 and the insulator 2 can be reduced.
[0048]
Further, when the plating layer is formed on the first wiring 102A and the external connection terminal 102B, the same plating layer 107 is also formed on the surfaces of the second wiring 103 and the ground potential layer 104. Since the second wiring 103 and the ground potential layer 104 can be prevented from being oxidized, the second wiring 103 and the ground potential layer 104 can be prevented from being peeled off from the bonding surface with the adhesive 2, thereby preventing a semiconductor device from being defective. it can.
[0049]
The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. .
[0050]
【The invention's effect】
The effects obtained by typical ones of the inventions disclosed in the present invention will be briefly described as follows.
[0051]
(1) In a T-BGA type semiconductor device in which a heat sink is bonded to a wiring tape in which wiring is formed on both surfaces of the tape base material via an adhesive, voids are generated on the bonding surface of the wiring tape and the adhesive. Can be prevented.
[0052]
(2) In a T-BGA type semiconductor device in which a heat sink is bonded to a wiring tape in which wiring is formed on both surfaces of the tape base material via an adhesive, peeling at the bonding surface of the wiring tape and the adhesive is reduced. can do.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a schematic configuration of a wiring tape used in the semiconductor device of Example 1;
FIG. 3 is a partially enlarged view of FIG.
4 is a schematic cross-sectional view taken along line BB ′ in FIG. 3 and a schematic cross-sectional view taken along line CC ′ in FIG. 3;
FIG. 5 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 6 is a schematic view for explaining the method for manufacturing a semiconductor device according to the present embodiment.
FIG. 7 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 8 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 9 is a schematic view for explaining the method for manufacturing the semiconductor device of the present example.
FIG. 10 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 11 is a schematic view for explaining the method for manufacturing the semiconductor device according to the embodiment.
FIG. 12 is a schematic diagram showing a schematic configuration of a conventional T-BGA type semiconductor device.
FIG. 13 is a schematic diagram showing a schematic configuration of a conventional T-BGA type semiconductor device.
[Explanation of symbols]
1 Wiring tape (TAB tape)
1A opening
101 Tape-shaped substrate
102A first wiring
102B External connection terminal
103 Second wiring
104 Ground potential layer
105 Copper plating layer (first plating layer)
106 Wiring protection film
107 Plating layer (second plating layer)
108 Insulator
109A, 109B copper foil
2 Insulator (adhesive)
3 Heat sink
4 Semiconductor chip
401 External electrode
5 Bonding wire
6 Mold resin
7 Ball terminal
8 Adhesive
9 Tape with copper foil
10 Via hole
11 void

Claims

A wiring tape on which the first wiring and its external connection terminals are formed is provided on the first main surface (front side) of the insulating tape-like base material having an open center, and the first main surface (front surface) of the wiring tape is provided. A heat sink is provided on the second main surface (back side surface) opposite to the side surface, an insulator is provided, a semiconductor chip is provided in the opening of the wiring board, and the external electrode of the semiconductor chip and the first wiring are connected to each other. In the semiconductor device formed by connecting with a bonding wire and sealing the semiconductor chip, the bonding wire, and their connecting portion with resin, a second wiring is provided on the second main surface of the wiring tape, and the second wiring A ground potential layer (ground surface) is provided in a region excluding the periphery of the second wiring, and the second wiring and ground potential layer are connected to the first wiring and its external connection terminals at predetermined positions on the tape base material. Conductive vias are provided,
A semiconductor device, wherein an insulator for insulating between the second wiring and the ground potential layer is provided around the second wiring.

The semiconductor device according to claim 1,
A semiconductor device, wherein a gold (Au) plating layer is provided on a surface of the second wiring and the ground potential layer.

A wiring tape forming step of forming a wiring tape in which a first wiring and its external connection terminal are formed on a first main surface (front side surface) of an insulating tape-like base material having an open center;
A film-like insulator having an opening at a position overlapping the opening of the tape base material on the second main surface (back side) facing the first main surface (front side) of the wiring tape is disposed. An insulator placement step,
A radiator plate is disposed on a surface of the insulator facing the surface on which the wiring tape is disposed, and a radiator plate bonding step for bonding the wiring tape and the radiator plate;
A semiconductor chip mounting step of mounting a semiconductor chip in the opening of the wiring tape of the heat sink;
A wiring connection step of connecting the external electrode of the semiconductor chip and the wiring tape by a bonding wire;
In a manufacturing method of a semiconductor device comprising: a semiconductor chip in an opening of the wiring board, a bonding wire, and a sealing step for sealing those connecting portions.
The wiring tape forming step includes
Forming a conductive thin film on each of the first main surface and the second main surface of the tape substrate;
Forming a via hole from the second main surface side at a predetermined position of the tape base material;
Forming a first plating layer on the conductive thin film and in the via hole;
Etching the conductive thin film on the second main surface to form a second wiring and a ground potential layer (ground surface);
Forming an opening in the center of the wiring tape;
Etching the conductive thin film on the first main surface to form a first wiring and its external connection terminal;
Forming a wiring protective film on the first main surface so that the first wiring and its external connection terminal are partially exposed;
Forming a second plating layer on the exposed surface of the first wiring and its external connection terminal, the second wiring and the ground potential layer surface;
A method of manufacturing a semiconductor device, wherein a liquid insulator is applied and cured around the second wiring to insulate the second wiring from a ground potential layer.