JP4023332B2 - Recording / playback device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a recording / reproducing apparatus capable of reading out and reproducing music data stored in a recording medium such as a hard disk apparatus or recording an audio signal input from the outside on a recording medium.
[0002]
[Prior art]
Conventionally, music data (song data) can be read from a recording medium such as a hard disk drive (HDD) and played back in multiple rooms, or audio signals input from the outside can be captured and recorded on the recording medium. A recording / reproducing apparatus having a plurality of channels is known.
FIG. 9 is a block diagram showing a configuration example of this type of recording / reproducing apparatus.
In this figure, 1 is a control unit (CPU) that controls the entire recording / reproducing apparatus, 2 is a memory that includes a ROM that stores a control program and the like, and a RAM that is used as a work area and a buffer area. , 91, etc., a bus arbiter (bus arbiter) that arbitrates use requests of the data bus 10, 4 is an ATAPI (AT Attachment Packet Interface) interface circuit that connects the hard disk device 5, and 5 is music data (music) Data) is stored in the hard disk device.
Reference numerals 6 to 9 denote audio output units corresponding to the respective channels for outputting the reproduction signals of the music data stored in the recording / reproducing apparatus to a plurality of rooms (room 1 to room n). Each of the audio output units 6 to 9 has the same components, and DMA controllers (DMAC: Direct Memory Access Controllers) 61, 71, 81, 91, FIFO control units connected to the data bus 10 62, 72, 82, 92, first-in first-out (FIFO) buffer (hereinafter simply referred to as "FIFO") 63, 73, 83, 93, DAC interface circuits 64, 74, 84, 94 and DAC (digital) Analog converter) 65, 75, 85, 95.
An audio input unit 11 includes an analog-to-digital converter (ADC) 111, an ADC interface circuit 112, a recording FIFO buffer 113, a recording FIFO control unit 114, and a recording DMAC 115, 10 includes the CPU 1, the memory 2, This is a data bus for transferring data among the ATAPI interface circuit 4, the audio output units 6 to 9, the audio input unit 11, and the like.
Although not shown, an input device for inputting operation instructions and a display device for displaying status information are naturally provided. Further, a CD-R / RW drive device, a DVD drive device, and the like are provided. It may be provided.
[0003]
In the recording / reproducing apparatus configured as described above, when reproducing the music data stored in the HDD 5, first, the CPU 1 reads the music data to be reproduced from the HDD 5 via the ATAPI interface circuit 4, A predetermined amount is written (buffered) in the buffer area of the memory 2.
FIG. 10 is a diagram showing a memory map of the buffer area set in the memory 2. In the example shown in this figure, the buffer area is set corresponding to each room (room 1 to room n) to which the reproduced audio signal is supplied. The amount of data buffered in each buffer area (the amount of data written in each buffer area) is the capacity of the FIFOs 63,..., 93 in consideration of the access time of the HDD 5 and the transfer time of the DMAC to other rooms. It is necessary to keep it large enough compared to.
[0004]
When a predetermined amount of data is buffered in the buffer area, the CPU 1 causes each DMAC to transfer data from the buffer area of the memory 2 to the FIFOs 63,..., 93 in the audio output units 6 to 9 corresponding to the rooms. Therefore, DMAC setting (DMA transfer processing) is performed.
FIG. 11 is a flowchart showing the flow of this DMA transfer process.
That is, the CPU 1 sets, for each DMAC, the start address and the number of transfer bytes in the memory 2 of the music data to be transferred in the current DMA transfer process (steps S51 and S52), and activates the DMAC in step S53. That is, the DMAC is set in an operable state. As a result, the DMAC can immediately transfer data when the bus use permission is acquired from the bus arbiter 3. The CPU 1 waits for the transfer of data by the DMAC to be completed and for a DMAC transfer end interrupt to occur (step S54).
For example, when reproducing in room 1, first, the head address is set to A in FIG. 10 (S51), and the number of transfer bytes is set to (B-A) (S52). Then, the DMAC is activated (S53) and waits for the end of the DMA transfer (S54). In the next DMA transfer process, the head address is set to point B and the transfer byte count is set to (C−B). As will be described later, it is convenient to keep the number of transfer bytes in one DMA transfer process constant.
[0005]
The FIFO controllers 62, 72,..., 92 generate a transfer request signal (REQn) when the data amount (FIFO remaining amount) stored in the corresponding buffers 63,. Is set.
FIG. 12 is a diagram showing FIFOs 63, 73,..., 93. As shown in the figure, it is detected that the remaining storage capacity of the FIFO is equal to or less than a predetermined value TH, and the corresponding FIFO control unit sends a transfer request signal. (REQn) is generated and output to the bus arbiter 3.
When the bus arbiter 3 receives the transfer request signal (REQn), that is, when the transfer request signal (ACKn) is ready to start transfer to the FIFO in which the transfer request has been generated, the bus request signal (REQn) Is returned to the generated FIFO control unit and the corresponding DMAC.
As a result, since the DMA transfer is started and the data that flows on the data bus 10 after the transfer request acceptance signal (ACKn) is returned is the data for the FIFO that generated the transfer request signal (REQn), the transfer request acceptance signal The FIFO control unit that has received (ACKn) latches the data and writes the data to the FIFO.
Here, it is convenient to set the number of transfer bytes by one DMA transfer to (full-TH) in FIG.
There are various arbitration methods in the bus arbiter 3, such as a method of fixing the priority order and a method of sequentially changing the priority order. In the case of this example, the latter is appropriate.
[0006]
The DAC interface circuits 64, 74, 84, 94 read music data from the corresponding FIFOs 63,..., 93 at a predetermined sampling period (for example, 44.1 kHz), and perform parallel-serial conversion (PS conversion) according to the DAC input format. ) Is output to the DACs 65, 75, 85, and 95, and the music data is reproduced from the DACs 65,.
[0007]
As described above, in the conventional recording / reproducing apparatus, the DMAC and the FIFO control unit are required for each audio output unit of each channel having the FIFO, the DAC interface circuit, and the DAC, and many components are required. .
In addition, since it is necessary to process transfer request signals (REQn) from many FIFO control units, the configuration and processing of the bus arbiter 3 is also complicated.
[0008]
In order to solve such problems, there has also been proposed an apparatus that reduces the number of DMACs used (see Patent Document 1).
According to the method proposed in Patent Document 1, the number of DMACs used can be reduced. However, when the remaining amount of FIFO used falls below a certain amount, the CPU is interrupted, and DMAC transfer processing is performed at that time. Therefore, there is a problem that a time lag occurs between the time when the FIFO control unit issues a transfer request and the time when data transfer is actually started.
[0009]
[Patent Document 1]
JP 09-069071 A
[0010]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide a recording / reproducing apparatus that reduces the number of DMACs used in a recording / reproducing apparatus having a plurality of channels and does not require a complicated configuration or complicated processing.
[0011]
[Means for Solving the Problems]
  In order to achieve the above object, a recording / reproducing apparatus of the present invention is a recording / reproducing apparatus having a plurality of reproduction channels,A control unit;Provided corresponding to each of the plurality of playback channels,Each otherData to be transferred to a plurality of FIFO buffers to be read synchronously and a FIFO buffer corresponding to a reproduction channel from which data is reproduced among the plurality of reproduction channels., One by one for each playback channel on which playback is performedA memory for storing, a DMA controller, and a FIFO controller for controlling the plurality of FIFO buffers;The controller is operable to determine the number of reproduction channels on which data is reproduced and set the data transfer amount corresponding to the number of reproduction channels on which data is reproduced to the DMA controller to operate the DMA controller. The process to set to the state is executed,The DMA controllerIn response to a DMA transfer request from the FIFO controller,Previously from the memory in one DMA transferDePlayback channel on which data is playedThe predetermined amount for eachDataRead sequentially to data busThe FIFO controller is configured to request a DMA transfer by the DMA controller when the amount of data stored in the FIFO buffer is lower than a predetermined value, and from the memory by the DMA controller.Sequentially read to the data busPlayback channel where data is played backThe predetermined amount for eachDataSequentiallyEach of them writes data to the corresponding FIFO buffer.
  Another recording / reproducing apparatus of the present invention is a recording / reproducing apparatus having a plurality of reproduction channels,A control unit;Provided corresponding to each of the plurality of playback channels,Each otherA plurality of FIFO buffers to be read synchronously and data to be transferred to the plurality of FIFO buffersSequentially a predetermined amount for each playback channelA memory to store,The data to be reproduced is stored in the FIFO buffer corresponding to the reproduction channel on which the data of the plurality of reproduction channels is reproduced,Playback of data among the plurality of playback channelsButDoneThisFIFO buffer corresponding to no playback channelOn the other handA memory for storing null data, a DMA controller, and a FIFO controller for controlling the plurality of FIFO buffers;The control unit sets a data transfer amount corresponding to the number of the plurality of reproduction channels in the DMA controller regardless of the number of the reproduction channels in which data is reproduced from among the plurality of reproduction channels. The process to set the controller to an operable state is executed.The DMA controllerIn response to a DMA transfer request from the FIFO controller,In a single DMA transfer, the memoryThe predetermined amount for each playback channelDataRead sequentially to data busThe FIFO control unit is configured to request a DMA transfer by the DMA controller when the amount of data stored in the FIFO buffer falls below a predetermined value, and from the memory by the DMA controller.Sequentially read to the data busThe plurality ofThe predetermined amount for each playback channelDataSequentiallyEach of them writes data to the corresponding FIFO buffer.
  Furthermore, still another recording / reproducing apparatus of the present invention is a recording / reproducing apparatus having a plurality of recording channels,A control unit;Provided corresponding to each of the plurality of recording channels,Each otherA plurality of FIFO buffers to be written synchronously and data transferred from a FIFO buffer corresponding to a recording channel for recording data among the plurality of recording channels., One by one for each recording channel on which recording is performedA memory for storing, a DMA controller, and a FIFO controller for controlling the plurality of FIFO buffers;The controller is operable to determine the number of recording channels on which data is recorded and to set the data transfer amount corresponding to the number of recording channels on which data is recorded in the DMA controller to operate the DMA controller. The process to set to the state is executed,The DMA controllerIn response to a DMA transfer request from the FIFO controller,With one DMA transfer,By the FIFO control unitFIFO buffer corresponding to a recording channel on which data is recorded among the plurality of recording channels.Sequentially read to the data bus by a predetermined amount IssuedData to the memoryWrite sequentiallyThe FIFO control unit performs processing for requesting a DMA transfer by the DMA controller when the amount of data stored in the FIFO buffer reaches a predetermined value, and a FIFO corresponding to a recording channel on which the data is recorded. The data stored in the bufferSequentially to the data bus by a predetermined amountIt is supposed to perform a reading process.
  Still another recording / reproducing apparatus of the present invention is a recording / reproducing apparatus having a plurality of recording channels,A control unit;Provided corresponding to each of the plurality of recording channels,Each otherA plurality of FIFO buffers to be written synchronously and data transferred from the plurality of FIFO buffersSequential amounts for each recording channelA memory for storing, a DMA controller, and a FIFO controller for controlling the plurality of FIFO buffers;The controller sets a data transfer amount corresponding to the number of the plurality of recording channels in the DMA controller regardless of the number of recording channels in which the data is recorded among the plurality of recording channels. It performs processing to set the controller to an operable state,The DMA controllerIn response to a DMA transfer request from the FIFO controller,With one DMA transfer,By the FIFO control unitThe plurality of FIFO buffersAre sequentially read out to the data bus by a predetermined amount.Data to the memoryWrite sequentiallyThe FIFO controller is configured to request a DMA transfer by the DMA controller when the amount of data stored in the FIFO buffer reaches a predetermined value, and to store data stored in the plurality of FIFO buffers.TheRegardless of whether the FIFO buffer is a FIFO buffer corresponding to a recording channel on which data is recorded,Sequentially to the data bus by a predetermined amountIt is supposed to perform a reading process.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a configuration of an embodiment of a recording / reproducing apparatus of the present invention. In this figure, the same components as those in FIG. 9 are given the same reference numerals to avoid duplication of explanation.
As is apparent from a comparison between FIG. 1 and FIG. 9, in the recording / reproducing apparatus of the present invention shown in FIG. 1, some of the audio output units 6, 7,. In this example, only the audio output unit 6 is provided with the DMAC 61 and the FIFO control unit 62, and the other audio output units (7, 8, 9) are respectively a FIFO (73,..., 93) and a DAC interface. Only the circuits (74,..., 94) and the DACs (75,..., 95) are provided, and the FIFOs (73,. It is made to be done.
Here, the speed at which data is written from the DMAC 61 to the FIFOs 63, 73,..., 93 is sufficiently higher than the speed at which data is read from the FIFOs 63, 73,. It is assumed that DAC1 (65) to DACn (95) operate with the same clock (word clock and bit clock).
Further, the storage capacity of each FIFO is assumed to be equal, and each DAC interface circuit 64,... Start playback. Here, the read strobe signals (RD1 to RDn) are synchronized because the DAC1 to DACn operate with the same clock. The FIFO control unit 62 continues to issue a transfer request signal (REQ1) until the DMAC 61 is activated once and transfer is performed and the remaining FIFO exceeds the threshold value (TH). Here, the threshold value of the FIFO remaining amount is set to ½ of the FIFO storage capacity.
In this embodiment, the case where there is one audio output unit (audio output unit 6) provided with the DMAC and FIFO control unit is shown. However, a plurality of audio output units include a DMAC and a FIFO control unit. And a plurality of audio output units may share and control audio output units that are not provided with DMAC and FIFO control units.
[0013]
Regarding the operation of the first embodiment of the recording / reproducing apparatus of the present invention configured as described above, the total number of rooms for outputting audio signals is three (room 1, room 2, and room 3), and reproduction channels. A case where the number is 3 channels will be described as an example.
FIG. 2 is a time chart for explaining an example of the operation in the first embodiment of the recording / reproducing apparatus of the present invention.
In this figure, it is assumed that a music data reproduction request to room 1 occurs at time T1. In response to the reproduction request, the CPU 1 sets the FIFO control unit 62 to enable (operate) the FIFO of the audio output unit corresponding to the room (in this case, the FIFO 63 of the audio output unit 6). To do. Then, the requested music data is read from the HDD 5 and transferred to the buffer area of the memory 2.
[0014]
FIG. 3 is a diagram illustrating a state in which music data distributed to the rooms 1 to 3 is stored in the HDD 5. As shown in this figure, the HDD 5 stores a plurality of song data, and the song data distributed to the room 1 is R1 data 0, R1 data 1, R1 data 2,. Is composed of a plurality of blocks such as R2 data 0, R2 data 1,..., And room 3 music data R3 data 0, R3 data 1,. Here, the block size (address E-address D) is, for example, ½ of the storage capacity of the FIFO (63, 73,..., 93), and data transfer is performed in units of blocks.
[0015]
The CPU 1 sequentially transfers the music data R1 data 0, R1 data 1,... Of the room 1 to the buffer area of the memory 2.
FIG. 4 is a diagram showing how music data is stored in the buffer area set in the memory 2.
As shown in the figure, music data R1 data 0, R1 data 1,... Are accumulated (buffered) in order from the address F of the memory 2 from the HDD 5 by the transfer process by the CPU 1.
When a predetermined amount of music data is buffered in the memory 2, the CPU 1 starts the DMA transfer process shown in FIG. The amount of data to be buffered is sufficiently large compared to the FIFO capacity.
[0016]
When the DMA transfer process shown in FIG. 5 is started, first, in step S11, the number of rooms in which music data is currently being reproduced is checked. As a result, in the case of reproducing only one room, the number of bytes corresponding to the one block is set in the DMAC 61 as the number of transfer bytes, and in the case of two-room reproduction, two blocks are set as the number of transfer bytes. In the case of reproduction, 3 blocks are set as the transfer byte number (steps S12 to S16). Next, the transfer start address is set (step S17), and in step S18, the DMAC 61 is activated (set to an operable state).
As described above, the FIFO control unit 62 determines that the data accumulation amount (remaining FIFO amount) in any of the FIFOs 63, 73,..., 93 managed by the FIFO control unit 62 is the threshold value (the FIFO storage capacity). When the value does not exceed (below) 1/2), the transfer request signal (REQ1) is output to the bus arbiter 3.
Therefore, when the playback request for room 1 is made for the first time at time T1 as described above, the amount of music data stored in any of the FIFOs 63 to 93 does not exceed 1/2 of the storage capacity. The unit 62 outputs a transfer request signal (REQ1). When the right to use the bus 10 is acquired and the transfer request acceptance signal (ACK1) is returned from the bus arbiter 3, the DMAC 61 sets the head address set in step S17 of the memory 2 (specifically, F in FIG. 4). ) From the number of transfer bytes (= G−F) set in step S13. The FIFO controller 62 outputs a write enable signal WE1, and writes the music data read out on the data bus 10 into the FIFO 63 (time T2 in FIG. 2). By this DMA transfer, as shown in FIG. 2, the data accumulation amount (remaining amount) of FIFO1 (63) becomes TH which is ½ of the storage capacity.
[0017]
When the DMA transfer ends, a transfer end interrupt is generated from the DMAC 61 to the CPU 1 (step S19 in FIG. 5). Since the reproduction in all the rooms is not completed (step S20), the CPU 1 returns to step S11, repeats the DMA transfer process, sets G as the start address of the next DMA transfer, and sets the number of transfer blocks. Set one block.
[0018]
As described above, since the amount of data stored in the FIFO 63 after the first DMA transfer ends is equal to TH (= 1/2 of the storage capacity) and does not exceed TH, the FIFO controller 62 further Continue to output the transfer request signal (REQ1).
Therefore, the second DMA transfer is performed in the same manner as described above (time T3 in FIG. 2). As a result, the music piece data “R1 data 1” in FIG. 4 is transferred to the FIFO 63, and the music piece data is accumulated up to the storage capacity of the FIFO1 (63).
When the FIFO control unit 63 detects that the amount of music data stored in the FIFO 1 (63) is full, the FIFO control unit 63 notifies the corresponding DAC interface circuit 64, and the DAC interface circuit 64 reads a read strobe signal (RD signal) with a predetermined period. 2 is started (time T4 in FIG. 2), and the RD signal is output to the FIFO 63. Thereby, the music data is read out from the FIFO 63 at a predetermined cycle and supplied to the DAC 65, and an analog audio output signal is output from the DAC 65. It will be supplied to the room 1. Thereby, the reproduction | regeneration of the music in the room 1 was started.
Thereafter, the music data is read from the FIFO 63 by the RD signal. When the data amount (remaining amount) stored in the FIFO 63 becomes equal to or less than the TH, as described above, the FIFO control unit 62 generates a transfer request signal (REQ1) and performs DMA transfer. Hereinafter, by repeating this, the music data is reproduced.
On the other hand, when the CPU 1 monitors the amount of music data stored in the buffer area of the memory 2 and detects that the music data is below a predetermined amount, the CPU 1 reads the subsequent music data from the HDD 5 as described above. Transfer to the buffer area of the memory 2. By repeating the above processing, music data is distributed to the room 1.
[0019]
Now, it is assumed that a reproduction request for room 2 is generated at time T5 (FIG. 2). In response to the reproduction request, the CPU 1 sets the corresponding FIFO 2 (73) to be enabled for the FIFO control unit 62. Then, transfer of the music data of the music to be reproduced in the room 2 from the HDD 5 to the buffer area of the memory 2 is started. That is, from this time point, both the song data in room 1 and the song data in room 2 (a total of two blocks of data) are transferred from the HDD 5 to the buffer area of the memory 2. Thereby, the music data (R1 data m + 1) to the room 1 and the first block (R2 data 0) of the music data to the room 2 are transferred to the area after the address H in the memory 2 by one transfer process. The Rukoto. Then, this address H is stored.
[0020]
Hereinafter, when the reproduction of the music for room 1 proceeds as described above and the start address of the next transfer becomes H, the number of reproduction rooms is set to 2 in step S11 of the DMA transfer process. Two blocks are set as the number of transfer bytes in the DMAC 61 (step S15), and H (FIG. 4) is set as the head address (step S17).
Then, the remaining amount of music data stored in the FIFO 1 (63) becomes 1/2 (TH) or less of the storage capacity, and a transfer request signal (REQ1) is generated by the FIFO control unit 62. When the transfer request acceptance signal (ACK1) is returned, the transfer processing by the DMAC 61 is started as described above. That is, the DMAC 61 reads data for two blocks (number of transfer bytes) from the address H (start address) of the memory 2. The FIFO controller 62 generates a write enable signal WE1 for the data of the first block of music data read out on the data bus 10, accumulates it in the FIFO 63 (time T6), For the data for the block, the write enable signal WE2 is generated and stored in the FIFO 73 (time T7).
As a result, as shown in FIG. 2, the music piece data R1 is stored in the FIFO1 (63) up to the full capacity, and the music piece data R2 is stored in the FIFO2 (73) up to 1/2 (TH) of the storage capacity.
Therefore, at this time point, the music data stored in the FIFO 1 (63) is read and reproduced by the RD signal from the DAC interface circuit 64, but the music data stored in the FIFO 2 (73) is reproduced by the DAC interface circuit. Since the instruction to drive 74 is not supplied from the FIFO controller 62, it is not read out.
[0021]
In this way, when the reproduction of the song data 1 proceeds and the amount (remaining amount) of the song data stored in the FIFO 1 (63) becomes equal to or less than TH, the transfer request signal is sent from the FIFO control unit 61 as described above. (REQ1) is generated and DMA transfer is performed. The leading address of this DMA transfer is I. By this DMA transfer, as shown in FIG. 2, the music data of FIFO 2 (73) is also accumulated to the full storage capacity. Accordingly, the FIFO control unit 62 supplies an instruction signal for starting generation of the RD signal (RD2) to the DAC interface circuit 74 as well as to the DAC interface circuit 64. Thus, the music data is read from the FIFO 2 (73) at a predetermined cycle (sampling cycle) by the RD2 signal, converted into an analog signal by the DAC 75, and an audio signal is output to the room 2 (time). T10). In this way, reproduction in the room 2 is started.
[0022]
Then, it is assumed that a reproduction request for the room 3 is generated at time T11. As described above, the CPU 1 sets the corresponding FIFO 3 (83) to be enabled for the FIFO control unit 62 in response to the reproduction request. Then, the music data R3 of the music to be reproduced in the room 3 is transferred from the HDD 5 to the buffer area of the memory 2. That is, from this time point, the song data R1 of the room 1, the song data R2 of the room 2, and the song data R3 of the room 3 are transferred from the HDD 5 to the buffer area of the memory 2 one block at a time in one transfer process. To.
As a result, as shown in FIG. 4, after the address J of the memory 2, each piece of music data R1 to R3 is stored for one block.
Hereinafter, when the reproduction of the room 1 and the room 2 proceeds in the same manner as described above and the next top address becomes J, the number of reproduction rooms is 3 (step S11) and the number of transfer bytes is the DMA transfer process. The head address is set to J (step S17) for three blocks (step S16).
[0023]
When the remaining memory capacity of the FIFO1 (63) and FIFO2 (73) becomes less than TH, a transfer request signal (REQ1) is generated from the FIFO controller 62, and the DMAC 61 generates three blocks from the address J of the memory 2. Music data (“R1 data n + 1”, “R2 data p + 1”, “R3 data 0”) is read onto the data bus 10, and the FIFO controller 62 receives the first one block of music data as a write enable signal. WE1 transfers to FIFO1 (63) (time T12), the next one block of music data is transferred to WE2 to FIFO2 (73) (T13), and the last one block of music data is transferred to FIFO3 (83). (T14). As a result, the song data is accumulated in the FIFO3 (83) up to TH.
Then, by the next DMA transfer started from time T15, the music piece data is stored in FIFO3 (83) to the full (T17). As a result, the FIFO control unit 62 supplies an instruction signal for starting generation of the RD signal (RD3) to the DAC interface circuit 84, and the delivery of the audio signal to the room 3 is started in the same manner as described above (T18). ).
As described above, music data can be distributed to a plurality of rooms using a single DMAC 61.
[0024]
Next, a description will be given of a second embodiment of the recording / reproducing apparatus of the present invention in which hardware design and software processing are simplified. This embodiment simplifies hardware design and software processing by making the data transfer amount of one DMA transfer constant (for example, for three blocks).
FIG. 6 is a timing chart showing an example of the operation in the second embodiment of the present invention, FIG. 7 is a diagram showing an example of a memory map of the buffer area of the memory 2 in this embodiment, and FIG. It is a flowchart which shows the DMA transfer process in this embodiment. Here, as described above, the description will be made assuming that the total number of rooms is 3 (the number of playback channels is 3). However, the present invention can be similarly applied to a case where a plurality of playback channels are provided.
As shown in the memory map of FIG. 7, in this embodiment, data for all the rooms (in this example, for three rooms) is transferred as a unit regardless of the number of rooms in which the song data is actually reproduced. I have to. That is, even when only room 1 is reproduced, data for three blocks is always buffered, and a portion corresponding to a room where reproduction is not performed is filled with null data. Further, when reproduction is performed in room 1 and room 2, the third block corresponding to room 3 is filled with null data.
[0025]
FIG. 8 is a flowchart showing the flow of the DMA transfer process. In this embodiment, at the time of reproduction, regarding the activation of the DMAC 61, it is sufficient to always execute the same process regardless of the number of reproduction rooms. That is, the number of transfer bytes is always set to 3 blocks (step S31), and the transfer start address is set to be shifted by 3 blocks (step S32). Thus, software processing can be simplified compared to the DMA transfer processing (FIG. 5) in the first embodiment. However, the usage efficiency of the memory 2 decreases.
[0026]
FIG. 6 is a timing chart showing an example of the operation of the second embodiment.
As shown in this figure, when a reproduction request (for example, a reproduction request to room 1) occurs at time T1, data transfer is performed for all three FIFOs (63, 73, 83). The FIFO control unit 62 sequentially outputs WE1, WE2, and WE3 so that data (music data or null data) for three blocks that are DMA-transferred are sequentially stored in the three FIFOs. By executing the DMA transfer twice, the music data to be actually reproduced is stored up to full in the FIFO1 (63), and null data is stored up to full in the FIFO2 (73) and FIFO3 (83), respectively. . Thereby, the FIFO control unit 62 sends an instruction to generate a read strobe signal (RD signal) to each DAC interface circuit (64, 74, 84), and based on this, music data or data is sent from the FIFO to the DAC. Null data is read every sampling period.
[0027]
As described above, according to this embodiment, the read strobe signal (RDn) may be generated only when one of the FIFOs is full regardless of the number of reproduction rooms, and the write enable The signal (WEn) may be output by switching WE1 → WE2 → WE3 every time one block of data is transferred on the assumption that data of three blocks is always transferred. Therefore, the hardware configuration can be simplified. On the other hand, in the case of the first embodiment described above, it is necessary for the FIFO control unit 62 to control the generation of the WEn signal in accordance with the switching of the number of transfer bytes from the DMAC 61.
[0028]
In each of the above-described embodiments, the reproduction of music data has been described. However, in the case of recording, the same configuration can be achieved only by changing the data flow direction.
For example, in FIG. 1, only a single audio input unit 11 is provided (the number of recording channels is 1), but a plurality of audio input units ( Recording channels), and only one of them is provided with a DMAC and a FIFO control unit. The audio input signals of a plurality of channels from the outside are converted into digital data by the ADC of each audio input unit, and written to each recording FIFO under the control of each ADC interface circuit. At this time, writing to each FIFO is performed by a synchronized write enable signal. When a predetermined amount of digital data is stored in the recording FIFO, a recording FIFO control unit provided in common generates a transfer request signal (REQ2) for the bus arbiter 3. When the bus use right is acquired and the transfer request acceptance signal (ACK2) is returned, the data stored in each recording FIFO is collectively stored in the buffer area of the memory 2 under the control of the recording DMAC provided in common. Then transferred. Data stored in the buffer area of the memory 2 is transferred to the HDD 5 under the control of the CPU 1. In this way, audio signals of a plurality of channels can be taken from the outside and recorded on the HDD.
Alternatively, similarly to the second embodiment described above, data for a plurality of recording channels may be collectively transferred to the memory regardless of whether or not recording is actually performed.
As shown in FIG. 1, in a system where recording and playback coexist, a DMAC and a FIFO control unit used in common may be provided on the recording side and the playback side, respectively.
[0029]
Further, in each of the above-described embodiments, the data transfer from the HDD 5 to the memory 2 has been described as being executed by the CPU 1. However, a DMAC is provided, and data transfer from the HDD 5 to the memory 2 is performed by the DMAC. You may do it. In this case, transfer can be performed more efficiently.
Furthermore, in each of the above-described embodiments, the song data stored in the HDD 5 has been described as sampling data that becomes an audio signal by D / A conversion as it is, but the present invention is not limited to this. It may be compressed music data. In this case, it may be decoded at any point before being input to the D / A.
[0030]
【The invention's effect】
As described above, according to the recording / reproducing apparatus of the present invention, it is possible to control transfer of music data to a plurality of FIFOs by using a small number, typically one DMAC. It is possible to configure the recording / reproducing apparatus having a small number of parts.
Further, since the plurality of FIFOs are operated in synchronization, the timing at which the FIFO reaches TH is synchronized. Therefore, DMAC setting for a plurality of FIFOs can be performed by one CPU interrupt, and the load on the CPU can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of a recording / reproducing apparatus of the present invention.
FIG. 2 is a time chart for explaining the operation of the first embodiment of the recording / reproducing apparatus of the present invention;
FIG. 3 is a diagram showing a state in which song data is stored in the HDD.
FIG. 4 is a diagram illustrating a state in which music data is buffered in a memory 2 in the first embodiment.
FIG. 5 is a flowchart for explaining a DMA transfer process in the first embodiment;
FIG. 6 is a time chart for explaining the operation of the second embodiment of the recording / reproducing apparatus of the present invention;
FIG. 7 is a diagram illustrating a state in which music data is buffered in the memory 2 in the second embodiment.
FIG. 8 is a flowchart for explaining DMA transfer processing in the second embodiment;
FIG. 9 is a block diagram showing a configuration of a conventional recording / reproducing apparatus.
FIG. 10 is a diagram showing an example of a memory map of a buffer area in a conventional recording / reproducing apparatus.
FIG. 11 is a flowchart of DMA transfer processing in a conventional recording / reproducing apparatus.
FIG. 12 is a diagram for explaining a FIFO in a conventional recording / reproducing apparatus.
[Explanation of symbols]
1: CPU, 2: Memory, 3: Bus Arbiter, 4: ATAPI Interface Circuit, 5: Hard Disk Device, 6-9: Audio Output Unit, 10: Data Bus, 61: DMAC, 62: FIFO Control Unit, 63, 73 83, 93: FIFO buffer, 64, 74, 84, 94: DAC interface circuit, 65, 75, 85, 95: DAC, 11: audio input unit, 111: ADC, 112: ADC interface circuit, 113: FIFO buffer 114: FIFO control unit, 115: DMAC

Claims (4)

A recording / reproducing apparatus having a plurality of reproduction channels,
A control unit;
A plurality of FIFO buffers provided corresponding to the plurality of reproduction channels, respectively, and reading out in synchronization with each other ;
A memory for sequentially storing a predetermined amount of data to be transferred to a FIFO buffer corresponding to a reproduction channel in which data is reproduced among the plurality of reproduction channels, for each reproduction channel to be reproduced ;
A DMA controller;
A FIFO control unit that controls the plurality of FIFO buffers;
The controller is operable to determine the number of reproduction channels on which data is reproduced and set the data transfer amount corresponding to the number of reproduction channels on which data is reproduced to the DMA controller to operate the DMA controller. The process to set to the state is executed,
The DMA controller, in response to the DMA transfer request from the FIFO control unit, once the DMA transfer, data data of each said predetermined amount for each playback channel playback before Kide over data is performed from the memory Read sequentially to the bus ,
The FIFO controller is configured to request DMA transfer by the DMA controller when the amount of data stored in the FIFO buffer falls below a predetermined value, and to be sequentially read from the memory to the data bus by the DMA controller. A recording / reproducing apparatus for performing a process of sequentially writing the predetermined amount of data to each corresponding FIFO buffer for each reproduction channel on which data is reproduced. A recording / reproducing apparatus having a plurality of reproduction channels,
A control unit;
A plurality of FIFO buffers provided corresponding to the plurality of reproduction channels, respectively, and reading out in synchronization with each other ;
A memory for sequentially storing a predetermined amount of data to be transferred to the plurality of FIFO buffers in correspondence with each reproduction channel , the FIFO buffer corresponding to the reproduction channel in which data is reproduced from the plurality of reproduction channels. a memory for storing null data for the FIFO buffer storing data to be reproduced, corresponding to the reproduction channel reproduction of data of the plurality of reproduction channels is not performed,
A DMA controller;
A FIFO control unit that controls the plurality of FIFO buffers;
The control unit sets a data transfer amount corresponding to the number of the plurality of reproduction channels in the DMA controller regardless of the number of the reproduction channels in which data is reproduced from among the plurality of reproduction channels. The process to set the controller to an operable state is executed.
The DMA controller sequentially reads the predetermined amount of data for each of the plurality of reproduction channels from the memory to a data bus in one DMA transfer in response to a DMA transfer request from the FIFO control unit . ,
The FIFO controller is configured to request DMA transfer by the DMA controller when the amount of data stored in the FIFO buffer falls below a predetermined value, and to be sequentially read from the memory to the data bus by the DMA controller. The recording / reproducing apparatus, wherein the predetermined amount of data for each of the plurality of reproduction channels is sequentially written into a corresponding FIFO buffer. A recording / reproducing apparatus having a plurality of recording channels,
A control unit;
A plurality of FIFO buffers provided corresponding to each of the plurality of recording channels and written in synchronization with each other ;
A memory for sequentially storing a predetermined amount of data transferred from a FIFO buffer corresponding to a recording channel in which data is recorded among the plurality of recording channels, for each recording channel in which recording is performed;
A DMA controller;
A FIFO control unit that controls the plurality of FIFO buffers;
The controller is operable to determine the number of recording channels on which data is recorded and to set the data transfer amount corresponding to the number of recording channels on which data is recorded in the DMA controller to operate the DMA controller. The process to set to the state is executed,
In response to a DMA transfer request from the FIFO control unit , the DMA controller is a FIFO corresponding to a recording channel in which data recording of the plurality of recording channels is performed by the FIFO control unit in one DMA transfer. The data sequentially read from the buffer to the data bus by a predetermined amount is sequentially written to the memory,
When the amount of data stored in the FIFO buffer reaches a predetermined value, the FIFO control unit stores data in the FIFO buffer corresponding to the recording channel on which the DMA transfer is requested by the DMA controller and the data is recorded. The recording / reproducing apparatus is characterized in that it performs a process of sequentially reading out a predetermined amount of data to the data bus . A recording / reproducing apparatus having a plurality of recording channels,
A control unit;
A plurality of FIFO buffers provided corresponding to each of the plurality of recording channels and written in synchronization with each other ;
A memory for sequentially storing a predetermined amount of data transferred from the plurality of FIFO buffers for each recording channel ;
A DMA controller;
A FIFO control unit that controls the plurality of FIFO buffers;
The controller sets a data transfer amount corresponding to the number of the plurality of recording channels in the DMA controller regardless of the number of recording channels in which the data is recorded among the plurality of recording channels. It performs processing to set the controller to an operable state,
The DMA controller, in response to the DMA transfer request from the FIFO control unit, a single DMA transfer, the data are sequentially read to the data bus by a predetermined amount each of the plurality of FIFO buffer to the by the FIFO control unit It writes sequentially to the memory,
The FIFO control unit includes a processing amount data stored in the FIFO buffer requests a DMA transfer by the DMA controller and the predetermined value, the data stored in the plurality of FIFO buffers, the FIFO buffer A recording / reproducing apparatus for performing a process of sequentially reading a predetermined amount to the data bus regardless of whether or not the FIFO buffer corresponds to a recording channel on which data is recorded.

Images