JP4023955B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor equipment, the method relates in particular to a semiconductor equipment metal was filled, such as copper (Cu) into fine recesses for interconnects formed on a semiconductor substrate fabrication.
[0002]
[Prior art]
As a metal material for forming a wiring circuit on a semiconductor substrate, aluminum or an aluminum alloy is generally used, but in recent years, movement using copper has become remarkable. This is not only advantageous for the signal delay phenomenon because the electrical resistivity of copper is 1.72 μΩcm, which is nearly 40% lower than the electrical resistivity of aluminum, but the electromigration resistance of copper is much lower than that of current aluminum. This is because the dual damascene process is easier to adopt than aluminum, and it is likely that a complicated and fine multilayer wiring structure can be manufactured relatively inexpensively.
[0003]
Here, there are three methods of (1) CVD, (2) sputter reflow, and (3) plating as a method of simultaneously embedding a metal such as copper in the wiring groove and via hole by the dual damascene method. Among these methods, the plating method has good embedding property in fine recesses, and tends to enable sound embedding by a relatively easy and inexpensive process. Incorporating into mass production lines is becoming common sense.
[0004]
FIG. 3 shows a basic process used for obtaining a semiconductor device in which a copper wiring is formed on a surface of a semiconductor substrate to form a wiring made of copper. That is, the semiconductor the substrate W, as shown in FIG. 3 (a), an insulating film 2 made of SiO ₂ is deposited on a conductive layer 1a on a semiconductor substrate 1 on which semiconductor devices are formed, lithography etching According to the technique, a minute recess 5 made of a contact hole 3 and a wiring groove 4 is formed, and a diffusion suppression (barrier) layer 6 made of TaN or the like is formed thereon.
[0005]
Then, as shown in FIG. 3B, the surface of the semiconductor substrate W is plated with copper to fill the recesses 5 of the semiconductor substrate 1 with copper 7 and on the diffusion suppression (barrier) layer 6. Copper 7 is deposited on the substrate. Thereafter, the copper 7 on the diffusion suppression (barrier) layer 6 and the diffusion suppression (barrier) layer 6 are removed by chemical mechanical polishing (CMP), and the copper 7 filled in the contact holes 3 and the wiring grooves 4 is removed. And the surface of the insulating film 2 are substantially flush. As a result, a buried wiring made of copper 7 is formed as shown in FIG.
[0006]
Here, when the copper 7 is embedded in the fine recess 5 provided on the surface of the semiconductor substrate W by, for example, an electrolytic plating method, the semiconductor substrate is prior to the copper plating as shown in FIG. Forming a base film 8 to be a power supply (seed) layer on the surface of the diffusion suppression layer 6 formed on W is widely performed. The main purpose of the base film (feeding layer) 8 is to supply a sufficient current to reduce metal ions in the liquid using the surface of the feeding layer as an electrical cathode and deposit it as a metal. In the electroless plating method, a catalyst layer is widely provided as the base film 8 instead of the power feeding layer.
[0007]
[Problems to be solved by the invention]
By the way, the formation of the base film 8 is generally performed by sputtering, but in the film formation by sputtering, the formation of the base film 8 that covers the entire surface of the concave portion 5 as the width of the concave portion 5 becomes narrower and deeper. It becomes difficult. For example, when the width W ₁ of the opening of the recess 5 is 0.25 μm, the limit depth D for forming a sound base film 8 on the entire surface of the recess 5 is said to be about 1.25 μm. .
[0008]
For this reason, when this limit depth is exceeded, as shown in FIG. 4A, the base film 8 is missing in a part of the side wall surface of the fine recess 5 provided on the surface of the substrate W, or A portion U presenting an incomplete shape is generated. When an electrolytic copper plating operation is performed in this state, the plating metal grows from the surface of the base film 8 in the same direction and at the same speed, and the growth of the plating metal is suppressed or prevented from the defective portion U of the base film 8. As a result, the deposition of the U portion plating film is only due to the growth from the adjacent portion in the lateral direction. That is, in this portion, the amount of growth within a predetermined time is smaller than the growth of the plated metal from the sound base film 8. As a result, as shown in FIG. 4B, voids (cavities) 9 are generated inside the copper 7 embedded in the recess 5.
[0009]
In order to prevent this, as shown in FIG. 5A, if the thickness of the base film 8 is made extremely thicker than usual, and the area ratio covered with the base film 8 is greatly increased, The overhang amount of the so-called overhang portion O formed on the shoulder portion of the opening is remarkably increased. In this state, when copper plating is performed, the copper ions replenished into the recess 5 as the plating progresses are exhausted during the plating process, so that the recess is formed as shown in FIG. In many cases, a seam 10, which is a thin slit-like defect, is generated inside the copper 7 embedded in the copper 5.
[0010]
Both the void 9 and the seam 10 which are these plating defects are extremely harmful as a conductive path. Therefore, by eradicating these defects and forming a continuous integrated conductive path, a sufficient current capacity is secured. It is desired to suppress signal delay and improve electromigration resistance. This is the same when electroless plating is performed using a catalyst layer as a base film instead of the power feeding layer in the electrolytic plating.
[0011]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a semiconductor equipment which is adapted to form a buried wiring made defect-free sound conductors into fine recesses.
[0012]
[Means for Solving the Problems]
In the method for manufacturing a semiconductor device of the present invention, a fine recess is formed on the surface of an insulating film on a semiconductor substrate, a diffusion suppressing layer is formed on the insulating film, and a power feeding layer made of copper is formed on the diffusion suppressing layer. or a catalyst layer is formed as a base film, wherein the surface of the base film to form a thin film made of tantalum nitride, grown copper in one direction toward the opening from the bottom of the recess by plating except the bottom of the recess The recess is filled with the copper .
[0015]
Thus, only the plating metal is grown from the underlying film exposed at the bottom of the minute recessed portions, except the bottom so are coated with a thin film, the growth of the plated metal from its parts is stopped. In other words, unlike the conventional method, plating is prevented from growing from the side wall of the recess and grows only in one direction from the bottom of the recess to the opening, so that defects such as voids and seams occur inside this. Can be prevented.
[0016]
The diffusion suppression layer is made of metal nitride, and the base film is made of one or more of copper, palladium, and metal catalyst material. In the case of performing electroplating, the base film is made of copper or palladium to be a power supply (seed) layer, and in the case of electroless plating, the base film is made of a metal catalyst material to be a catalyst layer.
[0017]
Further, the metal nitride is tantalum nitride .
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
First, as shown in FIG. 1A, a fine recess 5 for wiring is formed on the insulating film 2 made of SiO ₂ deposited on the semiconductor substrate of the semiconductor substrate W by lithography / etching technique. Then, a diffusion suppression (barrier) layer 6 made of, for example, tantalum nitride (TaN) or the like is formed. Further, a base film 8 made of, for example, copper, silver or the like and serving as a power feeding (seed) layer is formed on the surface of the diffusion suppressing layer 6. This example shows an example in which electrolytic plating is performed. When performing electroless plating, a catalyst layer made of a metal catalyst material is formed instead of a power feeding layer, and this is used as a base film. To do. Incidentally, the aforementioned copper has an action as a catalyst metal together with palladium, platinum and the like.
[0019]
Then, as shown in FIG. 1B, a thin film 11 made of tantalum nitride is formed only on the surface of the base film 8 except for the bottom of the recess 5. That is, the base film 8 only at the bottom of the concave portion 5 is exposed to the outside, to coat the base film 8 by a thin film 11 otherwise.
[0020]
In this state, an electrolytic plating solution flows into the recess 5 and an electric field is applied to perform electrolytic copper plating on the surface of the semiconductor substrate W. Then, since the power feeding is limited to the bottom surface of the deepest portion of the recess 5, as shown in FIG. 1C, the deposition of the copper 7 by plating proceeds in a state substantially parallel to the bottom surface of the recess 5, and the recess 5 Copper 7 is embedded in That is, the growth of copper 7 embedded by plating occurs only in one direction from the bottom of the recess 5 to the opening. In this way, the copper 7 is sequentially embedded from the deepest portion of the recess 5 and the growth from the side wall portion to the center of the recess 5 is completely prevented, so that the wiring is formed by being embedded in the fine recess 5. It is possible to completely prevent the occurrence of defects such as voids and seals in the copper 7 to be produced.
[0021]
Incidentally, as the Material that form a thin film 11, a conductive bulk low, strong ceramic or intermetallic compound diffusion suppressive and adhesion to copper is suitable. In the present embodiment, tantalum nitride made of the same material as the diffusion suppressing layer 6 is used .
[0022]
Thereafter, the copper 7 on the insulating film 2 is removed by chemical mechanical polishing (CMP) so that the surface of the copper 7 filled in the recess 5 and the surface of the insulating film 2 are substantially flush with each other, as shown in FIG. As shown in d), a wiring made of copper 7 is formed.
[0023]
Figure 2 shows an example of forming a thin film 11 only on the surface except for the bottom of the recess 5 of the underlayer 8. First, as shown in FIG. 2 (a), to form a thin film 11 Ri by the sputtering on the surface of the underlying film 8. Next, as shown in FIG. 2B, the thin film 11 deposited on the bottom surface of the recess 5 is removed by performing sputter etching with Ar ions targeting the substrate side.
[0024]
Various methods can be considered for removing the thin film 11 deposited on the bottom surface of the recess 5. The material of the thin film 1 1, because generally there is little chemical reactivity with the halogen-based gas used in a semiconductor process, it is desirable to advance the etching mainly by physical sputtering. Therefore, this example employs sputter etching with an inert gas targeted at the substrate side.
[0025]
Strictly speaking, it varies depending on the apparatus and operating conditions used, the material of the target thin film 11, and the like, but the rate of sputter etching with Ar ions is considered to be at least about 30 to 60 mm / min.
[0026]
Here, since Ar ions tend to be incident perpendicularly to the substrate surface, the probability that Ar ions collide only with the bottom surface of the recess 5 is much higher than the probability with respect to the side wall surface (selective etching). That is, if Ar ions are irradiated for a certain period of time, only the thin film 11 on the bottom surface of the recess 5 can be selectively removed. Therefore, if the thickness of the thin film 11 deposited on the bottom surface is about 5 nm, the required sputter etching time is within about 1 min.
[0027]
The film thickness of the thin film 11 covering the side wall surface is preferably thin from the viewpoint of minimizing the reduction in the cross-sectional area of the conductive line. On the other hand, it is thick from the viewpoint of ensuring a certain electric insulation. Is more convenient. Therefore, it is considered that the practical thin film 11 has a thickness of about 5 nm (as a guideline for the average value).
[0028]
In addition, a part of the thin film constituent atoms or molecules sputtered by Ar ions and struck out into the air are discharged to the vacuum pump side, and the rest are reattached to the surrounding side wall surface, substrate surface, etc. The amount of redeposition itself is so small that the negative effects of it can be ignored.
[0029]
【The invention's effect】
As described above, according to the present invention, the plating metal constituting the wiring grows in one direction from the bottom of the recess toward the opening in the minute recess, while the plating metal from the side wall of the recess. Therefore, a buried wiring made of a healthy conductor having no internal defects such as voids and seams can be formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
[Figure 2] Similarly, a cross-sectional view showing an example of forming a thin film on the surface except for the bottom of the recess of the base layer in the order of steps.
FIG. 3 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in order of steps.
FIG. 4 is a cross-sectional view for explaining generation of voids in a conventional method of manufacturing a semiconductor device.
FIG. 5 is a cross-sectional view for explaining generation of seams in a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
2 Insulating film 5 Concave part 6 Diffusion suppression layer 7 Copper 8 Base film 11 Thin film W Semiconductor substrate

Claims (4)

Forming a fine recess on the surface of the insulating film on the semiconductor substrate,
Forming a diffusion suppression layer on the insulating film;
On the diffusion suppression layer, a power feeding layer or a catalyst layer made of copper is formed as a base film,
Forming a thin film of tantalum nitride on the surface of the base film excluding the bottom of the recess,
Plating of copper is grown in one direction toward the opening from the bottom of the recess, a method of manufacturing a semiconductor device characterized by filling said recess in said copper. After forming the pre Symbol thin film on the underlying film, by removing the thin film sedimentary the bottom of the recess, forming a pre-Symbol thin film on a surface of the base film excluding the bottom of the recess The method of manufacturing a semiconductor device according to claim 1, wherein: The diffusion barrier layer is composed of metal nitrides, The method according to claim 1, wherein the catalyst layer is characterized by being composed by metallic catalyst materials.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the metal nitride is tantalum nitride.

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