JP4025614B2 - LSI with STTD decoding function - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LSI having an STTD decoding function.
[0002]
[Prior art]
One of the standards supported by IMT2000, which is a global standard for mobile communications established by the ITU (International Telecommunication Union), is the W-CDMA (Wideband Code Division Multiple Access) system.
[0003]
In the W-CDMA system, a transmission diversity technique is adopted as one technique for improving reception characteristics in a terminal. There are several modes for transmit diversity in W-CDMA. One of them is STTD (Space Time Block Coded Transmit Antenna Diversity).
[0004]
FIG. 8 is a diagram illustrating an STTD encoding and propagation model.
[0005]
In the figure, T indicates a symbol time, S1 indicates a transmission symbol 1 including I and Q components, and S2 indicates a transmission symbol 2.
[0006]
In the transmission station, when STTD is applied to the transmission diversity mode, information symbols are encoded and transmitted using two temporally continuous symbols and two transmission antennas.
[0007]
That is, at time T, the transmission complex of the transmission symbol S1 and the transmission symbol S2 multiplied by −1 is simultaneously transmitted from the transmission antenna 1 and the transmission antenna 2, respectively.
[0008]
Next, at time 2T, the conjugate complex numbers of transmission symbol S2 and transmission symbol S1 are simultaneously transmitted from transmission antenna 1 and transmission antenna 2, respectively. After time 3T, the same operation is repeated using the next two consecutive symbols.
[0009]
As described above, STTD encoding is realized by combining two transmission symbols and performing temporal encoding, and transmitting simultaneously from two spatially different transmission antennas.
[0010]
Next, the transmitted information symbols are subjected to amplitude fluctuation and phase fluctuation under the influence of Rayleigh fading in a mobile communication environment, and are received.
[0011]
That is, the symbol transmitted from the transmitting antenna 1 is received after being multiplied by the transfer function (channel estimation value) α1 of amplitude variation and phase variation.
[0012]
Similarly, the symbol transmitted from the transmitting antenna 2 is received after being multiplied by a transfer function (channel estimation value) α2 of amplitude variation and phase variation.
[0013]
At this time, it has been reported that the propagation delay between the two antennas at the receiving end is sufficiently shorter than the chip rate. Therefore, the received symbol R1 or R2 is received in a state in which information symbols transmitted simultaneously from the two antennas are added.
[0014]
Therefore, the received symbols R1 and R2 are expressed by the following equation (1) when white noise is ignored.
R1 ＝ S1 ・ α1－S2 * ・ α2 (S2 * is the conjugate complex number of S2)
R2 = S2 · α1 + S1 * · α2 (S1 * indicates the conjugate complex number of S1) ... Formula (1)
The receiver performs synchronous detection and STTD decoding using the received symbols R1 and R2 represented by Equation (1) and the estimated transfer functions α1 and α2 in the propagation path of each transmitting antenna, and demodulates S1 and S2. To do.
[0015]
That is, when the transmission symbols S1 and S2 are demodulated using Expression (1), Expression (2) is obtained.
[0016]
2 ・ S1 ＝ R1 ・ α1 * ＋ R2 * ・ α2
2 ・ S2 ＝ −R1 ・ α2 + R2 ・ α1 * ... Formula (2)
Incidentally, an interpolation interpolation synchronous detection method is known for transfer function estimation and synchronous detection.
[0017]
Interpolation synchronous detection is based on estimating a transfer function of a propagation path based on a plurality of received symbols, generating a coefficient for phase compensation based on the estimated transfer function, and multiplying the information symbol by this coefficient. This is a technique for performing phase compensation, and is described, for example, in Patent Document 1 below.
[0018]
Further, STTD encoding and decoding are described in, for example, Patent Document 2 below.
[0019]
[Patent Document 1]
JP 2000-78107 A (FIG. 3 etc.)
[Patent Document 2]
JP 2000-138623 A (FIG. 5 etc.)
[0020]
[Problems to be solved by the invention]
However, when STTD decoding is performed, the following problems occur compared to when STTD is not applied.
[0021]
When transmission diversity by STTD is not applied, the same symbol that is not encoded is transmitted simultaneously from two antennas. Therefore, when white noise is ignored, the received symbols R1 and R2 are expressed as in Equation (3).
[0022]
S1 = R1 ・ α * (α = α1 + α2)
S2 = R2 · α * ... Formula (3)
Here, assuming that QPSK (four-phase phase modulation) is adopted as the modulation method of the transmission signal, when Expression (2) and Expression (3) are expanded in consideration of I component and Q component, (4) and Equation (5).
[0023]
Expansion of formula (2)
S1i = α1i ・ R1i + α1q ・ R1q + α2i ・ R2i + α2q ・ R2q
S1q = −α1q ・ R1i + α1i ・ R1q + α2q ・ R2I−α2i ・ R2q
S2i = α1i ・ R2i + α1q ・ R2q−α2i ・ R1I−α2q ・ R1q
S2q = -α1q · R2i + α1i · R2q-α2q · R1i + α2i · R1q (4)
Expansion of formula (3)
S1i = α1i ・ R1i ＋ α1q ・ R1q
S1q = −α1q ・ R1i ＋ α1i ・ R1q
S2i = α1i ・ R2i ＋ α1q ・ R2q
S2q = −α1q · R2i + α1i · R2q Equation (5)
FIG. 7A and FIG. 7B compare Expression (4) and Expression (5).
[0024]
FIG. 7A shows the contents of transmission symbol demodulation calculation (same as Equation 4) when STTD encoding is applied, and FIG. 7B shows transmission symbol demodulation calculation when STTD encoding is not applied. (Same as equation 5). In FIGS. 7A and 7B, the arithmetic expression is divided into a plurality of terms, and each is numbered (1) to (4) so as to be distinguished.
[0025]
When STTD encoding is not used (in the case of FIG. 7B), only the process (1) is necessary to perform phase compensation for the information symbol S1.
[0026]
On the other hand, when the STTD decoding is to be realized (in the case of FIG. 7A), in order to demodulate the information symbol S1, “the processing of (1) and (2)” and “(1), ▲ It is necessary to perform the “addition process of each calculation result 2)”.
[0027]
Similarly, in order to demodulate the information symbol S2, in the STTD decoding, it is necessary to perform the processes (3) and (4) and the addition process of the calculation results (3) and (4), only the process (3). Compared to when STTD is not applied, demodulation of one symbol requires two complex multiplication processes and one addition process.
[0028]
In order to perform STTD decoding in this way, when the complex multiplier configuration necessary for normal phase compensation is diverted, it is necessary to add two complex multiplication processes after that, which increases the circuit scale. Resulting in.
[0029]
An object of the present invention is to solve such problems and to realize a reduction in the area occupied by an LSI circuit.
[0030]
[Means for Solving the Problems]
LSI with STTD decoding function of the present invention receives the STTD encoded signals in a plurality of fingers despreads at each finger, Tsu line demodulation of complex operation and STTD symbols for information symbols output from the respective fingers An LSI having an STTD decoding function for obtaining a decoded signal, and performing a complex operation on the received symbols output from each of the plurality of fingers in a time division manner and performing only a multiplication operation And an addition operation unit included in a rake synthesizer built in the LSI that performs all the addition processing of data necessary for demodulation of the STTD symbol .
[0031]
Efficient use of hardware resources is realized by sharing the complex operation unit and utilizing the adder in the rake synthesizer. Therefore, there is no need to provide a redundant arithmetic circuit, and the exclusive area of the LSI chip can be reduced.
[0033]
Further , it is not necessary to provide an adder for STTD decoding, and the area occupied by the LSI chip can be further reduced. Reduction of redundant circuits also contributes to reduction of power consumption.
Furthermore, the LSI having the STTD decoding function of the present invention receives the STTD encoded signal, performs despreading, and temporarily stores the despread information symbols in the symbol storage memory, while despreading For each finger, a plurality of fingers that perform transfer function estimation in a propagation path using pilot symbols extracted from later signals, a transfer function estimated value that the finger has estimated a transfer function, and an information symbol that is stored in the symbol storage memory A selector that selects and outputs in a time-sharing manner, and a common complex that executes at least a process of multiplying the information symbol output from the selector by a coefficient generated based on the transfer function estimation value output from the selector implementing a calculation unit, at least part of the addition process the data necessary for demodulation of the STTD symbols, Lake if A configuration that includes an addition calculating unit included in the vessel, the.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
[0035]
(Embodiment 1)
FIG. 1 is a diagram illustrating a configuration example of an LSI (CDMA communication system receiver) having an STTD decoding function according to the present invention.
[0036]
As shown in the figure, this LSI (CDMA communication system receiver) includes receiving fingers (hereinafter simply referred to as fingers) 70a to 70n, selectors 82 and 84, a control unit 120 that controls these selectors, and an STTD. A decoder 200 (this portion performs phase compensation and rake combining of received symbols when STTD decoding operation is not performed).
[0037]
Each of the fingers 70a to 70n includes a propagation function transfer function estimation unit (40a to 40n) and a symbol storage memory (20a to 20n).
[0038]
The selector 82 selects one of the estimated transfer functions output from each finger and supplies the selected transfer function to the STTD decoder 200.
[0039]
The selector 84 selects one of the information symbols output from each finger, and provides it to the STTD decoder 200.
[0040]
The STTD decoder 200 includes a transfer function selection unit 50, a complex operation unit 60 (having a multiplication unit 100 and an addition unit 102), and a holding unit 104 and an addition unit 106 (these are rake synthesis units) included in the rake synthesizer 90. And also functions as a part of an STTD symbol demodulator for decoding STTD encoded symbols).
[0041]
The transfer function selection unit 50 generates a complex multiplication coefficient to be supplied to the complex operation unit 60 based on the transfer function of the propagation path estimated by the transfer function estimation units 40a to 40n.
[0042]
The transfer function selection unit 50 distinguishes between the case where the STTD encoded signal is demodulated and the case where the normal signal is demodulated, generates a multiplication coefficient necessary for the scene, and supplies the multiplication coefficient to the complex operation unit 60.
[0043]
Next, a characteristic configuration of the LSI of FIG. 1 will be described.
[0044]
As shown in the above equation (4), for example, the I and Q components of the transmission symbol S1 are expressed as follows.
S1i = α1i ・ R1i + α1q ・ R1q + α2i ・ R2i + α2q ・ R2q
S1q = −α1q ・ R1i + α1i ・ R1q + α2q ・ R2I−α2i ・ R2q
Then, as shown in the upper side of FIG. 7A, the above equation can be divided into two sets of polynomials (1) and (2). Therefore, in order to restore the transmission symbols, it is necessary to calculate the polynomials (1) and (2) (multiplication and addition of complex multiplication coefficients) and add the results.
[0045]
In the present invention, as shown in FIG. 1, multiplication and addition of the first half complex multiplication coefficient are performed by a multiplication unit 100 and an addition unit 102 built in a complex operation unit 60 shared by each finger.
[0046]
Then, addition in the latter half is performed by the holding unit (flip-flop (FF)) 104 and the adding unit 106 in the rake combiner 90.
[0047]
The selectors 82 and 84 are provided to share the complex operation unit 60 among the fingers 70a to 70b.
[0048]
By sharing the complex operation unit 60, the amount of hardware can be reduced, and the power consumption of the circuit can also be reduced.
[0049]
Further, the second half of the addition processing is performed by the holding unit 104 and the addition unit 106 included in the rake combiner essential for the CDMA receiver, so that the existing hardware can be used effectively. Thereby, the amount of hardware and the power consumption of the circuit can be further reduced.
[0050]
FIG. 2 shows main operations in the complex arithmetic unit 60 and the rake synthesizer 90.
[0051]
First, in the stage (a), the complex arithmetic unit 60 performs the arithmetic operation of the above-mentioned polynomial (1).
[0052]
Subsequently, in step (b), the calculation result of (1) is held in the holding unit 104 in the rake synthesizer 90, while the complex calculation unit 60 performs the calculation of the above-described polynomial (2).
[0053]
In step (c), the addition of the calculation results (1) and (2) is performed using the adding unit 106 in the rake synthesizer 90. As a result, the transmission symbols s1i and s1q can be restored.
[0054]
(Embodiment 2)
FIG. 3 is a block diagram of a specific configuration of an LSI having an STTD decoding function according to the second embodiment.
[0055]
In FIG. 3, received symbols are input to the fingers 70a to 70n.
[0056]
3, the selector 80 in FIG. 3 includes a selector 82 that selects one of the estimated transfer functions output from the transfer function estimators 40a to 40n of the fingers 70a to 70n, and the fingers 70a to 70n. Selectors 84a and 84b for selecting one of the information symbols output from the 70n symbol storage memories 20a to 20n.
[0057]
In the following description, processing in the finger 70a will be described as an example. Similar processing is performed for the other fingers.
[0058]
The received data is first despread in the despreading unit 10a.
[0059]
The information symbols after despreading are accumulated in the symbol accumulation memory 20a and input to the pilot symbol extraction unit 30a.
[0060]
Pilot symbols used for transfer function estimation are extracted by the pilot symbol extraction unit 30a and input to the transfer function estimation unit 40a. The transfer function estimation unit 40a estimates transfer functions α1 and α2 in the propagation paths of the two transmission antennas.
[0061]
From the transfer functions α1 and α2 calculated for each finger, the selector 82 selects a transfer function for one finger (here, the transfer function of the finger 70a).
[0062]
Further, one of the information symbols R1 (R1i, R1q) read from the symbol storage memories 20a to 20n is selected by the selectors 84a and 84b.
[0063]
The complex operation unit 60 performs complex multiplication for demodulation on the STTD encoded signal. Further, the complex multiplier 60 performs phase compensation on the normal received signal by interpolation synchronous detection.
[0064]
As shown in FIG. 3, the complex operation unit 60 includes four multipliers 62 to 65 and two adders 66a and 66b.
[0065]
The rake combiner 90 includes flip-flops (FF) 91a, 91b, 93a, 93b, 94a, 94b, and adders 92a, 92b.
[0066]
The demodulated STTD symbols (Si, Sq) output from the rake combiner 90 are sent to a channel codec (not shown).
[0067]
Hereinafter, the demodulation operation of the STTD encoded signal will be described in four steps.
[0068]
Here, the operations of the blocks (1) to (4) shown in FIG. 7A are sequentially executed for each finger.
[0069]
In the first stage, information symbols R1 (R1i, R1q) are read from the symbol storage memory 20a and input to the complex operation unit (phase compensation unit) 60.
[0070]
The coefficients α1i, −α1q, α1q, and α1i generated by the transfer function selection unit 50 are input to the input ports aw, ax, ay, and az of the complex arithmetic unit (phase compensation unit) 60, respectively. Then, a predetermined calculation ((1) in FIG. 7A) is executed.
[0071]
The result of the calculation is sent to the rake combiner 90 and held in flip-flops (FF) 91a and 91b.
[0072]
In the second stage, the information symbol R2 (R2i, R2q) is newly read from the symbol storage memory 20a and input to the complex operation unit (phase compensation unit) 60.
[0073]
The coefficients α2i, α2q, + α2q, and −α2i generated by the transfer function selection unit 50 are input to the input ports aw, ax, ay, and az of the complex arithmetic unit 60. Then, the information symbol is multiplied by the above-described coefficient, and a predetermined addition is performed ((2) in FIG. 7A).
[0074]
The result of the calculation is sent to the rake combiner 90 and held in flip-flops (FF) 91a and 91b. On the other hand, the result of the first stage complex operation previously held is held in the flip-flops 93a and 93b.
[0075]
Next, the results of the complex operations in the first stage and the second stage are added by adders 92a and 92b. The addition result (STTD decode symbol) is temporarily stored in flip-flops (FF) 94a and 94b.
[0076]
This completes the STTD decoding process for one finger (here, finger 70a) for transmission symbol S1.
[0077]
The above-described first stage and second stage processes are sequentially performed for each of the fingers 70b to 70n. Then, the result of each processing is, for example, the maximum ratio combining in the rake combiner 90, and finally the transmission symbol S1 (S1i, S1q) is demodulated.
[0078]
In the third stage, the information symbol R2 (R2i, R2q) is read from the symbol storage memory 20a.
[0079]
Further, the coefficients of -α2i, -α2q, -α2q, α2i are input to the input ports aw, ax, ay, and az of the complex arithmetic unit 60.
[0080]
Then, a predetermined complex operation is performed ((4) in FIG. 7A), and the result is held in the flip-flops 91a and 91b of the rake combiner 90.
[0081]
In the fourth stage, the information symbol R2 (R2i, R2q) is newly read from the symbol storage memory 20a.
[0082]
The coefficients α1i, −α1q, α1q, and α1i are input to the input ports aw, ax, ay, and az of the complex arithmetic unit 60.
[0083]
Then, a predetermined complex operation is performed ((3) in FIG. 7A). The calculation result is sent to the rake combiner 90 and combined with the previous calculation result (the calculation result of (3) in FIG. 7A), and the combined result is temporarily stored in flip-flops (FF) 94a and 94b. Accumulated.
[0084]
Thereby, the STTD decoding process for the finger 70a regarding the transmission symbol S2 is completed. By repeating such three-stage and four-stage processing for each finger, the transmission symbol S2 (S2i, S2q) is finally demodulated.
[0085]
In this way, the complex operation is performed for each finger in a time-sharing manner, and a part of the addition processing necessary for STTD demodulation is performed using the hardware in the rake combiner, thereby making it redundant. By excluding the description, an LSI (CDMA receiver) having an extremely compact STTD decoding function is realized.
[0086]
FIG. 9 shows the configuration of an LSI (comparative example LSI) when the configuration of the present invention is not adopted. In FIG. 9, a plurality of fingers 7a to 7n include despreading units 1a to 1n, symbol storage memories 2a to 2n, pilot symbol extraction units 3a to 3n, transfer function estimation units 4a to 4n, and transfer functions, respectively. Estimating units 5a to 5n and symbol demodulation units 10a to 10n are provided. Reference numeral 9 denotes a rake combiner.
[0087]
In the configuration of FIG. 9, each finger is provided with a complex operation unit (6a to 6n) and a symbol demodulation unit (10a to 10n), and the number of elements constituting the circuit increases dramatically.
[0088]
According to the present invention, the number of circuit elements can be greatly reduced. In mobile phone terminals, miniaturization and low power consumption are strictly required, and the present invention is particularly effective.
[0089]
(Embodiment 3)
FIG. 4 is a block diagram illustrating a configuration of an LSI having an STTD decoding function according to the third embodiment.
[0090]
The LSI having the STTD decoding function shown in FIG. 4 has the same basic configuration and operation as the LSI shown in FIG.
[0091]
However, the complex operation unit 61 in FIG. 4 has only the multiplication unit 100 (there is no addition unit as in FIG. 1), and all the addition processing is performed by the hardware of the rake combiner 90 (holding This is different from the above-described mobile phone in that it is performed in a time division manner using the unit 104 and the addition unit 106).
[0092]
A selector 150 is provided in front of the rake synthesizer 90 in order to perform addition processing in a time division manner using the hardware of the rake synthesizer 90. The selector 150 is controlled by the control unit 122.
[0093]
Since the adder is removed from the complex operation unit 61, the exclusive area of the circuit can be further reduced.
[0094]
A more specific configuration is shown in FIG.
[0095]
The configuration of the LSI of FIG. 5 is basically the same as the configuration of the LSI of FIG. However, the difference is that the adder is removed in the complex arithmetic unit 60 and the selectors 87a and 87b are provided in front of the rake combiner 90.
[0096]
(Embodiment 4)
The LSI of the present invention can be applied to a CDMA receiver as shown in FIG.
In FIG. 6, the LSI of the present invention is shown surrounded by a dotted line. However, the present invention is not limited to this, and all the elements shown in FIG.
[0097]
As shown in the figure, a CDMA receiver includes a receiving antenna 10, a high-frequency signal processing unit 11 that performs filtering at a predetermined frequency and demodulates the baseband signal, and an A / D conversion unit 12 that converts an analog signal into a digital signal. And a de-spreading unit 13 that despreads the received signal at a predetermined timing and demodulates the data, and a synchronous detection unit (also STTD decoding unit) 14 that performs synchronous detection and STTD decoding of the despread data. A rake combining unit 15 that performs rake combining of multipaths that have been detected and STTD decoded, and a channel codec unit 16 that performs channel decoding are provided.
[0098]
The received signal is demodulated into a baseband signal by the high-frequency signal processing unit 11, A / D converted and converted into digital data, and then input to the finger unit 13.
[0099]
In the finger unit 13, data is demodulated and despread by a despreader for the desired number of multipaths and the number of multiplexed codes.
[0100]
The synchronous detection / STTD decoding unit 14 and the rake combining unit 15 compensate the phases of the plurality of data and perform rake combining.
[0101]
The use of the LSI of the present invention contributes to downsizing the CDMA receiver itself.
[0102]
【The invention's effect】
As described above, the present invention contributes to the realization of a small and low power consumption LSI (CDMA receiver) by eliminating the redundant circuit configuration by making efficient use of hardware.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an LSI having an STTD decoding function according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining characteristic operations of the LSI of FIG. FIG. 4 is a block diagram showing a specific configuration of an LSI having an STTD decoding function according to a second embodiment of the invention. FIG. 4 is a block diagram showing a configuration of an LSI having an STTD decoding function according to the third embodiment of the invention. FIG. 5 is a block diagram showing a specific configuration of an LSI having an STTD decoding function according to a third embodiment of the present invention. FIG. 6 is a block diagram showing an overall configuration of a CDMA receiver using the LSI of the present invention. 7A is a diagram showing an arithmetic expression for transmission symbol demodulation when STTD decoding processing is performed. FIG. 8B is a diagram showing an arithmetic expression for transmission symbol demodulation when STTD decoding processing is not performed. ] Contents of STTD encoding and STTD encoding signal FIG. 9 is a block diagram showing the structure of an LSI of a comparative example when the present invention is not applied.
10a ~ 10n Despreading part
20a-20n symbol storage memory
40a to 40n transfer function estimator
50 Transfer function selector
60 Complex operation part
70a ~ 70n Finger
82, 84 selector
90 Rake combiner (also used for STTD symbol demodulation)
100 multiplier
102 Adder
104 Holding part
106 Adder
120 Selector controller
200 STTD decoder (parts particularly relevant to STTD decoding function)

Claims (2)

An LSI with an STTD decoding function that receives STTD encoded signals with multiple fingers, despreads with each finger, and performs complex operation and demodulation of STTD symbols on the information symbols output from each finger to obtain decoded signals Because
A common complex operation unit that performs the complex operation in a time division manner and performs only the multiplication operation for the received symbol output from each of the plurality of fingers;
To implement all of the addition processing of data necessary for demodulation of the STTD symbols, and addition operation unit included in the rake combiner incorporated in the LSI,
An LSI having an STTD decoding function characterized by comprising: While receiving the STTD encoded signal and performing despreading, the information symbol after despreading is temporarily stored in the symbol storage memory, while the transfer function in the propagation path using the pilot symbol extracted from the signal after despreading A plurality of fingers performing estimation;
A selector that selects a transfer function estimated value that the finger has estimated a transfer function and an information symbol stored in the symbol storage memory for each finger and outputs the information symbol in a time-sharing manner;
A common complex operation unit that executes at least a process of multiplying the information symbol output from the selector by a coefficient generated based on the transfer function estimation value output from the selector;
An addition operation unit included in the rake synthesizer that performs at least part of the addition processing of data necessary for demodulation of the STTD symbol;
An LSI having an STTD decoding function characterized by comprising:

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