JP4027052B2 - Polycrystalline semiconductor thin film and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a polycrystalline semiconductor thin film and a method for manufacturing the same. The polycrystalline semiconductor thin film of the present invention is useful for forming an active region in a semiconductor device such as a thin film transistor (TFT), and is an active matrix type liquid crystal display device, FED (field emission display) element, contact image sensor, light receiving. It can be used for devices, three-dimensional ICs, etc.
[0002]
[Prior art]
  In recent years, an attempt has been made to form a high-performance semiconductor device on an insulating substrate such as glass in order to realize a large-sized, high-resolution liquid crystal display device, a high-speed, high-resolution contact image sensor, and a three-dimensional IC. It has been. In such a semiconductor device, a thin silicon semiconductor is generally used. Thin film silicon semiconductors are roughly classified into two types: those made of amorphous silicon semiconductor (a-Si) and those made of crystalline silicon film.
[0003]
  Amorphous silicon semiconductors are most commonly used because they have a low fabrication temperature, can be fabricated relatively easily by a vapor phase method, and are mass-productive. However, silicon semiconductors with physical properties such as conductivity have crystallinity. Inferior to Therefore, in order to obtain higher speed characteristics, establishment of a manufacturing method of a semiconductor device made of a crystalline silicon semiconductor is strongly demanded. Note that polycrystalline silicon, microcrystalline silicon, and the like are known as crystalline silicon semiconductors.
[0004]
  The following methods (1), (2) and (3) are known as methods for obtaining a thin film semiconductor having crystallinity (hereinafter also referred to as a semiconductor film).
[0005]
  (1) A semiconductor film having crystallinity is directly formed at the time of film formation.
[0006]
  (2) After an amorphous semiconductor film is formed, it is irradiated with strong light and crystallized by its energy.
[0007]
  (3) After forming an amorphous semiconductor film, it is made crystalline by applying thermal energy.
[0008]
  However, in the method (1), since crystallization proceeds simultaneously with the film forming step, it is indispensable to increase the film thickness in order to obtain crystalline silicon having a large particle size, and a film having good semiconductor properties is formed on the substrate. It is technically difficult to form a film over the entire surface. Further, since the film forming temperature is as high as 600 ° C. or higher, there is a problem in cost that an inexpensive glass substrate having a low heat-resistant temperature cannot be used.
[0009]
  In the method (2), since the crystallization phenomenon in the melting and solidifying process is used, the grain boundary is satisfactorily processed with a small particle size, and high-quality crystalline silicon can be obtained. However, taking the excimer laser currently most commonly used as an example, the stability of the laser is not sufficient to uniformly treat the entire surface of a large area substrate. Therefore, it is difficult to obtain a silicon film having uniform crystallinity, and it is difficult to obtain a plurality of semiconductor devices having uniform characteristics on the same substrate. Further, since the irradiation area of the laser beam is small, there is a problem that the throughput is low.
[0010]
  The method (3) has an advantage that it can cope with a large area compared to the methods (1) and (2), but the crystallization requires a heat treatment at a high temperature of 600 ° C. or more for several tens of hours. is necessary. Therefore, there are a problem in terms of cost and low throughput in that an inexpensive glass substrate having a low heat-resistant temperature cannot be used. In the method (3), since the solid phase crystallization phenomenon is used, the crystal grains grow parallel to the substrate surface, and even those having a grain size of several μm appear. However, since the grown crystal grains collide with each other to form a grain boundary, the grain boundary serves as a trap level for carriers, which causes a decrease in mobility of a semiconductor device such as a TFT.
[0011]
  A method for producing a silicon film having high quality and uniform crystallinity by heat treatment at a lower temperature and in a short time by applying the method (3) is disclosed in JP-A-9-289167 and the like. Yes.
[0012]
  Japanese Patent Application Laid-Open No. 9-312404 discloses that a heat treatment is performed after introducing a small amount of a metal element such as nickel into the surface of an amorphous silicon film, so that the heat treatment is performed at a low temperature of 600 ° C. or less for a processing time of several hours. Performing crystallization is disclosed. 14A and 14B are schematic diagrams for explaining crystal growth by the method disclosed in the publication. FIG. 14A shows a stage in the process of growth, and FIG. 14B shows a stage after the completion of the growth. By introducing the metal element into the surface of the amorphous silicon film, a compound of silicon and the metal element is formed at an early stage, and thereafter, the metal element serves as a catalyst to start crystal growth centering on the compound to generate crystal nuclei. It is considered that crystal growth is promoted radially from the crystal nucleus, and crystallization proceeds rapidly. Hereinafter, a metal element that promotes crystal growth of a semiconductor such as silicon is also referred to as a catalyst element.
[0013]
  A crystal grain grown by a normal solid phase growth method without using a catalytic element exhibits a twin crystal structure, and there are many crystal defects called twin defects in one crystal grain. On the other hand, when a crystal grows from a crystal nucleus of silicon and a catalytic element, a plurality of columnar semiconductor crystals (hereinafter also simply referred to as “columnar crystals”) that are substantially regarded as a single crystal are centered on the crystal nucleus. It grows radially (see FIG. 14A). In a circular arc region (indicated by hatching in FIG. 14A) that grows in one direction from the crystal nucleus and aggregates a plurality of columnar crystals, the crystal orientations of the respective columnar crystals are aligned. There is little orientation, and there are almost no crystal defects that serve as trap sites for electrons and holes. Also, between different arc-shaped regions formed by growing from one crystal nucleus in different directions, it grows from the same crystal nucleus, so the crystal orientation of the columnar crystals contained in each arc-shaped region is approximate. There is little misorientation and there are almost no crystal defects. The width of the arc-shaped region (the maximum distance in the direction perpendicular to the growth direction) is about 15 μm.
[0014]
  In this way, crystal grains composed of a plurality of columnar crystals grown radially around one crystal nucleus are formed (see FIG. 14B). The plurality of columnar crystals in the crystal grains have almost the same crystal orientation and little misorientation between the columnar crystals, so that there are almost no crystal defects that serve as trap sites for electrons and holes. Hereinafter, a set of columnar crystals that are grown from one crystal nucleus and have substantially the same crystal orientation is referred to as a domain. Since a silicon film formed using a catalytic element has good crystallinity in the domain, for example, when an active region of a TFT is formed in the domain, a TFT having excellent ON characteristics and little variation in rising can be obtained. The crystal grain diameter (domain diameter) is about 100 μm to several hundred μm.
[0015]
[Problems to be solved by the invention]
  However, since a plurality of columnar crystals in a domain generated from another crystal nucleus are substantially aligned in different crystal orientations, a domain generated from one crystal nucleus and a domain generated from another crystal nucleus collide with each other. The misorientation between both domains is large, and a grain boundary including a large number of crystal defects serving as electron and hole trap sites is generated between both domains.
[0016]
  A crystalline silicon film manufactured by the method disclosed in Japanese Patent Laid-Open No. 9-312404 is shown in FIGS. 15 and 16A to 16C. FIG. 15 shows 0.5% hydrofluoric acid and 0.5% H₂  O₂  5 is an optical micrograph after the crystal silicon film has been exposed to etching using an etching solution containing s. FIG. 16A is an image photograph showing the result of measuring the in-plane distribution of crystal orientation in the crystalline silicon film by an EBSP (electron backscatter diffraction pattern) method on a display. FIG. 16B is an image photograph showing, in FIG. 16A, dots where the crystal orientation angles differ by 10 ° or more between adjacent measurement points. FIG. 16C is an image photograph showing an in-plane distribution of crystal orientations when a crystal having a crystal orientation angle difference of 5 ° or less in FIG. 16B is regarded as one crystal, and a region regarded as one crystal. Is represented by the difference in shading.
[0017]
  According to FIG. 15, it can be seen that there is a grain boundary having a large misorientation between crystal grains, and the crystal grains are surrounded by the grain boundary. Note that in this specification, a boundary generated when crystal grains collide with each other is called a grain boundary. Further, according to FIGS. 16A to 16C, columnar crystals grow radially around one crystal nucleus to form a plurality of arc-shaped regions, and the angle difference of crystal orientations within each arc-shaped region is within 5 °. It turns out that it is. In addition, the angle difference of the crystal orientation between the arcuate regions is approximately 10 ° or more and less than 30 °.
[0018]
  Therefore, a TFT in which an active region is formed across a grain boundary between domains includes a large number of crystal defects in the crystalline silicon film, and therefore has lower ON characteristics than a TFT in which an active region is formed in the domain. As a result, the variation in the rising characteristics becomes very large. When such a TFT with large characteristic variation is used as a switching element of a display device, for example, the ON characteristic is poor due to the grain boundary between domains, and the rise variation is large, so display along the grain boundary between domains. Causes spots.
[0019]
  An object of the present invention is to provide a semiconductor device having a high degree of integration by realizing a semiconductor device having stable characteristics with little variation in characteristics. Another object of the present invention is to provide a polycrystalline semiconductor thin film suitable for manufacturing such a semiconductor device. It is another object of the present invention to provide a manufacturing method for manufacturing the semiconductor device or the polycrystalline semiconductor thin film of the present invention with a high yield and a simple method.
[0020]
[Means for Solving the Problems]
  Each of the polycrystalline semiconductor thin films of the present invention has a plurality of columnar shapes.siliconA plurality of domains composed of a crystal and bent or branched in the same plane, the plurality of domains having a crystal orientation between adjacent domainsThere is a region where the angle difference is less than 10 °, and the domain is a collection of columnar crystals grown from one crystal nucleus generated from a compound formed from silicon and nickel.
[0021]
  in frontThe width of the domain is preferably 0.1 μm or more and 1.5 μm or less. The width of the domain refers to the maximum distance of the domain in a direction perpendicular to a direction in which a columnar semiconductor crystal grows from a crystal nucleus described later.
[0022]
  The domain issiliconWhennickelIs formed from a crystal nucleus generated from the compound as a nucleus, and the generation of the crystal nucleus occurs between a temperature lower by 100 ° C. than the formation temperature of the compound and the generation temperature of the compound. The heating rate is equal to or less than the heating rate that maximizes the number.siliconAnd saidnickelIt is preferable that the crystal nucleus is formed by a process including at least a process of heating.
[0023]
  The generation density of the crystal nuclei is 0.5 × 10^-2Piece / μm²  Is preferably larger.
[0024]
  SaidnickelConcentration of 1 × 10¹⁶atoms / cm³  1 × 10 or more¹⁸atoms / cm³  It is preferable to be within the following range.
[0025]
  The semiconductor device of the present invention is a semiconductor device in which a plurality of switching elements are formed from the polycrystalline semiconductor thin film.
[0026]
  Preferably, the switching element is a TFT, the channel region width of the TFT is larger than the domain width, and a plurality of the domains exist in the channel region. The width of the channel region of the TFT refers to the maximum distance of the channel region in a direction perpendicular to the direction from the source region to the drain region.
[0027]
  The liquid crystal display device of the present invention is a liquid crystal display device including the semiconductor device.
[0028]
  The method for producing a polycrystalline semiconductor thin film of the present invention is an amorphoussiliconForming a thin film on a substrate, andnickelIntroducing into the thin film; andsiliconAnd saidnickelForming a crystal nucleus from the compound, and growing a crystal using the crystal nucleus as a nucleus, the method for producing a polycrystalline semiconductor thin film, the generation of the crystal nucleus The step is performed at a temperature increase rate equal to or lower than the temperature increase rate at which the number of crystal nuclei generated is maximized between a temperature lower than the formation temperature of the compound by 100 ° C. and the generation temperature of the compound.siliconAnd saidnickelAt least a step of heating.
[0029]
  The crystal growth step is performed at a higher temperature rising rate than the crystal nucleus generation step.siliconAnd a step of heating the crystal nucleus.
[0030]
  The crystal nucleus generation step is preferably a step of heating to a temperature range of 300 ° C. or higher and 550 ° C. or lower.
[0031]
  The crystal growth step is preferably a step of heating to a temperature range of 550 ° C. or higher and 730 ° C. or lower.
[0032]
  The crystal growth step is preferably performed by RTA (rapid thermal annealing) treatment..
[0033]
  in frontRecordnickelIn the introduction step, a surface concentration of 1 × 10 6 is applied to the surface of the thin film or the substrate.¹²atoms / cm²  1 × 10 or more¹⁴atoms / cm²  Said to be within the following rangenickelIs preferably introduced.
[0034]
  SaidnickelThe introduction processnickelIt is preferable to include the process of apply | coating the solution containing this on the said thin film by a spin coat method.
[0035]
  SaidnickelThe solution containing preferably contains at least one selected from the group consisting of water, methanol, ethanol, n-propanol, i-propanol and acetone.,in frontRecordnickelIt is preferable that the solution containing nickel acetate contains nickel acetate.
[0036]
  SaidnickelThe introducing step is preferably performed by a DC sputtering method.
[0037]
  It is preferable that the polycrystalline semiconductor thin film crystallized by the crystal growth step includes a minute amorphous region. It is preferable to include a step of performing intense light irradiation on the minute amorphous region.
[0038]
  An excimer laser beam having a wavelength of 400 nm or less is used as the intense light, and the energy density on the surface of the thin film is 200 mJ / cm.²  450 mJ / cm²  Irradiation is preferably performed within the following range.
[0039]
  It is preferable to include a step of performing a thermal oxidation treatment after the crystal growth step.
[0040]
  The generation density of the crystal nuclei is 1.5 × 10^-2Piece / μm²  Is preferably larger.
[0041]
  The polycrystalline semiconductor thin film of the present invention will be described with reference to the drawings. 1A and 1B are schematic views for explaining crystal growth of a polycrystalline semiconductor thin film according to the present invention. FIG. 1A shows a stage in the process of growth, and FIG. 1B shows a stage after the growth is completed. Hereinafter, silicon will be described as an example of a semiconductor.The1A and 1B, the arrows indicate the trajectories in the growth direction, and the positions of the crystal nuclei A, C, D, E, and F indicate the positions before the start of crystal growth.
[0042]
  The polycrystalline semiconductor thin film of the present invention includes a plurality of domains each composed of a plurality of columnar semiconductor crystals and bent or branched in the same plane. Each domain has a plurality of columnar crystals grown from one crystal nucleus, and the plurality of columnar crystals have substantially the same crystal orientation. Therefore, in each domain, there are almost no crystal defects that serve as trap sites for electrons and holes.
[0043]
  As shown in FIG. 1A, crystallization starts in a random direction from a plurality of crystal nuclei A, C, D, E, and F generated in an amorphous semiconductor thin film. Due to the difference in chemical potential, the crystal nucleus is most stable in terms of energy when it exists at the amorphous / crystallized boundary, and moves around the amorphous region around the crystal nucleus with crystallization. Thus, a plurality of columnar crystals CS having substantially uniform crystal orientations are grown. Strictly speaking, a fragment from which a part of a crystal nucleus is separated moves in an amorphous region.
[0044]
  When the crystal nucleus moves and grows, the growth direction changes, and the domains are bent or branched in the same plane. As the growth direction changes, the crystal orientation of the columnar crystal CS at the growth tip gradually changes. However, since such a change in crystal orientation occurs to relieve stress in the thin film, large crystal defects such as penetration and stacking faults do not occur, and the crystal orientation changes so as to minimize crystal defects. . In addition, since the crystal orientation changes while gradually twisting, the crystal lattice is continuous and connected at the atomic level. As described above, the crystal orientation is different even within a single domain. However, the columnar crystal CS in the single domain has a continuous crystal lattice, and there are almost no crystal defects. Hereinafter, in order to contrast with the above-mentioned granular domains (crystal grains), a domain in which the direction of crystal growth is changed and bent or branched is also referred to as a rod-shaped domain RC.
[0045]
  FIG. 2 shows an optical micrograph of the rod-like domain in the initial crystal growth stage. A white portion in FIG. 2 indicates a rod-like domain. The width of the columnar crystal CS (the maximum distance of the columnar crystal CS in the direction perpendicular to the growth direction of the columnar crystal CS, which is indicated by W1 in FIG. 1A) is about 10 nm to 100 nm. The width of the rod-like domain (the maximum distance of the domain in the direction perpendicular to the growth direction of the columnar crystal CS, indicated by W2 in FIGS. 1A and 1B) is 0.1 μm or more and 1.5 μm or less. When the width of the rod-like domain is less than 0.1 μm, the crystal growth may be terminated with insufficient crystal growth, and a large amorphous region may remain in the film. If the width of the rod-shaped domain exceeds 1.5 μm, the area in contact with other rod-shaped domains may decrease, and there may be a decrease in the area where the crystal orientation is substantially the same between adjacent rod-shaped domains.
[0046]
  The rod-shaped domain RC continues to grow while being bent or branched while the growth direction changes during the growth. As shown in FIG. 1A, growth starts in a random direction from a plurality of crystal nuclei A, C, D, E, and F generated in an amorphous semiconductor thin film, and continues to grow while changing the growth direction. . As a result, as shown in FIG. 1B, the rod-like domain RC generated from one crystal nucleus (for example, crystal nucleus D in FIG. 1A) in the same plane becomes a plurality of other crystal nuclei (for example, crystals in FIG. 1A). It comes into contact with the rod-like domain RC generated from the nuclei A, B, C, E, F). Due to the difference in the crystal orientation of the columnar crystal CS included in each rod-shaped domain RC, a portion of the region where the rod-shaped domain RC generated from one crystal nucleus and the rod-shaped domain RC generated from another crystal nucleus are in contact with each other. A boundary having defects is formed. A solid line portion in FIG. 1B indicates a boundary.
[0047]
  However, as described above, each rod-like domain RC grows while the crystal orientation of the columnar crystal CS is gradually changed. Moreover, since each rod-shaped domain RC is bent or branched, a region in contact with a plurality of other rod-shaped domains RC is long. Therefore, a region in which the crystal orientations of the columnar crystals CS are substantially the same, that is, a region in which there is almost no difference in crystal orientation angle is formed between adjacent rod-like domains RC. For example, a boundary having a crystal defect is formed between the rod-shaped domain RC generated from the crystal nucleus D in FIG. 1A and the adjacent rod-shaped domain RC generated from another crystal nucleus B, and the columnar crystal A region (region without a boundary) having substantially the same crystal orientation of CS is formed. In this region, the crystal lattice is substantially continuous and connected at the atomic level, and there are almost no crystal defects. Such regions having substantially the same crystal orientation are formed at various locations within the same plane.
[0048]
  A region having substantially the same crystal orientation is formed between adjacent rod-shaped domains RC because the rod-shaped domain RC is bent or branched in the same plane and grown from the crystal nucleus of each rod-shaped domain RC. This is considered to be due to the random starting direction. As a result, the region where the different rod-shaped domains RC are in contact with each other becomes longer, and there is a high possibility that a region having substantially the same crystal orientation is formed between the adjacent rod-shaped domains RC.
[0049]
  Here, “a region in which the crystal orientation is substantially the same between adjacent domains” means that there is almost no crystal defect that becomes a trap site of electrons or holes between adjacent domains. It means that there is almost no difference in azimuth angle. Specifically, the difference in crystal orientation angle is less than 10 °, preferably less than 5 °. The difference in crystal orientation angle is preferably 3 ° or less, more preferably 2 ° or less. The difference in crystal orientation angle can be measured by the EBSP method.
[0050]
  If there is a region having substantially the same crystal orientation between adjacent domains, electrons or vacancies can move between both domains through this region. In the present invention, regions having substantially the same crystal orientation are formed (randomly) at various locations in the same plane, so that stable characteristics with little variation are obtained regardless of the direction of the channel region of the TFT. be able to.
[0051]
  3A and 3B and FIGS. 4A, 4B, and 4C are diagrams showing a polycrystalline semiconductor thin film formed of rod-like domains. FIG. 3A shows the seco liquid (K₂  CrO₄  0.06 mol / L, HF; 25%, water; 75%), a SEM (Scanning Electron Microscope) photograph after the polycrystalline semiconductor thin film has been exposed and etched, FIG. 3B shows the polycrystalline semiconductor thin film 2 is an image photograph in which the in-plane distribution of crystal orientations measured by the EBSP method is displayed on a display, and the difference in crystal orientation is represented by the difference in light and shade. From FIG. 3B, it can be seen that each rod-like domain is bent or branched and has approximately a single crystal orientation. It can also be seen that the rod-like domains have different crystal orientations.
[0052]
  FIG. 4A is an image photograph in which dots having a crystal orientation angle difference of 2 ° or more between adjacent measurement points in FIG. 3B are represented by dots, and portions having a crystal orientation angle difference of less than 2 ° are blank. ing. FIG. 4B is an image photograph in which FIG. 3B and FIG. 4A are superimposed. FIG. 4C is an image photograph in which a portion where the crystal orientation angle difference is 2 ° or more and less than 5 ° in FIG. 4B is shown by light dots, and a portion where the crystal orientation angle difference is 5 ° or more is shown by dark dots. From FIG. 4C, the polycrystalline semiconductor thin film formed with the rod-like domains has many portions where the crystal orientation angle difference is less than 5 °, and the rod-like domains are not surrounded by the dots with the crystal orientation angle difference of 5 ° or more. I understand.
[0053]
  An etching rate is different between a region having many crystal defects and a region having few crystal defects, and a region having few crystal defects has a high etching rate, and a region having many crystal defects has a slow etching rate, so that irregularities are formed. In the SEM image after the etching process in FIG. 3A, a black region is a region with few crystal defects, and a white region is a region with many crystal defects. A region with many crystal defects corresponds to a misorientation region, and a boundary exists between domains. However, it can be seen that each rod-like domain is not surrounded by a boundary and is continuous with other adjacent rod-like domains (see FIGS. 3A and 4A). Therefore, when electrons or holes move from point A to point B in FIG. 4B, the straight line connecting points A and B crosses the boundary (misorientation region), so the electrons or holes move from point A to point B. It is difficult to move to a point in a straight line direction (since there are many crystal defects at the boundary, electrons or vacancies are trapped). However, the rod-like domain is not surrounded by the boundary, and there is a region where the crystal orientation is substantially the same between the adjacent rod-like domains. To B. That is, electrons or vacancies can move between adjacent domains through regions with substantially the same crystal orientation.
[0054]
  In contrast, FIG.6In B, each granular domain is surrounded by a grain boundary and is not connected to other adjacent granular domains. Therefore, the electrons or vacancies in the granular domain are trapped at the grain boundary, so that it is difficult to move to the adjacent granular domain.
[0055]
  As described above, the polycrystalline semiconductor thin film of the present invention can move between rod-like domains in which electrons or vacancies are adjacent to each other, so that high mobility can be expected. Therefore, when a plurality of switching elements are manufactured from the polycrystalline semiconductor thin film of the present invention, a high performance semiconductor device with high ON characteristics can be obtained because of high mobility.
[0056]
  In addition, if the width of the TFT channel region is larger than the width of the rod-like domain, a plurality of rod-like domains exist in the channel region. Therefore, the TFT characteristics are averaged, and there is little variation in rising characteristics. A device is obtained.
[0057]
  Furthermore, a liquid crystal display device using the semiconductor device of the present invention as a switching element can obtain a clear image in which occurrence of display spots is suppressed. The liquid crystal display device includes at least an element substrate having the semiconductor device of the present invention, a counter substrate disposed opposite to the element substrate and having a counter electrode, and a liquid crystal layer interposed between the element substrate and the counter substrate. Prepare. It is also possible to manufacture a drive circuit from the polycrystalline semiconductor thin film of the present invention. By forming the switching element and the drive circuit from the polycrystalline semiconductor thin film on the glass substrate, significant cost reduction, downsizing, and reliability can be achieved. An improvement can be realized.
[0058]
  Hereinafter, the manufacturing method of the polycrystalline semiconductor thin film of this invention is demonstrated. The method for producing a polycrystalline semiconductor thin film according to the present invention includes a step of forming an amorphous semiconductor thin film on a substrate, a step of introducing a catalytic element for promoting crystallization of the semiconductor into the thin film, The method includes at least a step of forming a compound with the catalyst element and generating a crystal nucleus from the compound, and a step of growing a crystal using the crystal nucleus as a nucleus. Hereinafter, each step will be described by taking silicon as an example, but the present invention can also be applied to germanium, a mixed crystal of germanium and silicon, and these compounds.
[0059]
  (1) Amorphous silicon film formation process
  This step is a step of forming an amorphous silicon thin film (hereinafter also referred to as an amorphous silicon film) on a substrate.
[0060]
  A method for forming the amorphous silicon film on the substrate is not particularly limited, and examples thereof include a plasma CVD (Chemical Vapor Deposition) method and a sputtering method. In the present invention, the plasma CVD method is preferable. According to the plasma CVD method, an amorphous silicon film can be formed at a low temperature and at a high speed. The film thickness of the amorphous silicon film formed on the substrate is about 50 to 150 nm.
[0061]
  Although it does not specifically limit as a board | substrate which can be used in this invention, A glass substrate is mentioned. As will be described later, in the present invention, crystallization can be carried out by treatment for several hours at a low temperature of 600 ° C. or lower, so that it is replaced with an expensive quartz substrate having high heat resistance and almost no heat shrinkability. Thus, an inexpensive glass substrate can be used.
[0062]
  Before forming an amorphous silicon film on a glass substrate, a base film made of silicon oxide is formed on the glass substrate to prevent impurities in the glass substrate from diffusing into the amorphous silicon film. Is preferred.
[0063]
  (2) Catalyst element introduction process
  This step is a step of introducing a catalytic element that promotes crystallization of silicon into the amorphous silicon film.
[0064]
  Examples of catalyst elements that promote crystallization of semiconductors include Ni, Co, Pd, Pt, Cu, Ag, Au, In, Sn, Al, and Sb, and one or more elements selected from these elements. By using, the effect of promoting crystallization occurs in a small amount. The following model can be considered as the reason. The catalytic element does not act alone, but promotes crystal growth by forming a compound (silicide) by bonding with the semiconductor (silicon). At that time, when the semiconductor thin film having an amorphous crystal structure is crystallized, it acts like a kind of template to promote crystallization.
[0065]
  Among these catalytic elements, Ni is preferable as a catalytic element that promotes crystallization of silicon. Ni is NiSi together with 2 Si₂  (Silicide) is formed. NiSi₂  Has a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi₂  Has a lattice constant of 5.406 、, which is very close to the lattice constant of 5.430 の of crystalline silicon. Therefore, NiSi₂  Is an optimal template for crystallizing an amorphous silicon film, and Ni is considered to be most desirable as a catalyst element for promoting the crystallization of silicon.
[0066]
  Examples of the method for introducing the catalyst element include sputtering, vapor deposition, plating, ion doping, CVD, and spin coating. The spin coating method is a method in which a solution or dispersion of a catalytic element is applied onto a substrate and dried, and a catalyst introduced into an amorphous silicon film by adjusting the concentration of the catalytic element in the solution or dispersion. The amount of element can be adjusted.
[0067]
  The concentration of the catalytic element in the amorphous silicon film is 1 × 10¹⁶atoms / cm³  1 × 10 or more¹⁸atoms / cm³  The following degree is preferable. The concentration of the catalytic element is 1 × 10¹⁶atoms / cm³  If it is less than 1, the crystal growth becomes insufficient, and many amorphous regions remain. On the other hand, the concentration of the catalytic element is 1 × 10¹⁸atoms / cm³  In the case where the channel area of the semiconductor device is exceeded, the catalytic element may cause a leak when the channel region of the semiconductor device is formed.
[0068]
  The step of introducing the catalytic element into the amorphous silicon film may be performed either before or after the amorphous silicon film is formed on the insulating substrate, as long as it is before the crystal nucleus forming step described later. Normally, before forming an amorphous silicon film on an insulating substrate, a base film made of silicon oxide is formed on the insulating substrate, and impurities in the insulating substrate are diffused into the amorphous silicon film. prevent. Since the surface of the amorphous silicon film is hydrophobic, the surface of the base film is hydrophilic. Therefore, when spin coating is performed using a hydrophilic solvent, it is better to apply on the base film. It can be applied more stably than when applied on an amorphous silicon film. When the catalytic element is introduced onto the glass substrate or the base film, crystal growth starts from the lower surface of the amorphous silicon film.
[0069]
  The surface concentration of the solution containing the catalytic element is 1 × 10 5 by spin coating.¹²atoms / cm²  1 × 10 or more¹⁴atoms / cm²  It is applied on an insulating substrate or an amorphous silicon film and dried so as to be as follows. Surface concentration is 1 × 10¹²atoms / cm²  If it is less than 1, the crystal growth is insufficient and many amorphous regions remain. Surface concentration is 1 × 10¹⁴atoms / cm²  If it exceeds 1, crystals may grow in multiple directions from one crystal nucleus to form granular domains. The surface concentration of the catalytic element can be measured by a total reflection X-ray fluorescence analysis (TRXRF) method or the like.
[0070]
  The solution containing a catalytic element (for example, nickel) preferably contains at least one solvent selected from the group consisting of water, methanol, ethanol, n-propanol, i-propanol, and acetone. When nickel is used as the catalyst element, nickel can be uniformly applied on the insulating substrate or the amorphous silicon film by dissolving nickel acetate in the solvent.
[0071]
  Similarly, a catalytic element such as nickel can be introduced by a DC (direct current) sputtering method at a low voltage. At this time, it is possible to introduce a catalyst element having a very low concentration by reducing the DC voltage. For example, the DC voltage is set to about 200V to 600V.
[0072]
  The catalytic element applied on the insulating substrate or the amorphous silicon film is taken into the amorphous silicon film by heating in the following crystal nucleation step.
[0073]
  (3) Crystal nucleation process
  This step is a step of forming a compound (silicide) of silicon and a catalytic element and generating crystal nuclei from the compound.
[0074]
  In the crystallization method using a catalytic element, a compound of the catalytic element and silicon (silicide) is formed by the reaction of the catalytic element and silicon in the heating process in which the catalytic element is introduced, and the crystal nucleus is further formed from the silicide. It is formed and crystal growth starts from the crystal nucleus. The crystal nucleus means a compound at an early stage where crystal growth has started. Not all of the compounds (silicides) become crystal nuclei, and there are silicides that re-dissolve during temperature rise due to changes in solid solubility accompanying temperature rise. If the silicide is too small, crystal growth does not occur and crystal nuclei are not generated.
[0075]
  In the present invention, by increasing the generation density of crystal nuclei and reducing the amount of catalytic elements in one crystal nucleus, crystal growth is started in one direction from one crystal nucleus, and the width of the rod-like domain is reduced. The rod-like domain can be grown while being bent or branched. On the other hand, in the granular domain, the generation density of crystal nuclei is low and the amount of catalytic elements in one crystal nucleus is large, so that crystal growth starts from one crystal nucleus in a radial (multidirectional) manner, and is substantially linear. Grows (without bending or branching).
[0076]
  However, in order to increase the generation density of crystal nuclei and reduce the amount of catalyst element in one crystal nucleus, it is not sufficient to adjust the introduction amount of the catalyst element. Control is needed. FIG. 5 is a graph showing the relationship between the rate of temperature rise during crystallization annealing and the crystal nucleus generation density. From FIG. 5, it can be seen that the crystal nucleus generation density has a certain maximum point with respect to the rate of temperature increase, and the crystal nucleus generation density rapidly decreases at a temperature increase rate larger than the maximum point. FIG. 2 shows an optical micrograph of the state of crystal nucleation when the heating rate is 10 ° C./min, and FIG. 6 shows an optical micrograph of the state of crystal nucleation when the heating rate is about 50 ° C./min. . 2 and 6 show that the crystal growth is stopped at an early stage of crystal growth by heating at 250 ° C. to 550 ° C. at respective heating rates and then heating at a temperature of 550 ° C. for 15 minutes. This is an observation of the state of crystal nucleus generation.
[0077]
  A rod-like domain is formed below the heating rate at which the nucleation density is maximum (see FIG. 2), but granular domains are formed at a heating rate greater than the heating rate at which the nucleation density is maximum (see FIG. 2). (See FIG. 6). That is, a polycrystalline silicon film having a high crystal nucleus generation density and made of rod-like domains can be obtained by setting the temperature increase rate during the crystallization annealing to a temperature increase rate that maximizes the crystal nucleus generation density.
[0078]
  The rate of temperature increase at which the nucleation density is maximized depends on the film quality of the amorphous silicon film, and therefore is appropriately determined according to conditions such as the type of amorphous silicon film and the type of catalytic element. For example, the amorphous silicon film used in FIG. 5 is a parallel plate type plasma CVD method, and the power density of RF power is 80 mW / cm.²  And SiH₄  And H₂  The film was formed at a substrate temperature of 430 ° C. using a mixed gas of Nickel was used as a catalyst element and introduced into the amorphous silicon film surface. The surface concentration of nickel introduced into the amorphous silicon film surface is 7 × 10¹²atoms / cm²  Met. In this case, the heating rate at which the nucleation density was maximum was 45 ° C./min.
[0079]
  The reason why the shape of the domain growing from the crystal nucleus and the crystal nucleus generation density change due to the change in the heating rate is not clear, but can be explained by the following model. When the rate of temperature increase is high, the temperature rises until the silicide is formed, and the silicide is formed at a high temperature, so that the diffusion of the catalyst element increases. Further, since the thermal energy at the time of silicide formation is large, large silicide grows and the generation density of silicide is lowered. When a crystal is grown from such a large silicide having a low generation density, a large amount of catalytic elements are contained in the silicide, so that the width of the domain as a bundle of generated columnar crystals becomes very large. Accordingly, the crystal growth proceeds from the crystal nucleus as a granular domain, and the generation density of silicide is low, so the crystal nucleus generation density is also low.
[0080]
  On the other hand, when the rate of temperature increase is small, there is a time margin for forming silicide even at a low temperature stage, so that silicide is formed at a low temperature and the diffusion of the catalyst element is small. Since the thermal energy at the time of silicide formation is small, small silicide is generated at a high density. When a crystal is grown from such a small silicide having a high generation density, the amount of the catalytic element in the silicide is small, and therefore the width of the domain as a bundle of generated columnar crystals becomes very small. Accordingly, crystal growth proceeds from the crystal nucleus as a rod-like domain, and the generation density of silicide is high, so the crystal nucleus generation density is also high.
[0081]
  Heating at a temperature rise rate or less at which the nucleation density is maximized is performed at least from a temperature lower by 100 ° C. than the formation temperature of the compound of the semiconductor and the catalytic element to the generation temperature of the compound. For example, in the case of silicon, the generation temperature of the compound (silicide) is in the range of about 300 ° C. or more and about 400 ° C. or less. The temperature is increased at a temperature increase rate (for example, 40 ° C./min) equal to or lower than the temperature increase rate at which the generation density is maximum. Formation of the compound of the semiconductor and the catalytic element can be confirmed by, for example, TEM (Transmission Electron Microscope).
[0082]
  After the compound of the semiconductor and the catalytic element is formed, there is no restriction on the rate of temperature rise, and heating can be performed at a temperature rise rate that is equal to or lower than the temperature rise rate at which the nucleation density is maximized or greater than this temperature rise rate. . For example, in the case of silicon, the generation temperature of crystal nuclei is about 500 ° C. or more, and after the generation of the compound (silicide), the temperature increase rate is higher than the temperature increase rate at which the nucleus generation density becomes maximum (for example, 50 ° C./min). You may heat up to about 500 degreeC.
[0083]
  (4) Crystal growth process
  This step is a step of growing a crystal using a crystal nucleus formed from a compound (silicide) of silicon and a catalytic element as a nucleus.
[0084]
  In this step, the temperature is raised to a temperature higher than the generation temperature of crystal nuclei to grow columnar crystals and form rod-like domains. In this step, the temperature can be increased at a rate higher than the rate of temperature increase when the compound of the semiconductor and the catalytic element is formed, thereby significantly reducing the processing time.
[0085]
  7A, 7B, and 7C are graphs showing the rate of temperature increase in the crystal nucleus formation step and the crystal growth step. In FIG. 7A, the heating rate is the same in each step of the crystal nucleation step and the crystal growth step. For example, the temperature is raised to a temperature within the range of 370 ° C. to 730 ° C. at a rate of temperature rise of 10 ° C./min (denoted as T1 in FIGS. 7A, B, and C).₁  Heat for about several hours.
[0086]
  In FIG. 7B, the rate of temperature rise is higher in the crystal growth step than in the crystal nucleus formation step. For example, in the crystal nucleation step, the generation temperature of a compound or crystal nuclei (a temperature in the range of 330 ° C. to 550 ° C. is shown in FIGS.₂  Is written. ) At a heating rate of 10 ° C./min, and in the crystal growth step, the temperature T is increased at a heating rate of 100 ° C./min.₁  Up to a temperature T₁  Heat for about several hours.
[0087]
  In FIG. 7C, the temperature growth rate is higher in the crystal growth step than in the crystal nucleus formation step, and the temperature increase rate in the crystal growth step changes stepwise. For example, in the crystal nucleation step, the temperature is increased to a temperature T2 at a temperature increase rate of 10 ° C./min, and in the crystal growth step, the temperature T is increased at a temperature increase rate of 100 ° C./min.₁  And the temperature T is increased at a rate of temperature increase of 300 ° C./min.₁  Higher temperature (eg, 550 ° C. to 730 ° C., T in FIG.₃  Is written. ) And then the temperature is lowered to room temperature over about 30 minutes.
[0088]
  7A, 7B, and 7C, the crystal nucleus formation step is performed at the same temperature increase rate, but the temperature increase rate until the compound of the semiconductor and the catalytic element is formed and the crystal nucleus is formed from the compound. It may be different from the rate of temperature rise until.
[0089]
  The crystal growth step may be performed by RTA (rapid thermal annealing) treatment. Since the RTA treatment can raise the temperature rapidly in a short time, when a glass substrate is used, the glass substrate can be heated so as not to warp even at a temperature higher than the strain point temperature of the glass.
[0090]
  The polycrystalline semiconductor thin film crystallized by the crystal growth step preferably includes a minute amorphous region. By including the amorphous region, the efficiency of subsequent intense light irradiation can be improved. The amorphous region is preferably about 5% to 10% of the area of the film surface. FIG. 8 is a photomicrograph of the surface of the polycrystalline silicon film on which crystals have been grown by raising the temperature from 250 ° C. to 550 ° C. at a temperature raising rate of 10 ° C./min. FIG. 8 shows that the film surface is substantially filled with crystalline silicon, but includes a minute amorphous region (black granular portion in FIG. 8).
[0091]
  By performing intense light irradiation on the amorphous region, defects in the crystal are reduced, characteristics of the semiconductor device are improved, and a stable semiconductor device with little variation can be obtained. Excimer laser light having a wavelength of 400 nm or less is used as intense light, and the energy density on the surface of the polycrystalline semiconductor thin film is 200 mJ / cm²  450 mJ / cm²  By irradiating within the following range, the crystallinity improving effect can be improved. In intense light irradiation, it is preferable to heat the substrate to 200 ° C. or higher and 450 ° C. or lower.
[0092]
  Further, by performing a thermal oxidation treatment after the crystal growth step, defects in the crystal are reduced, characteristics of the semiconductor device are improved, and a stable semiconductor device with little variation can be obtained. Specifically, when a quartz substrate is used, dry oxidation (O) in a temperature range of 850 ° C. to 1100 ° C. for about 0.1 hour to 5 hours at normal pressure.₂  Oxidation). When a glass substrate is used, steam oxidation (H in a temperature range of 550 ° C. or more and 650 ° C. or less and about 0.5 hours to 5 hours or less and 5 atmospheres to 20 atmospheres)₂  O oxidation). The thermal oxidation treatment can be performed regardless of the presence or absence of the intense light irradiation.
[0093]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments.
[0094]
  (Embodiment 1)
  This embodiment will be described using an N-type TFT as an example. The TFT of this embodiment can be used not only as an active matrix driver circuit and pixel portion but also as an element constituting a thin film integrated circuit. In the present embodiment, pixel TFTs on an active matrix substrate for a liquid crystal display device will be described as an example as a representative thereof. It is required to uniformly produce hundreds of thousands to millions of N-type TFTs on an active matrix substrate for a liquid crystal display device.
[0095]
  9A, 9B, 9C and 9D are plan views schematically showing the manufacturing process of the pixel TFT of this embodiment. In reality, hundreds of thousands or more of pixel TFTs are formed on the active matrix substrate, but in FIGS. 9A to 9D, description will be made in a simplified manner with 12 TFTs of 3 rows × 4 columns. 10A, 10B, 10C, 10D and 10E are cross-sectional views schematically showing the manufacturing process of one pixel TFT of this embodiment.
[0096]
  First, as shown in FIGS. 9A and 10A, a silicon oxide film 102 is formed on a glass substrate (Corning 1737, etc.) 101 as a base coat film (BC film) by a plasma CVD method at a substrate temperature of 430 ° C. with a thickness of 100 nm to 100 nm. A film of 400 nm, for example, 300 nm is formed, and then an intrinsic (I-type) amorphous silicon film (a-Si film) 103 is formed to a thickness of 25 nm to 80 nm, for example, 30 nm at a substrate temperature of 430 ° C. This is treated with 0.5% hydrofluoric acid for 30 seconds to remove the natural oxide film on the surface, and the surface of the a-Si film 103 is further treated with ozone water to improve wettability.
[0097]
  As shown in FIG. 10A, a solution containing nickel 104 on the a-Si film 103 has a surface concentration of 1 × 10 5 by spin coating.¹²atoms / cm²  ~ 1x10¹⁴atoms / cm²  For example 5 × 10¹²atoms / cm²  Add to be. The surface concentration is a result of measurement with a total reflection X-ray fluorescence analyzer (TRXRF). Water is used as the solvent, and nickel acetate is used as the solute. Since nickel acetate is very soluble in water, a nickel solution having a stable concentration can be prepared. Further, it can be added uniformly on the a-Si film 103. The amount of nickel added can be controlled by the concentration of the solution (FIG. 10A). The concentration of the catalytic element in the a-Si film 103 is, for example, 5 × 10¹⁷atoms / cm³  It is.
[0098]
  Next, in an inert atmosphere, it is heated to 300 ° C. to 550 ° C. at a temperature rising rate (5 ° C./min to 40 ° C./min) that is not higher than the temperature rising rate (45 ° C./min) at which the nucleation density is maximum Subsequently, the heat treatment is performed by raising the temperature from 550 ° C. to 730 ° C. at a temperature raising rate higher than 40 ° C./min. In the present embodiment, the temperature is increased to 400 ° C. at a temperature increase rate of 10 ° C./min, subsequently heated to 570 ° C. at a temperature increase rate of 100 ° C./min, heated at 570 ° C. for 2 hours, and further to room temperature. The temperature is lowered over 30 minutes. The temperature raising step in this case is as shown in the schematic diagram of FIG.₂  Is 400 ° C. and T1 is 570 ° C. Of course, as shown in FIG. 7A, the temperature may be increased from 550 ° C. to 730 ° C. at a constant temperature increase rate (5 ° C./min to 40 ° C./min) that is equal to or lower than the temperature increase rate at which the nucleation density is maximum.
[0099]
  This processing is performed by a baking apparatus composed of a plurality of in-line heating zones, and the temperature raising rate and the substrate temperature are controlled by the temperature setting of each heating zone and the substrate conveyance speed. The temperature rising rate at which the nucleation density is maximized depends on the film quality of the a-Si film, and thus needs to be optimized depending on the film quality of the a-Si film. By this heat treatment, the a-Si film 103 is crystallized to become a polycrystalline silicon film (p-Si film).
[0100]
  By the heating process up to 400 ° C., silicidation of nickel 104 added to the surface of the a-Si film occurs. In this embodiment, since the temperature is raised at a temperature rise rate or less that maximizes the nucleus generation density, the generation density of silicide is high, and each is a very small silicide. Further, by raising the temperature to 570 ° C., crystal nuclei are generated from the silicide, and columnar crystals grow. Since the generated crystal nuclei are very small and the amount of nickel in the crystal nuclei is small, columnar crystals grow from each crystal nuclei in one random direction in the plane, forming rod-like domains. Since the generation density of silicide is high, the generation density of rod-like domains is also high.
[0101]
  Further, when heated at 570 ° C. for 2 hours, the rod-like domain grows while being bent or branched, and crystallization is completed. Further, the width of the rod-like domain at this time is not less than 0.1 μm and not more than 1.5 μm, for example, not more than 1 μm. The nucleus generation density is 8 × 10^-2Piece / μm²  It is.
[0102]
  The amount of nickel used in this heating process is insufficient to crystallize the entire a-Si film 103. Further, since the heating time is short, crystal nuclei are not generated without a catalytic element, and an uncrystallized region where crystal growth does not reach remains a-Si. As a result, after this heat treatment, a minute amorphous region and a crystallized region are mixed. Specifically, the state is as shown in FIG. 8, and the area ratio of the a-Si region to the entire silicon film at this time is about 10%. The size of each a-Si region (black granular region in FIG. 8) is about 1 μm. The area ratio and size of the a-Si region are measured with an optical microscope.
[0103]
  As shown in FIG. 10B, the crystalline silicon film 106 is obtained by irradiating the laser beam 105 to promote the crystallinity of the silicon film. As the laser light, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nm) is used. The laser light irradiation condition is that the substrate is heated to 200 to 450 ° C., for example, 400 ° C. during irradiation, and the energy density is 250 to 450 mJ / cm.²  For example, 350 mJ / cm²  Irradiate with. The shape of the beam is a long shape, the beam size is formed on the substrate 101 so as to be 150 mm × 1 mm, and scanning is sequentially performed with a step width of 0.05 mm in a direction perpendicular to the long direction. Therefore, a total of 20 irradiations are performed at an arbitrary point on the silicon film 103.
[0104]
  By this irradiation, the amorphous region remaining in the crystalline silicon film 106 is preferentially melted, and the entire film is crystallized reflecting a good crystal component in the crystallized region. The purpose of laser irradiation is to improve the crystal, and the basic crystallinity (in-plane distribution of crystal orientation) is performed in an energy range that does not change.
[0105]
  The unnecessary portion of the polycrystalline silicon film 106 is removed and element isolation is performed to form an island-shaped crystalline silicon film 106a that becomes an active region (channel region 111, source 112 / drain 113 region) of the TFT (FIG. 9B).
[0106]
  Next, a silicon oxide film 107 having a thickness of 30 nm to 150 nm, for example, 100 nm is formed by plasma CVD as a gate insulating film so as to cover the island-like crystalline silicon film 106a. Further, a tantalum nitride film having a thickness of 50 nm to 200 nm, for example, 100 nm is formed by sputtering, and a tungsten film is continuously formed to a thickness of 300 nm to 500 nm, for example, 400 nm, followed by patterning to form the gate electrode 108. .
[0107]
  Subsequently, a low concentration impurity (phosphorus) 109 is implanted by ion doping using the gate electrode 108 as a mask (see FIG. 10C). Phosphine (PH) as doping gas³  ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 3 × 10.¹³cm^-2~ 3x10¹⁴cm^-2For example 1 × 10¹⁴cm^-2Do as. Further, in this doping process in which a high-concentration impurity (phosphorus) 110 is injected through a photoresist having a pattern 1 μm wider on the left and right sides (see FIG. 10D) than the gate electrode 108, phosphine (PH³  ), The acceleration voltage is 60 kV to 90 kV, for example, 80 kV, and the dose is 1 × 10¹⁵cm^-2~ 1x10¹⁶cm^-2For example 6 × 10¹⁵cm^-2Do as. In this step, the regions 114 and 115 into which only the low-concentration impurity 109 is implanted later become the LDD (Lightly Doped Drain) region of the TFT. The regions 112 and 113 into which the low-concentration impurity 109 and the high-concentration impurity 110 are respectively implanted become source / drain regions. The region 111 that is masked by the gate electrode 108 and is not implanted with impurities will later become a TFT channel region. This state is shown in FIGS. 9C and 10D.
[0108]
  Then, activation of the ion-implanted impurity and improvement of crystallinity deteriorated by introducing the impurity are performed by heat treatment at 450 to 600 ° C., for example, 550 ° C. for 1 to 10 hours, for example, 4 hours. Since phosphorus has an effect of attracting nickel, this heat treatment diffuses nickel in the region 111 where phosphorus is not implanted (later TFT channel region), and the region 114 where phosphorus is implanted at a high concentration. 115. If nickel, particularly nickel silicide, is present in the channel region, it becomes a leak source and causes an increase in the off-current of the TFT, but this heat treatment causes nickel to diffuse from the channel region and move to the source / drain region. Nickel can be gettered from the channel region. Therefore, an increase in the off current of the TFT can be suppressed. The sheet resistance of the N-type impurity (phosphorus) regions 112 and 113 is 200 Ω / cm.²  ~ 800Ω / cm²  It is.
[0109]
  Subsequently, a silicon oxide film or a silicon nitride film having a thickness of about 800 nm is formed by a plasma CVD method, and an interlayer insulating film 116 is formed. Contact holes are formed in the interlayer insulating film 116, and a source electrode wiring 117 of the TFT is formed by a metal material film, for example, a three-layer film of titanium, aluminum, and titanium. Finally, annealing is performed at 400 ° C. for 60 minutes in a nitrogen atmosphere.
[0110]
  Since the TFT of this embodiment is an element that switches the pixel electrode, the drain wiring is provided with a pixel electrode 118 such as a transparent electrode (for example, ITO). Through the above steps, the TFT 119 shown in FIGS. 9D and 10E is completed. In order to protect the TFT 119, a protective film made of a silicon nitride film or the like may be formed on the TFT 119 as necessary.
[0111]
  (Embodiment 2)
  In the present embodiment, a process of forming a CMOS structure circuit in which an N-type TFT and a P-type TFT are complementarily formed on a glass substrate will be described. This CMOS structure circuit is used for an active matrix liquid crystal peripheral circuit and a general thin film integrated circuit.
[0112]
  FIG. 11 is a plan view of the TFT of this embodiment. 12A to 12D and FIGS. 13A and 13B are cross-sectional views taken along line A-A ′ of FIG. 11, and schematically show a manufacturing process of the TFT of this embodiment. The process proceeds in the order of FIGS. 12A to 12D and FIGS. 13A and 13B.
[0113]
  First, as shown in FIG. 12A, a silicon oxide film 202 is formed on a glass substrate (Corning 1737) 201 as a base coat film (BC film) at a substrate temperature of 430 ° C. by a plasma CVD method at a thickness of 100 nm to 400 nm, for example, 300 nm. Then, an intrinsic (I-type) amorphous silicon film (a-Si film) 203 is formed to a thickness of 25 nm to 80 nm, for example, 40 nm at a substrate temperature of 430 ° C. This is treated with 0.5% hydrofluoric acid for 30 seconds to remove the natural oxide film on the surface, and the surface of the a-Si film 103 is further treated with ozone water to improve wettability.
[0114]
  As shown in FIG. 12A, a surface concentration of a solution containing nickel 204 on the a-Si film 203 is 1 × 10 5 by spin coating.¹²atoms / cm²  ~ 1x10¹⁴atoms / cm²  For example 5 × 10¹²atoms / cm²  Add to be. The surface concentration is a result of measurement with a total reflection X-ray fluorescence analyzer (TRXRF). Water is used as the solvent, and nickel acetate is used as the solute. Since nickel acetate is very soluble in water, a nickel solution having a stable concentration can be prepared. Further, it can be added uniformly on the a-Si film 203. The amount of nickel added can be controlled by the concentration of the solution (FIG. 12A). The concentration of the catalytic element in the a-Si film 103 is, for example, 5 × 10¹⁷atoms / cm³  It is.
[0115]
  Next, in an inert atmosphere, it is heated to 300 ° C. to 550 ° C. at a temperature rising rate (5 to 40 ° C./min) that is equal to or lower than the temperature rising rate (45 ° C./min) at which the nucleation density is maximized. Heat treatment is performed by raising the temperature from 550 ° C. to 730 ° C. at a temperature elevation rate of 30 ° C./min or more. In the present embodiment, the temperature is increased to 400 ° C. at a temperature increase rate of 10 ° C./min, and subsequently heated to 570 ° C. at a temperature increase rate of 100 ° C./min, and further to 670 ° C. at a temperature increase rate of 300 ° C./min. Raise the temperature. The temperature is lowered to 600 ° C. over 14 minutes, and further to room temperature over about 30 minutes. The temperature raising process in this case is as shown in the schematic diagram of FIG.₂  Is 400 ° C, T₁  Is 570 ° C, T₃  Is 670 ° C.
[0116]
  This process was performed with an RTA apparatus because it was necessary to control the heating rate in a wide range. The RTA apparatus is an inline type, and includes a heating zone by a plurality of IR (infrared) heaters and a heating zone by lamp heating by a halogen lamp, a xenon lamp or the like. The heating step for raising the temperature to 400 ° C. at a heating rate of 10 ° C./min, and the subsequent heating step for raising the temperature to 570 ° C. at a heating rate of 100 ° C./min are performed in the heating zone using an IR heater, respectively. The temperature raising step for raising the temperature to 670 ° C. at 300 ° C./min is performed in a heating zone by lamp heating. The temperature increase rate and the substrate temperature of this heat treatment were controlled by the temperature setting of each zone, the substrate transport speed, and the lamp power. In this embodiment, the temperature is raised to 670 ° C., but since the heating time is as short as several tens of seconds, even an inexpensive glass substrate having a low heat resistance temperature is processed at a temperature higher than the strain point of the glass substrate. Is possible.
[0117]
  The temperature rising rate at which the nucleation density is maximized depends on the film quality of the a-Si film, and thus needs to be optimized depending on the film quality of the a-Si film. By this heat treatment, the a-Si film 203 is crystallized to become a polycrystalline silicon film (p-Si film).
[0118]
  By the heating process up to 400 ° C., silicidation of nickel 204 added to the surface of the a-Si film occurs. In this embodiment, since the temperature is raised at a temperature rise rate or less that maximizes the nucleus generation density, the generation density of silicide is high, and each is a very small silicide. Further, by raising the temperature to 570 ° C., crystal nuclei are generated from the silicide, and columnar crystals grow. Since the generated crystal nuclei are very small and the amount of nickel in the crystal nuclei is small, columnar crystals grow from each crystal nuclei in one random direction in the plane, forming rod-like domains. Since the generation density of silicide is high, the generation density of rod-like domains is also high.
[0119]
  Until the temperature is lowered to 600 ° C., rod-like domains grow while branching, and crystallization is completed. Further, the width of the rod-like domain at this time is not less than 0.1 μm and not more than 1.5 μm, for example, not more than 1 μm. The nucleation density is 9 × 10^-2Piece / μm²  It is.
[0120]
  The amount of nickel used in this heating step is insufficient to crystallize the entire a-Si film 203. Further, since the heating time is short, crystal nuclei are not generated without a catalytic element, and an uncrystallized region where crystal growth does not reach remains a-Si. As a result, after this heat treatment, a minute amorphous region and a crystallized region are mixed. Specifically, the state is as shown in FIG. 8, and the area ratio of the a-Si region to the entire silicon film at this time is about 10%. The size of each a-Si region (black granular region in FIG. 8) is about 1 μm. The area ratio and size of the a-Si region are measured with an optical microscope.
[0121]
  As shown in FIG. 12B, the crystalline silicon film 206 is obtained by irradiating the laser beam 205 to promote the crystallinity of the silicon film. As the laser light, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nm) is used. The laser light irradiation condition is that the substrate is heated to 200 ° C. to 450 ° C., for example, 400 ° C. during irradiation, and the energy density is 250 mJ / cm.²  ~ 450mJ / cm²  For example, 350 mJ / cm²  Irradiate with. The shape of the beam is a long shape, the beam size is formed on the substrate 101 so as to be 150 mm × 1 mm, and scanning is sequentially performed with a step width of 0.05 mm in a direction perpendicular to the long direction. Therefore, a total of 20 irradiations are performed at an arbitrary point on the silicon film 203.
[0122]
  By this irradiation, the amorphous region remaining in the crystalline silicon film 206 is preferentially melted, and the entire film is crystallized reflecting a good crystal component in the crystallized region. The purpose of laser irradiation is to improve the crystal, and the basic crystallinity (in-plane distribution of crystal orientation) is performed in an energy range that does not change.
[0123]
  Unnecessary portions of the polycrystalline silicon film 206 are removed and element isolation is performed to form an island-shaped crystalline silicon film 206a which becomes an active region (channel region 111, source 112 / drain 113 region) of the TFT.
[0124]
  Next, a silicon oxide film 207 having a thickness of 30 nm to 150 nm, for example, 100 nm, is formed by plasma CVD as a gate insulating film so as to cover the island-shaped crystalline silicon film 206a. Further, as shown in FIG. 12C, a low-concentration impurity (phosphorus) 208 is implanted by an ion doping method through a photoresist having an outer shape of a region to be a channel region later (see FIG. 12C). Phosphine (PH) as doping gas₃  ), The acceleration voltage is 60 kV to 90 kV, for example, 80 kV, and the dose amount is 3 × 10¹³cm^-2~ 3x10¹⁴cm^-2For example 1 × 10¹⁴cm^-2Do as.
[0125]
  Further, as shown in FIG. 12D, a tantalum nitride film having a thickness of 50 nm to 200 nm, for example, 100 nm is formed by sputtering, and a tungsten film is continuously formed to a thickness of 300 nm to 500 nm, for example, 400 nm. The gate electrode 209 is formed by patterning using a pattern that is 1 μm wider on the left and right sides (see FIGS. 12C and 12D) than the region where the low concentration impurity is implanted.
[0126]
  A high concentration impurity (phosphorus) 210 is implanted using the gate electrode 209 as a mask. In this doping step, phosphine (PH₃  ), The acceleration voltage is 60 kV to 90 kV, for example, 80 kV, and the dose is 1 × 10¹⁵cm^-2~ 1x10¹⁶cm^-2For example 6 × 10¹⁵cm^-2Do as. In this step, the regions 214 and 215 into which only the low-concentration impurities 210 are implanted later become the LDD regions of the TFT. Since the regions 214 and 215 are located so as to overlap with the gate electrode 209, the subsequent TFT has a GOLDD (Gate Overrapped Lightly Doped Drain) structure.
[0127]
  The regions 212n and 213n into which the low-concentration impurity 208 and the high-concentration impurity 210 are respectively implanted become source / drain regions. The region 211n masked by the gate electrode 209 and not implanted with impurities will later become a channel region of the N-type TFT.
[0128]
  As shown in FIG. 13A, the photoresist is patterned, and impurities (boron) 216 are implanted into predetermined regions 214p and 215p of the island-like crystalline silicon film 206a by ion doping. Diborane (B₂H₆), The acceleration voltage is 60 kV to 90 kV, for example, 80 kV, and the dose amount is 3 × 10¹⁵cm^-2~ 2x10¹⁶cm^-2For example 1 × 10¹⁶cm^-2Do as. Phosphorus and boron are implanted into the regions 212p and 213p, respectively, but since the amount of boron implantation is larger, the regions 212p and 213p become P-type source / drain regions. Further, the region 211p in which the impurity (boron) 216 is not implanted becomes a channel region of the P-type TFT later.
[0129]
  Thereafter, the heat treatment at 450 ° C. to 600 ° C. activates the implanted impurities and improves the crystallinity deteriorated by introducing the impurities. In this embodiment, heat treatment is performed at 600 ° C. for 4 hours. Since phosphorus has an effect of attracting nickel, this heat treatment diffuses nickel in the region 211 where phosphorus is not implanted (later TFT channel region), and the region 212n where phosphorus is implanted at a high concentration. Collected at 212p, 213n and 213p. If nickel, particularly nickel silicide, is present in the channel region, it becomes a leak source and causes an increase in the off-current of the TFT, but this heat treatment causes nickel to diffuse from the channel region and move to the source / drain region. Nickel can be gettered from the channel region. Therefore, an increase in the off current of the TFT can be suppressed. The sheet resistance of the source / drain regions 212n and 213n of the N-type TFT is 200Ω / cm.²  ~ 800Ω / cm²  The sheet resistance of the source / drain regions 212p and 213p of the P-type TFT is 600 Ω / cm²  ~ 1500Ω / cm²  It is.
[0130]
  Subsequently, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed by a plasma CVD method, and an interlayer insulating film 217 is formed. Contact holes are formed in the interlayer insulating film 217, and source electrode wirings 218, 219 and 220 of the TFT are formed of a metal material film, for example, a three-layer film of titanium, aluminum and titanium. Finally, annealing is performed at 400 ° C. for 60 minutes in a nitrogen atmosphere of 1 atm.
[0131]
  Through the above steps, the N-channel TFT 221 and the P-channel TFT 222 shown in FIGS. 11 and 13B are completed. In order to protect the TFTs 221 and 222, a protective film made of a silicon nitride film or the like may be formed on the TFTs 221 and 222 as necessary.
[0132]
  In the above-described embodiment, the catalytic element is added on the amorphous silicon film. However, the catalytic element may be introduced on the glass substrate or the base film, and the amorphous silicon film may be formed thereon. Crystal growth in this case occurs from the lower surface of the amorphous silicon film.
[0133]
【The invention's effect】
  In the polycrystalline semiconductor thin film of the present invention, adjacent domains are continuous, and electrons or vacancies move between adjacent domains, so that the ON characteristics are high, the characteristic variation is small, and high mobility can be expected. When a plurality of switching elements are manufactured from the polycrystalline semiconductor thin film of the present invention, since the mobility is large, a semiconductor device having a high ON characteristic and a high integration degree can be obtained.
[0134]
  In addition, if the width of the TFT channel region is larger than the width of the rod-like domain, a plurality of rod-like domains exist in the channel region. Therefore, the TFT characteristics are averaged, and there is little variation in rising characteristics. A device is obtained.
[0135]
  Furthermore, a liquid crystal display device using the semiconductor device of the present invention as a switching element can obtain a clear image in which occurrence of display spots is suppressed.
[0136]
  According to the method for producing a polycrystalline semiconductor thin film of the present invention, the polycrystalline semiconductor thin film of the present invention can be produced by a simple method with a high yield.
[Brief description of the drawings]
FIG. 1 is a schematic diagram for explaining crystal growth of a polycrystalline semiconductor thin film according to the present invention. FIG. 1A shows a stage in the process of growth, and FIG. 1B shows a stage after the growth is completed.
FIG. 2 is an optical micrograph of a rod-like domain in an initial crystal growth stage.
FIG. 3A is an SEM photograph after a polycrystalline semiconductor thin film has been subjected to a revealing etching treatment.
FIG. 3B is an image photograph showing the result of measuring the in-plane distribution of crystal orientation in a polycrystalline semiconductor thin film by an EBSP method on a display.
FIG. 4A is an image photograph showing, as a line, portions where crystal orientation angles differ by 2 ° or more between adjacent measurement points in FIG. 3B.
FIG. 4B is an image photograph in which FIG. 3B and FIG. 4A are superimposed.
FIG. 4C is an image photograph in which a portion where the angle difference of crystal orientation is 2 ° or more and less than 5 ° is shown by light dots in FIG. 4B and a portion where the angle difference of crystal orientation is 5 ° or more is shown by dark dots.
FIG. 5 is a graph showing the relationship between the rate of temperature rise during crystallization annealing and the crystal nucleus generation density.
FIG. 6 is an optical micrograph of a crystal nucleus generation state at a temperature rising rate of about 50 ° C./min.
FIG. 7 is a graph showing a temperature increase rate in a crystal nucleus formation step and a crystal growth step.
FIG. 8 is a photomicrograph of the surface of a polycrystalline silicon film on which crystals have been grown by raising the temperature to 550 ° C. at a rate of temperature increase of 10 ° C./min.
9 is a plan view schematically showing a manufacturing process of the pixel TFT of Embodiment 1. FIG.
10 is a cross-sectional view schematically showing a manufacturing process of one pixel TFT of Embodiment 1. FIG.
11 is a plan view of a TFT according to Embodiment 2. FIG.
12 is a cross-sectional view taken along line A-A ′ of FIG. 11 and schematically shows a manufacturing process of the TFT of Embodiment 2. FIG.
13 is a cross-sectional view taken along line A-A ′ of FIG. 11 and schematically shows a manufacturing process of the TFT according to the second embodiment.
14A and 14B are schematic diagrams for explaining crystal growth by the method disclosed in Japanese Patent Laid-Open No. 9-312404. FIG. 14A shows a stage in the middle of growth, and FIG. 14B shows a stage after the growth is completed. Yes.
FIG. 15 is an optical micrograph after the crystal silicon film manufactured by the method disclosed in Japanese Patent Application Laid-Open No. 9-312404 has been subjected to a revealing etching process.
FIG. 16A is an image photograph in which a result obtained by measuring an in-plane distribution of crystal orientation in a crystalline silicon film by an EBSP method is displayed on a display.
FIG. 16B is an image photograph showing, as a line, portions where crystal orientation angles differ by 10 ° or more between adjacent measurement points in FIG. 16A.
FIG. 16C is an image photograph showing an in-plane distribution of crystal orientations when a crystal having a crystal orientation angle difference of 5 ° or less is regarded as one crystal in FIG. 16B.
[Explanation of symbols]
101, 201 glass substrate
102, 202 Base coat film
103, 203 Amorphous silicon film
104, 204 Nickel (catalytic element)
105, 205 Laser light
106, 206 Polycrystalline silicon film
107, 207 Gate insulation film
108, 209 Gate electrode
109, 208 Impurity (phosphorus)
110, 210 Impurity (phosphorus)
111, 211n, 211p channel region
112, 212n, 212p source region
113, 213n, 213p drain region
114, 115, 214, 215 LDD region
216 Impurities (boron)
116, 217 Interlayer insulating film
117 Source electrode
118 pixel electrode
218, 219, 220 Electrode / Wiring
119 pixel TFT
221 N-channel TFT
222 P-channel TFT

Claims (23)

Each is composed of a plurality of columnar silicon crystals, and includes a plurality of domains bent or branched in the same plane,
In the plurality of domains, there is a region where the difference in crystal orientation angle between adjacent domains is less than 10 ° , and the domains are grown from one crystal nucleus generated from a compound formed from silicon and nickel . A polycrystalline semiconductor thin film that is an assembly of columnar crystals.   The polycrystalline semiconductor thin film according to claim 1, wherein a width of the domain is 0.1 μm or more and 1.5 μm or less. Between before Symbol 100 ° C. temperature lower than the formation temperature of the compound to the generation temperature of said compound, processes the number of occurrences of the crystal nuclei to heat the silicon and the nickel in the following heating rate heating rate which maximizes The polycrystalline semiconductor thin film according to claim 1, wherein the crystal nucleus is formed by a process including at least. The polycrystalline semiconductor thin film according to claim 3, wherein the generation density of the crystal nuclei is greater than 0.5 × 10 ⁻² pieces / μm ² . 4. The polycrystalline semiconductor thin film according to claim 3, wherein the nickel concentration is in the range of 1 × 10 ¹⁶ atoms / cm ^{3 to} 1 × 10 ¹⁸ atoms / cm ³ .   A semiconductor device in which a plurality of switching elements are formed from the polycrystalline semiconductor thin film according to claim 1.   The semiconductor device according to claim 6, wherein the switching element is a thin film transistor, a width of a channel region of the thin film transistor is larger than a width of the domain, and a plurality of the domains exist in the channel region.   A liquid crystal display device comprising the semiconductor device according to claim 6. Forming a thin film of amorphous silicon on the substrate; introducing nickel into the thin film; forming a compound of the silicon and nickel; generating crystal nuclei from the compound; A method for producing a polycrystalline semiconductor thin film having at least a step of growing a crystal using a crystal nucleus as a nucleus,
The crystal nucleus generation step includes the step of heating the silicon at a temperature increase rate equal to or lower than a temperature increase rate at which the number of crystal nuclei generated is maximum between a temperature lower than the compound formation temperature by 100 ° C. and the compound generation temperature. And a method for producing a polycrystalline semiconductor thin film, comprising at least a step of heating the nickel.   The method for producing a polycrystalline semiconductor thin film according to claim 9, wherein the crystal growth step is a step of heating the silicon and the crystal nuclei at a higher temperature rising rate than the step of generating the crystal nuclei.   The method for producing a polycrystalline semiconductor thin film according to claim 9, wherein the crystal nucleus generation step is a step of heating to a temperature range of 300 ° C. or higher and 550 ° C. or lower.   The method for producing a polycrystalline semiconductor thin film according to claim 9, wherein the crystal growth step is a step of heating to a temperature range of 550 ° C. or higher and 730 ° C. or lower.   The method for producing a polycrystalline semiconductor thin film according to claim 9, wherein the crystal growth step is performed by an RTA (rapid thermal annealing) process. In the nickel introduction step, the nickel is introduced into the surface of the thin film or the substrate so that the surface concentration is in the range of 1 × 10 ¹² atoms / cm ^{2 to} 1 × 10 ¹⁴ atoms / cm ² . The method for producing a polycrystalline semiconductor thin film according to claim 9.   The method for producing a polycrystalline semiconductor thin film according to claim 9, wherein the nickel introducing step includes a step of applying a solution containing nickel onto the thin film by a spin coating method.   The method for producing a polycrystalline semiconductor thin film according to claim 15, wherein the solution containing nickel contains at least one selected from the group consisting of water, methanol, ethanol, n-propanol, i-propanol, and acetone.   The method for producing a polycrystalline semiconductor thin film according to claim 15, wherein the solution containing nickel contains nickel acetate.   The method for producing a polycrystalline semiconductor thin film according to claim 9, wherein the nickel introduction step is performed by a DC sputtering method.   The method for producing a polycrystalline semiconductor thin film according to claim 9, wherein the polycrystalline semiconductor thin film crystallized by the crystal growth step includes a minute amorphous region.   The method for producing a polycrystalline semiconductor thin film according to claim 19, comprising a step of performing intense light irradiation on the minute amorphous region. 21. The polycrystalline semiconductor thin film according to claim 20, wherein an excimer laser beam having a wavelength of 400 nm or less is used as the intense light, and irradiation is performed within an energy density range of 200 mJ / cm ² or more and 450 mJ / cm ² or less on the thin film surface. Production method.   The method for producing a polycrystalline semiconductor thin film according to claim 9, further comprising a step of performing a thermal oxidation treatment after the crystal growth step. The method for producing a polycrystalline semiconductor thin film according to claim 9, wherein the generation density of the crystal nuclei is greater than 0.5 × 10 ⁻² pieces / μm ² .

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