JP4028574B2 - LSI testability design method - Google Patents

Description

  The present invention relates to testability design for integrated circuits including logic gates.

  With recent advances in semiconductor integrated circuit technology, the number of elements (logic gates) included in LSIs (Large Scale Integrated Circuits) has increased, and along with this, how efficiently LSI testing has become a problem. . There is a testability design as a method for solving this problem. A typical one is a scan path design using a scan path method (see, for example, Patent Document 1).

  In the scan path method, all or a part of flip-flops included in an LSI are replaced with test flip-flops (hereinafter referred to as “scan flip-flops”), and these are connected serially to form a scan path ( This is called “insert scan path”). Here, the scan flip-flop generally has a test enable terminal for setting a test mode, a scan-in terminal for inputting scan data, a scan-out terminal for outputting scan data, and the like. The scan-in terminal of the first scan flip-flop is connected to the external input terminal of the LSI, and the scan-out terminal of the last scan flip-flop is connected to the external output terminal of the LSI. Then, the clock of each scan flip-flop is controlled from the outside to operate as a shift register. At this time, test data is given through the external input terminal, and the values stored in each scan flip-flop are sequentially taken out through the external output terminal, thereby testing the combinational circuit connected to each scan flip-flop.

  There are some basic design rules for design for testability (scan path design) using such a scan path method. For example, design rules such as 1) all flip-flop clocks can be controlled from an external port, 2) asynchronous reset / set can be controlled from an external port, and 3) no combinational circuit feedback is included. is there.

Therefore, after performing design rule inspection on the target circuit before performing scan path design, if scan path design is possible, scan path insertion is performed and automatic test pattern generation (ATPG: Automatic Test Pattern Generator) )I do. In the test pattern automatic generation, a test pattern and a fault detection rate indicating the degree of detection of stuck-at faults by the test pattern are output. Then, check the failure detection rate, and if the failure detection rate is insufficient, correct the circuit and increase / decrease the scan rate, then check the testability design rule again, insert the scan path, and test pattern Generate automatically. The above process is repeated until a sufficient failure detection rate is obtained by automatic test pattern generation.
Japanese Patent Laid-Open No. 5-6409

  As described above, conventionally, in order to obtain the failure detection rate, rule inspection for easy test design, scan path insertion, calculation of failure detection rate by automatic test pattern generation (ATPG), increase / decrease of scan rate and circuit correction Each treatment had to be repeated.

  In this case, in the scan path method, particularly in the partial scan in which a part of the flip-flops in the circuit is replaced with the scan flip, the scan time insertion and calculation of the failure detection rate by ATPG are repeated, so that the design time becomes long. There is.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a testability design method that shortens the design period of an LSI.

A testability design method according to the present invention includes a step of designing a scan path for a circuit including a logic gate, and a step of generating a test pattern by inserting the scan path. A method executed by a computer. The computer includes a stack structure memory having a last-in first-out function and an arithmetic means. The LSI testability design method includes a step of estimating a failure detection rate based on a test pattern before inserting a scan path. In the step of estimating the failure detection rate, the calculation means stores a pointer indicating the logic gate to be visited , and stores only the pointer of the input terminal of the logic gate to which the output of the logic gate having the input terminal set first is connected. The logic gate sequentially visits the logic gate according to the pointer stored in the stack structure memory by the step of storing in the stack structure memory and the pointer stored in the stack structure memory, and performs the logic operation on each logic gate and sequentially obtains the logic operation result. Estimating a failure detection rate according to the test pattern.

  According to the present invention, the LSI design period can be shortened.

  Embodiments of a testability design rule inspection apparatus according to the present invention will be described below with reference to the accompanying drawings. The testability design rule inspection apparatus according to the present embodiment is an apparatus for inspecting a design rule when performing a scan path design for a semiconductor integrated circuit, and a test pattern failure generated by automatic test pattern generation (ATPG). Estimate the detection rate.

<Configuration of testability design rule inspection device>
FIG. 1 is a block diagram showing the configuration of the testability design rule inspection apparatus. The testability design rule inspection apparatus includes a data input unit 3 for inputting data, setting values, user operation information, and the like from the outside, and a DFT for inspecting general design rules (design constraints) when performing scan path design. A rule inspection unit 5, a failure detection rate calculation unit 10 that calculates a failure detection rate for a circuit, and a display control unit 20 that performs various displays such as a calculation result of the failure detection rate. The failure detection rate calculation unit 10 includes a net search unit 13 that performs a net search by propagating a logical value, and a set based on input / output terminals of logic gates that satisfy a specific condition in order to calculate the failure detection rate. A set generation unit 15 to be obtained and a failure detection rate calculation unit 17 for calculating a failure detection rate. Furthermore, the testability design rule inspection device includes a network structure database 50 and a collective database 60. Note that the testability design rule inspection apparatus of the present embodiment also has logic circuit information that is circuit information of a test target circuit described in Verilog-HDL or the like, although not shown.

  The testability design rule inspection device configured as described above includes a CPU that executes a predetermined program and realizes a predetermined function, a storage device such as a hard disk or ROM that stores programs and data, and a program executed by the CPU. It may be configured by hardware such as a loaded RAM, a display device, and an input device such as a keyboard and a mouse. In this case, the function of each block shown in FIG. 1 is realized by loading a predetermined program stored in an information recording medium such as a hard disk or ROM into the RAM and executing it by the CPU.

<Various databases>
The network structure database 50 includes logic gate information 51 that is information defining logic gates that constitute a circuit, and signal connection information 53 that is information defining connection relationships between logic gates. The logic gate information 51 includes the name of the logic gate, information on the input terminal group of the logic gate, information on the output terminal group of the logic gate, and information (operation opcode) indicating the operator of the logic gate. The signal connection information 53 includes the names of signal lines that connect the logic gates and information on the logic gate terminals that are connected to the signal lines.

  FIG. 2 shows an example in which the logic gate information 51 is configured using a C language structure. As shown in the figure, the logic gate information structure 100 includes a logic gate name 101, a pointer 103 to an output terminal list, and a pointer 105 to an input terminal list. The pointer 103 to the output terminal list stores the head address of the output terminal list. That is, the pointer 103 to the output terminal list stores the storage location (address) of the first output terminal name 103a. The output terminal names included in the output terminal list can be sequentially read out based on the address indicated by the pointer 103 to the output terminal list. Similarly, the pointer 105 to the input terminal list stores the head address of the input terminal list.

  Further, the logic gate information 51 has an operator structure 110 associated with the output terminal names 103a. The operator structure 110 includes an operation opcode 111 that stores an operator opcode indicating an operation, a first argument pointer 113 that stores an address of a first argument for the operation, and a second that stores an address of a second argument. It consists of an argument pointer 115. The operation opcode 111 stores an input terminal name in some cases.

  FIG. 3 shows a specific example of data in the logic gate information 51 using the structure. FIG. 3B shows an example of data stored in the logic gate information 51 for the AND gate shown in FIG. The logical gate name of the AND gate shown in FIG. 3A is “AND03”, has three input terminals whose terminal names are “I1”, “I2”, and “I3”, and the terminal name is “O1”. "Has one output terminal. That is, as shown in FIG. 3B, in the logic gate structure 100, “AND03” is stored in the logic gate name 101, and “O1” is stored in the output terminal name 103a indicated by the pointer 103 to the output terminal list. Is stored. In the operator structure 110, “&”, which is an operation code indicating an AND operation, is stored in the operation opcode 111, and the first address of the operator structure 110 b is stored in the first argument pointer 113, and the second argument pointer 115. Stores the start address of the operator structure 110c. The operation terminal 111b of the operator structure 110b stores the input terminal name “I1”. In the operator structure 110c, “&” which is an operation code indicating an AND operation is stored in the operation opcode 111c, the first address of the operator structure 110d is stored in the first argument pointer 113c, and the second argument pointer 115c is stored in the second argument pointer 115c. The head address of the operator structure 110e is stored. The input terminal name “I2” is stored in the operation opcode 111d of the operator structure 110d. The input terminal name “I3” is stored in the operation opcode 111e of the operator structure 110e. The input terminal name “I1” is stored in the address area 105a indicated by the pointer 105 to the input terminal list. Thereafter, the input terminal names “I2” and “I3” are sequentially stored in a predetermined area of the input terminal list. In the figure, “null” indicates that no data is stored, and the output terminal list and the input terminal list indicate the end of data.

  FIG. 4 shows an example in which the signal connection information 53 is configured using a C language structure. As shown in the figure, the signal connection information structure 200 includes a signal line name 201, a fan-in pointer 203, and a fan-out list pointer 205. The fan-in pointer 203 stores the address of the storage area in which the output terminal name of the logic gate connected to the input side of this signal line is stored. The fan-out list pointer 205 stores the head address of the fan-out list. The fan-out list is made up of pointers 205a, 205b. Pointers 205a, 205b,... Store addresses of storage areas for input terminal names of logic gates connected to the output side with respect to the signal lines.

  FIG. 5 is a diagram showing a specific example of data in the signal connection information 53 using the structure. FIG. 5B shows an example of data stored in the signal connection information 53 for the circuit shown in FIG. FIG. 5A shows an example in which the output of the AND gate (AND03) is connected to the inverter (INV01) and the AND gate (AND04) via the signal line (NET01). In this example, in the signal connection information structure 200, “NET01” is stored in the signal line name 201, and the address of the output terminal “O1” is stored in the pointer 203 to the fan-in. The fan-out list pointer 205 stores the head address of the fan-out list, that is, the address of the pointer 205a. The address of the input terminal “I4” is stored in the pointer 205a, and the address of the input terminal “I5” is stored in the pointer 205b. The pointer 205c stores “null” indicating the end of the fan-out list.

  The set database 60 includes a set UT based on untestable terminals among logic gate terminals, a set UC based on terminals that cannot be controlled from the outside during testing, and logic gate terminals. It consists of a set UO based on terminals that cannot be observed from the outside during testing. FIG. 6A shows an example in which the collective database 60 is configured using a C language structure. The aggregate structure 300 includes an aggregate name 301 and a pointer 303 to a terminal list. The terminal list pointer 303 stores the head address of the terminal list, that is, the address of the pointer 303a. The terminal list includes pointers 303a... Indicating storage areas in which terminal names of terminals included in the set are stored. FIG. 6B shows an example of data storage.

<Operation of the testability test rule inspection device>
The operation of the testability design rule inspection apparatus configured as described above will be described.

  The testability design rule inspection device of this embodiment performs a net inspection by propagating a predetermined logical value when inspecting a testability design rule, thereby detecting a failure detection rate of a test pattern generated by ATPG. Estimate. Before describing the overall operation of the testability design rule inspection apparatus, the net search process will be described first.

<Net search processing>
FIG. 7 is a flowchart showing the net search process of the testability design rule inspection device. In the net search process, logic gates are sequentially visited in the depth direction, and logic operations corresponding to the operation opcodes are performed at the visited logic gates. This process is controlled by the net search unit 13.

  As shown in the figure, first, initial conditions are set to start a net search. That is, an input terminal for starting a net search and a logical value to be propagated are input via the data input unit 3 (S101). Next, a pointer indicating the storage location of the input terminal that has been input is pushed to the stack structure memory (S102). Here, the stack structure memory is generally a memory that realizes a last-in first-out function (LIFO). An operation for storing data in the stack structure memory is called a push, and an operation for taking out data from the stack structure memory is called a pop. . The stack structure memory stores a pointer to the input terminal of the logic gate to be visited.

  Thereafter, the logic gate is visited according to the pointer stored in the stack structure memory, and the logic operation is performed according to the logic gate.

  That is, the address of the input terminal of the logic gate is popped from the stack structure memory (S103). It is determined whether or not an address can be popped from the stack structure memory (S104). When the address cannot be popped from the stack structure memory, that is, when the stack structure memory is empty, the net search process is terminated. When the address can be popped, the logic gate information is referred to, the address of the logic gate is obtained from the address of the input terminal (S105), and the address of the output terminal of the logic gate is obtained (S106). It is determined whether or not the output terminal address can be acquired (S107). When the address of the output terminal can be acquired, a logical operation is performed on the logical gate based on the operation opcode and the logical value (S108). The result of the logical operation is held in a predetermined storage area as a propagation result at the logical gate.

  Thereafter, all logic gates to be visited next to the currently visited logic gates are searched, and the addresses of the input terminals and the logic values to be propagated are set for them (S109). Details of this processing will be described later.

  When setting of the address of the input terminal of the logic gate to be visited and the logic value to be propagated (S109) is completed, the process returns to step S106. The above processing (S106 to S109) is repeated for all the output terminals for one logic gate, and then the process returns to step S103 to pop the address of the input terminal to be searched next from the stack structure memory. At this time, the stack structure memory stores the input terminal of the next logic gate to which the output of the logic gate having the input terminal set first is connected, and is advanced by one in the depth direction. . Thereafter, the above process is repeated to sequentially search in the depth direction.

  In the flowchart, when the end of the net is reached, the address of the input terminal is not newly pushed to the stack structure memory even if the next visited destination setting process (step S109) is entered. Thus, by popping the stack structure memory next time, it is possible to continuously perform a net search for a logic gate connected to another branch.

  The next visit destination setting process in step S109 will be described with reference to the flowchart shown in FIG.

  First, with reference to the signal line connection information, the address of the input terminal of the next logic gate to which the output terminal is connected is sequentially obtained based on the address of the currently visited output terminal (S111). The address of the input terminal is acquired by being sequentially designated by the address to the fan-out list of the signal line connection information. Thereafter, it is determined whether or not an address can be acquired (S112). When the address is acquired, the logical operation result (calculated in step S108) at the preceding logic gate is set as the logical value input to the input terminal (S113). Thereafter, the address of the next input terminal is pushed to the stack structure memory (S114), and the process returns to step S111. The above processing is repeated until the setting of the addresses and logic values of all input terminals for the output terminal of the currently visited logic gate is completed.

<Example of program for net search processing>
FIG. 9 shows an example of a program for realizing the net search process shown in the flowcharts of FIGS. This program is written based on C language grammar.

  In FIG. 9, a function depth_search () indicated by (a) is a function for performing a net search. The function depth_search () uses the stack structure memory, and searches the net while storing the address of the logic gate to be visited in the stack structure memory. In the function depth_search (), variables v, o_pin, and instance are pointers that store the values of the input terminal, output terminal, and logic gate addresses, respectively. The function culc_opr (a, b) shown in (b) refers to the operation opcode of the logic gate specified by the argument a, executes the logical operation using the value of the argument b, and returns the logical operation result. The function stuck_push (x) shown in (c) pushes the pointer specified by the argument x to the stack structure memory. The function stuck_pop () shown in (d) pops and returns a pointer from the stack structure memory. The function get_funout (x) shown in (e) returns the address of the input terminal of the logic gate connected to the logic gate (or output terminal) specified by the argument x. In this case, when there are a plurality of input terminals of the logic gate connected to the logic gate (or output terminal) specified by the argument x, the addresses of these input terminals are returned sequentially each time the function is called. For depth_search (), the pointer i_pin of the input terminal of the logic gate for starting the net search and the initial value val of the logic value are passed as arguments.

  In the program shown in FIG. 9, statements (1) and (2) correspond to steps S101 and S102. Statement (3) corresponds to steps S103 and S104. Statement (4) corresponds to step S105. Statement (5) corresponds to steps S106 and S107. Statement (6) corresponds to step S108. Statement (7) corresponds to steps S111 and S112. Statement (8) corresponds to step S113. Statement (9) corresponds to step S114. In terms of the program loop, the loops of statements (3) to (12) correspond to the loops of steps S103 to S109. The loop of statements (5) to (11) corresponds to the loop of steps S106 to S109. The loop of statements (7) to (10) corresponds to the loop of step S109, that is, steps S111 to S114.

<Main flow>
The overall operation of the testability design rule inspection apparatus will be described below with reference to the flowchart of FIG.

  In the testability design rule inspection device, when an operation start operation is input in the data input unit 3, the DFT rule inspection unit 5 refers to the logic circuit information of the test target circuit described in Verilog-HDL, A general design rule in the scan campus design is inspected (S1). As design rules in general scan path design, for example, the following items are inspected. That is, a) whether the clock of the flip-flop to be scanned and the set / reset terminal can be controlled from the outside, b) whether or not the flip-flop to be scanned has a corresponding scan flip-flop, etc. The Thereafter, the inspection result is determined (S2), and if the constraints for scan path design are satisfied, the failure detection rate calculation unit 10 performs a predetermined net search process to calculate the failure detection rate (S3). Finally, the display control unit 20 displays the design constraint inspection result, failure detection rate, net search processing result, and the like (S4).

<Failure detection rate calculation process>
Hereinafter, the calculation of the failure detection rate (step S3) will be described with reference to the flowchart of FIG. As described above, this process is controlled by the failure detection rate calculation unit 10.

  In FIG. 11, first, the data input unit 3 inputs a constraint for test pattern automatic generation (ATPG), that is, a signal for setting a test mode, and an initial value of a logical value to be propagated (S11). . Thereafter, the net search unit 13 of the failure detection rate calculation unit 10 propagates the input logic value to each logic gate in the circuit (S12). Here, the propagation of a logical value means that a logical operation is performed by giving a predetermined logical value to one logic gate, and a logical operation is performed by giving the operation result to the next logic gate. The process of inputting a result to the next logic gate and performing a logical operation is repeated to obtain logical operation results sequentially. For example, in the example shown in FIG. 12A, the logical value propagates from 0 → 0 → 1 → 1 to the external input terminal 71, AND gate 72, inverter 73, and OR gate 74.

  Next, the set generation unit 15 obtains a set UT of logic gate terminals that cannot be tested because the value is fixed by the constraint in the test mode (S13). That is, the set generation unit 15 refers to the propagation result of the logical value, detects a logic gate terminal (node) whose terminal state is fixed to 0 or 1 by the constraint, and uses these logic gate terminals as a basis. Create a set UT. For example, when one of the input terminals of the AND gate becomes 0 due to the constraint, the output of the AND gate is fixed to 0, so that the output terminal is included in the set UT. The set UT stores an address (pointer) of a storage location of the logic gate terminal name in a database having a structure as shown in FIG.

  Next, the set generation unit 15 obtains a set UC that is a set of logic gate terminals that cannot be controlled in the test mode. That is, the net search unit 13 performs a net search by propagating a logical value X (the logical value X may be “0” or “1”) from the Q output of the flip-flop that is not subject to scan conversion. (S14). Thereafter, in the net search by the propagation of the logical value X, the logical gate terminals that propagate with the logical value X remaining as X are detected, and a set UC based on these logical gate terminals is created (S15).

  Here, propagation of the logical value X will be described with reference to FIG. In the figure, one input of the OR gate 84 is fixed to “0” by the constraint, and one input of the AND gate 85 is also fixed to “0” by the constraint. When a logical value X is propagated from such an external input terminal 81 to such a circuit, the output of the inverter 82 is “inverted value of X”, the output of the inverter 83 is “X”, and the output of the OR gate 84 is “ The output of the AND gate 85 becomes “0” at “X”. Therefore, the logical value X has propagated to the input / output terminals of the inverters 82 and 83, the other input terminal of the OR gate 84, and the other input terminal of the AND gate 85, and the other terminals have logical values. X will not propagate. The net search by the propagation of the logical value X is performed with reference to each logic gate information and signal connection information stored in the network structure database 50.

Returning to FIG. 11, the set generation unit 15 further obtains a set UO that is a set of logic gate terminals that cannot be observed in the test mode. That is, the set generation unit 15 temporarily creates a set UO of logic gate terminals not included in the sets UT and UC obtained in the above steps (S16). Thereafter, a net search by propagation of the logical value X is performed for each logical gate terminal in the temporary set UO (S17), and the logical gate that has reached the external output terminal or the D input of the scan conversion target flip-flop Terminals are detected, and these logic gate terminals are removed from the temporary set UO to create a final set UO (S18).

Finally, the failure detection rate calculation unit 17 sets the original numbers of the set UT, the set UC, and the set UO as ut, uc, uo, and the total number of previous terminals in the circuit, and detects the failure after the scan path is inserted. The rate is calculated using the following equation (S19).
Failure detection rate = (total-(ut + uc + uo)) / total * 100 (%)

  In this way, the testability design rule inspection apparatus obtains the failure detection rate after the scan path is inserted.

  As described above, the set UT is a group of logic gate terminals that are regarded as untestable because the logic value is fixed by the constraint for ATPG. The set UC is a logic gate terminal group that cannot be controlled by the combinational ATPG because it is controlled by the data output of flip-flops that are not subject to scan conversion, that is, flip-flops that are not scanned in the circuit after the scan path is inserted. The set UO is a flip-flop to be subjected to scan conversion, that is, a flip-flop scanned in a circuit after insertion of a scan path, or a logic gate terminal group that cannot be observed from an external output terminal. With a recent combinational ATPG, almost 100% of fault detectable patterns can be generated except for redundant circuits and feedback loop paths. In addition, if a logic circuit is synthesized with a recent logic synthesis tool, there is no redundant circuit. Therefore, from the number of terminals of all logic circuit gates in the circuit as described above, except for terminals that cannot be tested because they are fixed during testing, terminals that cannot be controlled during testing, and terminals that cannot be observed. By obtaining the detection rate, the failure detection rate by ATPG can be predicted.

<Display processing of net search results>
Next, the display process (step S4) of the result of the net search process will be described. This process is controlled by the display control unit 20 and causes the display device to display a list of terminal names belonging to the set UT, the set UC, and the set UO obtained in the process of calculating the failure detection rate. That is, for the terminals belonging to each of the set UT, the set UC, and the set UO, the terminal names are obtained by referring to the logic gate structure, and these terminal names are displayed on the display device. This allows the user to check untestable, uncontrollable, and unobservable locations on the display device, making it easy to identify circuit correction locations for ease of testing and to examine the scan rate. Can be improved.

  In the testability design rule inspection apparatus, the data input unit 3 may input not only the constraints for ATPG but also the circuit range designated by the user, that is, the logic gate range. At this time, the display control unit 20 displays the net search result for the network within the designated circuit range, that is, the propagation state of the logical value. That is, it displays how the logical value propagates in the designated circuit range. Thereby, the user can confirm the net search result, can quickly determine whether or not the result is a desired one, and can interactively process the change of the logical value to be propagated → confirmation → change. As a result, it is possible to quickly cope with circuit correction for facilitating the test, and the design efficiency can be improved.

  As described above, the test-enabling design rule inspection apparatus calculates the failure detection rate at the same time when the DFT rule is inspected. For this reason, in order to calculate the failure detection rate, it is necessary to repeat DFT rule inspection, scan path insertion, calculation of failure detection rate by automatic test pattern generation (ATPG), increase / decrease in scan rate, and circuit correction as in the past. Design efficiency can be improved.

  According to the testability design rule inspection apparatus of this embodiment, it is possible to predict a failure detection rate by automatic test pattern generation (ATPG) in testability design rule inspection. As a result, it is not necessary to repeat each process of rule inspection for easy test design, scan path insertion, calculation of fault detection rate by automatic test pattern generation, increase / decrease of scan rate, and circuit correction to obtain the fault detection rate Design efficiency can be improved.

  In addition, since the untestable part, the uncontrollable part, and the unobservable part are displayed, it is possible to easily identify the circuit correction part for the testability design and to examine the scan rate, and to improve the design efficiency.

  In addition, the result of the net search in the designated circuit range is displayed. For this reason, the user can confirm the logic propagation state in the desired range of the circuit, and can perform a scan path analysis in the test state. As a result, it is possible to easily specify the circuit correction location for the design for testability and to examine the scan rate, thereby improving the design efficiency.

  The present invention is applicable to a testability design for an integrated circuit including a logic gate.

1 is a block configuration diagram of a testability design rule inspection device according to the present invention. The figure which showed the structural example of the logic gate information comprised using the structure of C language. The figure which showed the specific example of the data stored in the logic gate information comprised using the structure of C language. The figure which showed the structural example of the signal connection information comprised using the structure of C language. The figure which showed the specific example of the data stored in the signal connection information comprised using the structure of C language. (A) The figure which showed the example of a structure of the set database comprised using the structure of C language, (b) The figure which showed the specific example of the data stored in the set database. The flowchart which shows the net search process of the testability design rule inspection apparatus which concerns on this invention. The flowchart which shows the setting process of the next visited place in the net search process of the testability design rule inspection apparatus which concerns on this invention. The figure which shows the example of a program which implement | achieves the net search process of the testability design rule inspection apparatus concerning this invention. The flowchart which shows the whole operation | movement of the testability design rule inspection apparatus which concerns on this invention. The flowchart which shows the failure detection rate calculation process of the testability design rule inspection apparatus which concerns on this invention. (A) The figure explaining propagation of the general logical value, (b) The figure explaining propagation of the logical value X.

Explanation of symbols

3 Data Input Unit 5 DFT Rule Checking Unit 10 Failure Rate Calculation Unit 13 Net Search Unit 15 Set Generation Unit 17 Failure Rate Calculation Unit 20 Display Control Unit 50 Network Structure Database 51 Logic Gate Information 53 Signal Connection Information 60 Set Database

Claims (1)

In an LSI testability design method executed by a computer, including a step of designing a scan path for a circuit including a logic gate, and a step of generating a test pattern by inserting the scan path.
The computer includes a stack structure memory having a last-in first-out function and an arithmetic means.
The LSI testability design method includes a step of estimating a failure detection rate by the test pattern before inserting the scan path,
The step of estimating the failure detection rate includes:
The arithmetic means stores the pointer indicating the logic gate to be visited in the stack structure memory in which only the pointer of the input terminal of the logic gate to which the output of the logic gate having the input terminal initially set is connected is stored. Steps,
The arithmetic means visits the logic gates sequentially according to the pointers stored in the stack structure memory, performs a logical operation on each logic gate, and sequentially obtains the logical operation results, thereby approximating the failure detection rate by the test pattern. Including the steps of
LSI testability design method.

Images