JP4029984B2 - TFT array substrate - Google Patents

Description

  The present invention relates to a TFT array substrate, and more particularly to improvement of a semiconductor pattern in a TFT array substrate in which TFTs are arranged in a matrix in a display area and used for a liquid crystal display device or the like.

  The liquid crystal display device includes a liquid crystal display panel that performs image display and a control circuit thereof. The liquid crystal display panel is configured by enclosing liquid crystal between a TFT array substrate and a color filter substrate. In the TFT array substrate, a large number of pixel electrodes are formed on an insulating transparent substrate made of glass or the like, and a thin film transistor (TFT) is formed for each pixel electrode. On the other hand, the color filter substrate placed opposite the TFT array substrate has a common electrode formed on an insulating transparent substrate made of glass or the like, and controls the alignment direction of liquid crystal molecules by the electric field between the pixel electrode and the common electrode. Image display.

  In addition, a large number of gate lines are formed on the TFT array substrate, and a large number of source lines are formed so as to cross these gate lines. Both the gate wiring and the source wiring are formed by patterning a metal layer made of Cr, Al, Mo or the like. However, the gate wiring and the source wiring are formed using the first metal layer formed on the glass substrate so that the gate wiring and the source wiring do not conduct at these intersections, while the gate wiring and the source wiring are formed on the first metal layer via an insulating film. A source wiring is formed using the second metal layer.

  The TFT includes a gate electrode made of a first metal layer, a source electrode and a drain electrode made of a second metal layer, and an insulating film and a semiconductor layer formed between the first metal layer and the second metal layer. The This TFT is on / off controlled based on the potential of the gate wiring. When the TFT is in the on state, the potential of the source wiring connected to the source electrode is written to the pixel electrode connected to the drain electrode.

In the TFT array substrate described above, the source wiring is easily disconnected at the intersection with the gate wiring. As a conventional method for preventing such disconnection of the source wiring, a technique for forming a semiconductor layer constituting the TFT under the source wiring is known (for example, Patent Document 1). In the case of a TFT array substrate in which an auxiliary capacitance wiring (Cs electrode) parallel to the gate wiring is formed using the first metal layer, the same is true at the intersection of the auxiliary capacitance wiring and the source wiring. Problems arise. For this reason, the semiconductor layer arranged under the source wiring is formed as a semiconductor wiring extended along the source wiring.
JP-A-11-242241

  The inventors have found that such a TFT array substrate is observed to be damaged due to static electricity in the semiconductor layer after the patterning process in the manufacturing process. FIG. 16 is a diagram showing an example of this state. This figure is an enlarged view of the lower end portion of the display area on the TFT array substrate, showing the end portion of the semiconductor wiring 14L extended along the source wiring (not shown) and its peripheral portion. Yes. The semiconductor wiring 14L traverses the display region in the vertical direction along the source wiring and intersects with the outermost gate wiring 11L (or auxiliary capacitance wiring 11C). For this reason, the terminal portion is disposed so as to protrude outward from the gate wiring 11L.

  In some cases, damage is caused from the terminal portion of the semiconductor wiring 14L to the intersection of the gate wiring 11L (or the auxiliary capacitance wiring 11C), and the insulating film at the intersection with the gate wiring 11L is damaged, resulting in dielectric breakdown. As described above, since the source wiring is formed on the intersection at a subsequent process, when the gate wiring 11L and the source wiring are short-circuited due to a defect in the insulating film, one linear defect is formed vertically and horizontally. There was a problem that occurred.

  One possible cause of such an insulating film defect is peeling charge that occurs when the TFT array substrate after the etching process is lifted from the lower electrode in a dry etching apparatus. That is, the charge generated by the peeling electrification flows from the tip of the protruding semiconductor wiring 14L through the side end of the semiconductor wiring 14L to the gate wiring 11L, whereby the side end of the semiconductor wiring 14L and the side end It is considered that the insulating film at the intersection of the gate line 11L is damaged.

  FIG. 17 is a diagram showing an example of the dry etching process. In the dry etching apparatus, the upper electrode 201 and the lower electrode 202 are disposed opposite to each other in the vacuum chamber 200 to generate plasma, and an etching process is performed. During the etching process, the TFT array substrate 100 is disposed on the lower electrode 202, and the region on the upper surface of the TFT array substrate 100 where no resist is formed is etched. After the etching process, the TFT array substrate 100 is lifted from the lower electrode 202 with the pins 203 in contact with the lower surface thereof, and the transfer arm 204 is inserted into the lower surface of the TFT array substrate 100 and carried out of the vacuum chamber 200.

  At the time of pin-up, the semiconductor wiring immediately after patterning is peeled and charged, and the charge damages the vicinity of the terminal portion of the semiconductor wiring that protrudes like an antenna, and damages the insulating film at the intersection with the first metal layer. it is conceivable that. In FIG. 16, the case where the gate wiring 11L is arranged on the outermost side has been described. However, in the case where the auxiliary capacitance wiring 11C is arranged outside the gate wiring 11L, at the intersection with the auxiliary capacitance wiring 11C. Insulating film defects occur. In this case, the storage capacitor line 11C and the source line are short-circuited, and a linear defect occurs.

  Further, in the subsequent manufacturing process, charges may be accumulated in the semiconductor wiring 14L due to static electricity, and the peeling charging in the above-described dry etching process is just one example. When charge is accumulated in the semiconductor wiring 14L, not only the case where the linear defect as described above is caused, but also the case where the TFT is broken to cause a point defect is conceivable.

  The present invention has been made in view of the above circumstances, and an object thereof is to improve the antistatic characteristics of semiconductor wiring and improve the manufacturing yield of a TFT array substrate. Another object of the present invention is to provide a high-quality TFT array substrate at a low cost.

The TFT array substrate according to the present invention includes a large number of gate lines made of a first metal layer, a second metal layer, a large number of source lines arranged so as to intersect the gate lines, and the first metal layer. A TFT composed of a gate electrode , a source electrode and a drain electrode made of the second metal layer, and an insulating film and a semiconductor layer formed between the first metal layer and the second metal layer; and the same as the semiconductor layer A series of layers , each disposed under the source wiring and extending along the source wiring, and the same layer as the semiconductor layer, and a series of two or more semiconductor wirings under the different source wiring A semiconductor connection portion is formed to form a semiconductor pattern and connect these semiconductor wirings . With such a configuration, the area of each semiconductor wiring can be increased without complicating the manufacturing process, and the occurrence of defects due to static electricity can be suppressed.

Further, the TFT array substrate according to the present invention is configured such that the semiconductor connection portion connects two or more semiconductor wirings under different source wirings outside the display region. With such a configuration, the area of the semiconductor wiring in the TFT array substrate can be increased without causing deterioration in display quality such as a reduction in aperture ratio.

Further, the TFT array substrate according to the present invention is configured such that the semiconductor connecting portion connects two or more semiconductor wirings under different source wirings on each of the opposite end sides of the display region.

In addition, the TFT array substrate according to the present invention is configured to extend along the source line across the display area. Further, the TFT array substrate according to the present invention is configured such that the semiconductor connecting portion connects two or more semiconductor wirings under different source wirings on each of the opposite end sides of the display region.

Further, the TFT array substrate according to the present invention is configured such that the semiconductor connecting portion connects adjacent semiconductor wirings in the display region. With such a configuration, semiconductor wirings can be connected in the display area.

In the TFT array substrate according to the present invention, the semiconductor connection portion is disposed on the gate wiring, extends along the gate wiring, and has a non-overlapping region with the gate wiring between the different source wirings. Configured as follows. With such a configuration, the semiconductor wiring can be connected in the display region without reducing the aperture ratio.

Further, TFT array substrate according to the present invention, the first consists of metal layers, is arranged parallel to the gate lines, a number of storage capacitor lines which are connected to each other, the semiconductor connecting portion, the auxiliary capacitor It is arranged on the wiring and is configured to extend along the auxiliary capacity wiring. With such a configuration, the semiconductor wiring can be connected in the display region without reducing the aperture ratio.

  According to the present invention, the area of each semiconductor wiring can be reduced without complicating the manufacturing process by forming a semiconductor connecting portion that connects two or more semiconductor wirings and these semiconductor wirings as a series of semiconductor patterns. It can be increased, and the occurrence of defects due to static electricity can be suppressed. Therefore, it is possible to improve the static electricity resistance of the semiconductor wiring and improve the manufacturing yield of the TFT array substrate. Further, it is possible to provide a high-quality TFT array substrate at low cost by increasing the area of the semiconductor wiring in the TFT array substrate without degrading the display quality.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration example of a liquid crystal display device including a TFT array substrate according to the present invention. In the figure, 100 is a TFT array substrate, 101 is a control substrate, 102 is a gate drive module, and 103 is a source drive module. Reference numeral 104 denotes a display area, 105 denotes a TFT, 11L denotes a gate wiring, and 15L denotes a source wiring, all of which are formed on the TFT array substrate 100.

  In the TFT array substrate 100, a large number of gate wirings 11L are formed in parallel, and a large number of source wirings 15L are formed in parallel so as to cross these gate wirings 11L. Further, a TFT 105 is formed at each intersection of the gate line 11L and the source line 15L, and a pixel electrode is connected to each TFT 105. A rectangular area in which these pixel electrodes are arranged is a display area 104, each gate line 11L is formed so as to cross the display area 104 in the left-right direction, and each source line 15L crosses the display area 104 in the vertical direction. It is formed as follows.

  The TFT 105 has a gate electrode and a source electrode connected to the gate wiring 11L and the source wiring 15L, respectively, and a drain electrode connected to the pixel electrode. Therefore, each TFT 105 is controlled to be turned on / off based on the potential of the gate wiring 11L, and the potential of the source wiring 15L at the time of turning on is written to the pixel electrode. The TFT array substrate 100 is bonded to a color filter substrate in which a common electrode and a color filter are formed on a glass substrate, and a liquid crystal is sealed in the gap to form a liquid crystal display panel. In FIG. The filter substrate is omitted.

  The control board 101 controls the gate driving module 102 and the source driving module 103 based on an image signal input from the outside to display an image. The gate drive module 102 is a flexible thin circuit called TCP (Tape Carrier Package) in which a gate driver circuit is formed on an insulating film, and drives the gate wiring 11L based on an output signal of the control board 101. ing. Similarly, the source driving module 103 is a TCP in which a source driver circuit is formed on an insulating film, and drives the source wiring 15 </ b> L based on an output signal of the control board 101.

  FIG. 2 is an enlarged plan view showing one pixel on the TFT array substrate 100. One pixel on the TFT array substrate 100 includes a TFT 105 and a pixel electrode 17 connected to the drain electrode 15 </ b> D of the TFT 105 via the contact hole 21. The pixel electrode 17 is surrounded by the gate line 11L and the source line 15L, and an auxiliary capacitance line 11C that crosses the pixel electrode 17 is formed.

  Under the source wiring 15L, a semiconductor wiring 14L extending along the source wiring 15L is formed. The width of the semiconductor wiring 14L is narrower than that of the source wiring 15L, is disposed so as to overlap with the source wiring 15L, and traverses the display area 104 in the vertical direction. The auxiliary capacitance line 11C is an electrode formed so as to cross the vicinity of the center of the pixel electrode 17 in order to increase the pixel capacitance. The auxiliary capacitance line 11C is arranged in parallel to the gate line 11L and intersects the source line 15L while displaying the display region 104. Is crossed horizontally.

  The TFT 105 is formed in the vicinity of the intersection of the gate line 11L and the source line 15L, and includes a source electrode 15S, a drain electrode 15D, a gate electrode 11G, and a TFT semiconductor portion 14T. The source electrode 15S has a pattern in which the source wiring 15L is branched to the TFT region. The gate electrode 11G is a part of the gate wiring 11L, and includes a wiring portion formed in the TFT region. The TFT semiconductor portion 14T has a pattern in which the semiconductor wiring 14L is branched to the TFT region.

  3A shows a cross-sectional view taken along the line AA in FIG. 2, and FIG. 3B shows a cross-sectional view taken along the line BB in FIG. The TFT 105 is a back channel TFT in which the gate electrode 11G is disposed below the TFT semiconductor portion 14T (insulating substrate 10 side).

  In the TFT region where the TFT 105 is formed, a gate electrode 11G is formed on the insulating substrate 10, and a TFT semiconductor portion 14T is formed on the gate electrode 11G via the insulating film 12. The source electrode 15S and the drain electrode 15D are formed on the TFT semiconductor portion 14T so as to face each other with the channel region 20 in between. Further, an interlayer insulating film 16 is formed on the source electrode 15S, the drain electrode 15D, and the channel region 20. A contact hole 21 is formed in the interlayer insulating film 16 on the drain electrode 15D, and the pixel electrode 17 is connected to the drain electrode 15D through the contact hole 21.

  The insulating substrate 10 is a transparent and insulating substrate made of glass or the like. The gate electrode 11G is formed by patterning a first metal layer made of Cr, Al, Mo or the like formed on the insulating substrate 10. The insulating film 12 is made of SiNx or the like that insulates the first metal layer from the upper layer. The TFT semiconductor portion 14T is formed of a semiconductor layer mainly composed of silicon Si or the like, and includes two layers, a non-doped layer formed on the insulating film 12 and a contact layer formed on the non-doped layer. In the channel region 20, the contact layer is removed by etching, leaving only the non-doped layer. The source electrode 15S and the drain electrode 15D are formed by patterning a second metal layer made of Cr, Al, Mo or the like formed on the TFT semiconductor portion 14T. The interlayer insulating film 16 is made of SiNx or the like that insulates the second metal layer from the upper layer.

  In the pixel electrode region, the pixel electrode 17 is formed on the insulating substrate 10 via the insulating film 12 and the interlayer insulating film 16. The pixel electrode 17 is a transparent electrode made of ITO (Indium Tin Oxide) or the like. The first metal layer is used for the auxiliary capacitance line 11C formed in a part of the pixel electrode region. That is, the auxiliary capacitance line 11C is formed on the insulating substrate 10 and faces the pixel electrode 17 with the insulating film 12 interposed therebetween. By holding the auxiliary capacitance line 11C at the reference potential, the pixel capacitance is increased. Yes.

  In the source wiring region where the source wiring 15L is formed, the semiconductor wiring 14L is formed on the insulating substrate 10 via the insulating film 12. A source wiring 15L having a width wider than that of the semiconductor wiring 14L is formed on the semiconductor wiring 14L, and an interlayer insulating film 16 is further formed on the source wiring 15L. The semiconductor layer is used for the semiconductor wiring 14L, and the second metal layer is used for the source wiring 15L.

  In the intersection region of the source wiring 15L and the gate wiring 11L, the gate wiring 11L made of the first metal layer is formed on the insulating substrate 10, and the semiconductor wiring 14L and the gate wiring 11L are interposed on the gate wiring 11L via the insulating film 12. A source line 15L is formed. Exactly in the same manner, in the intersecting region of the source wiring 15L and the auxiliary capacitance wiring 11C, the auxiliary capacitance wiring 11C made of the first metal layer is formed on the insulating substrate 10, and an insulating film is formed on the auxiliary capacitance wiring 11C. A semiconductor wiring 14 </ b> L and a source wiring 15 </ b> L are formed via 12.

  FIG. 4 is a plan view showing an example of the manufacturing process of the TFT array substrate 100 of FIG. 2, in which the TFT region and its periphery are shown. FIG. 5 is a sectional view showing an AA section in the manufacturing process. First, a first metal layer made of Cr, Al, Ti, Ta, Mo, W, Ni or the like is formed on the insulating substrate 10 by sputtering or vapor deposition. By patterning the first metal layer, the gate wiring 11L, the gate electrode 11G, and the auxiliary capacitance wiring 11C are formed (FIG. 5A).

Next, the insulating film 12, the non-doped layer, and the contact layer are successively formed by plasma CVD or the like (FIG. 5B). The insulating film 12 is made of silicon nitride SiNx, silicon oxide SiOx, or the like. The semiconductor layer is made of amorphous silicon, polycrystalline silicon or the like, and the contact layer is made of n ⁺ silicon obtained by doping the silicon layer with an n-type impurity such as phosphorus or arsenic. This semiconductor layer is patterned by dry etching to form a semiconductor wiring 14L and a TFT semiconductor portion 14T (FIGS. 4A and 5C).

  Next, a second metal layer made of Cr, Al, Ti, Ta, Mo, W, Ni, or the like is formed by sputtering or vapor deposition, and this second metal layer is patterned to form source wiring 15L, source Electrode 15S and drain electrode 15D are formed. Subsequently, the channel region 20 is etched using the source electrode 15S and the drain electrode 15D as a mask, and the contact layer is removed leaving the non-doped layer (FIGS. 4B and 5D).

  Next, an interlayer insulating film 16 made of silicon nitride SiNx, silicon oxide SiOx, organic polymer or the like is formed, and this insulating film 12 is patterned to form a contact hole 21 on the drain electrode 15D (FIG. 5E). )). Finally, a transparent conductive film made of ITO or the like is formed, and this transparent conductive film is patterned to form the pixel electrode 17 in the pixel electrode region including the contact hole 21 (FIGS. 4C and 5). (F)).

  FIG. 6 is a plan view showing a configuration example of a main part of the TFT array substrate 100 according to the first embodiment of the present invention, and shows a semiconductor pattern 140 formed on the insulating substrate 10. The semiconductor pattern 140 includes a large number of semiconductor wirings 14L and two semiconductor connection portions 14J that connect these semiconductor wirings 14L, and is simultaneously formed as an integrated shape by dry etching of the semiconductor layer.

  The semiconductor wiring 14L crosses the display area 104 vertically while intersecting with the gate wiring 11L and the auxiliary capacitance wiring 11C. The TFT semiconductor portion 14T branches off from the semiconductor wiring 14L at each intersection with the gate wiring 11L, but is omitted in FIG. The semiconductor connecting portion 14J is formed in the vicinity of two opposing sides (the upper end side and the lower end side in FIG. 6) of the display area 104 so as to be parallel to these end sides, and the terminal ends of all the semiconductor wirings 14L. Are connected outside the display area 104. Therefore, as illustrated, the semiconductor pattern 140 has a ladder shape.

  FIG. 7 shows an enlarged plan view of the area A1 (near the upper end side of the display area 104) in FIG. At the upper end of the TFT array substrate 100, a pad 17P to which the terminal of the source drive module 103 is connected is disposed. The pad 17P is formed of ITO or the like, and is connected to the source line 15L drawn from the display region 104 through the contact hole 22. On the other hand, the semiconductor wiring 14L led out from the display region 104 along the source wiring 15L is connected to each other by the semiconductor connecting portion 14J.

  FIG. 8 is an enlarged plan view of the area A2 (near the lower end side of the display area 104) in FIG. At the lower end portion of the TFT array substrate 100, the source line 15L drawn from the display area 104 is terminated. On the other hand, the semiconductor wiring 14L led out from the display region 104 along the source wiring 15L is connected to each other by the semiconductor connecting portion 14J.

  In the conventional TFT array substrate, the semiconductor wiring 14L is formed as an independent pattern. On the other hand, in the TFT array substrate according to the present embodiment, the semiconductor wiring 14L and the semiconductor connecting portion 14J are formed as a series of shape patterns, and two or more semiconductor wirings 14L are connected by the semiconductor connecting portion 14J. For this reason, since the area of each semiconductor wiring 14L can be increased and the potential of the semiconductor wiring 14L can be stabilized, the occurrence of defects due to static electricity can be suppressed. That is, in the dry etching process of the semiconductor layer or in the subsequent manufacturing process, if the semiconductor wiring 14L is charged and the charge amount is the same, damage caused by the discharge can be suppressed, and the TFT array The production yield of the substrate can be improved.

  In particular, in the present embodiment, since the semiconductor wiring 14L is connected outside the display region 104, it can be realized without reducing the aperture ratio of the TFT array substrate. In addition, the occurrence of defects can be effectively suppressed by connecting all the semiconductor wirings 14L. Therefore, the TFT array substrate can be provided inexpensively and stably without degrading the display quality of the liquid crystal display device.

  FIG. 9 is a view showing another configuration example of the main part of the TFT array substrate 100 according to the first embodiment of the present invention, and shows a semiconductor pattern 141 formed on the insulating substrate 10. As in the case of FIG. 6, all the semiconductor wirings 14 </ b> L are also connected by the semiconductor connecting portions 14 </ b> J formed in the display region 104 in the semiconductor pattern 141.

  Each semiconductor wiring 14L is connected to one adjacent semiconductor wiring 14L by the semiconductor connecting portion 14J and the other terminal connected to the other adjacent semiconductor wiring 14L. In other words, adjacent semiconductor wirings 14L are connected in series in order, and all the semiconductor wirings 14L are connected so as to form a so-called one-stroke writing, thereby forming a meandering pattern. Even when such a semiconductor pattern 141 is used, all the semiconductor wirings 14L can be connected outside the display region 104, and the same effect as in the case of FIG. 6 can be obtained.

  In the present embodiment, the case where the end portions of the semiconductor wiring 14L are connected has been described. However, the present invention is not limited to such a case. That is, regardless of whether or not it is a terminal portion, if the semiconductor wirings 14L can be connected to each other and the area thereof can be increased, the occurrence of defects due to static electricity can be suppressed, and the effects of the present invention are achieved.

Embodiment 2. FIG.
In the first embodiment, the case where all the semiconductor wirings 14L are connected has been described. In contrast, in the present embodiment, a case will be described in which each semiconductor wiring 14L is connected to any other semiconductor wiring 14L, and two or more semiconductor patterns to which all the semiconductor wirings 14L belong are formed.

  FIG. 10 is a view showing an example of the configuration of the main part of the TFT array substrate 100 according to the second embodiment of the present invention, in which two semiconductor patterns 142a and 142b formed on the insulating substrate 10 are shown. Yes. Each of the semiconductor patterns 142a and 142b has a comb-like shape in which a large number of semiconductor wirings 14L are connected at one end portion, and the adjacent semiconductor wirings 14L belong to different semiconductor patterns 142a and 142b. In other words, the comb-shaped semiconductor patterns 142a and 142b are arranged to face each other in a state where one tooth is inserted and combined in order between the other teeth.

  In this case, unlike the first embodiment, not all semiconductor wirings 14L are connected to form one semiconductor pattern, but each semiconductor wiring 14L is connected to at least one of the other semiconductor wirings 14L. It is connected and belongs to one of the semiconductor patterns 142a and 142b. In other words, as in the first embodiment, there is no semiconductor wiring 14L formed independently, and the area of each semiconductor wiring 14L can be increased as compared with the conventional TFT array substrate.

  FIG. 11 is a diagram showing another configuration example of the main part of the TFT array substrate 100 according to the second embodiment of the present invention, and shows a large number of semiconductor patterns 143 formed on the insulating substrate 10. . Each semiconductor pattern 143 is configured by connecting two semiconductor wirings 14L. For this reason, there is no semiconductor wiring 14L formed independently, and the area of each semiconductor wiring 14L can be increased as compared with the conventional TFT array substrate.

  According to the present embodiment, two or more semiconductor patterns are formed on the insulating substrate 10. Each semiconductor pattern includes two or more semiconductor wirings 14L connected by the semiconductor connecting portion 14J, and all the semiconductor wirings 14L belong to any one of the semiconductor patterns. For this reason, the area of each semiconductor wiring 14L can be increased, the potential of each semiconductor wiring 14L can be stabilized, and the occurrence of defects due to static electricity can be suppressed.

Embodiment 3 FIG.
In the first and second embodiments, the example in which the semiconductor wiring 14 </ b> L is connected outside the display region 104 has been described. On the other hand, in the present embodiment, a case where the semiconductor wiring 14L is connected in the display region 104 will be described.

  FIG. 12 is a view showing a configuration example of the main part of the TFT array substrate 100 according to the third embodiment of the present invention, and shows a semiconductor pattern 144 formed on the insulating substrate 10. The semiconductor pattern 144 includes a large number of semiconductor wirings 14 </ b> L and a semiconductor connection portion 14 </ b> K that connects these semiconductor wirings 14 </ b> L in the display region 104. The semiconductor connecting portion 14K is formed on the gate wiring 11L and connects adjacent semiconductor wirings 14L at the intersection of the gate wiring 11L and the source wiring 15L. Therefore, the semiconductor wiring 14L can be connected in the display region 104 without reducing the aperture ratio.

  Here, when the semiconductor connecting portion 14K is extended along the gate wiring 11L and the semiconductor wiring 14L is connected, there is a problem that adjacent TFTs 105 are connected. That is, a region of the semiconductor layer located on the gate line 11L is activated by the potential of the gate line 11L. If this activated region is a continuous region for the TFTs 105 adjacent in the direction of the gate wiring 11L, current flows between these TFTs 105, and the TFTs 105 cannot be operated normally. For this reason, it is necessary to have a configuration in which the activation region is not continuous between the TFTs 105.

  FIG. 13 is an enlarged plan view showing the semiconductor connecting portion 14K of FIG. The semiconductor connection portion 14K is formed so as to extend substantially along the gate wiring 11L, but has a non-overlapping region that does not overlap with the gate wiring 11L, and the active region of the adjacent TFT 105 is one end in this non-overlapping region. There are discontinuities and discontinuities.

  Here, the gate wiring 11L and the semiconductor connecting portion 14K have constricted portions 11n and 14n with narrowed wiring widths, respectively, and the constricted portion 14n of the semiconductor connecting portion 14K does not overlap with the gate wiring 11L. The constricted part 11n is allowed to pass through. That is, a region not overlapping with the gate wiring 11L is provided in the semiconductor connection portion 14K, and the activation region is interrupted at one end. Therefore, the adjacent semiconductor wirings 14L can be connected while discontinuous the activation regions of the adjacent TFTs 105.

  FIG. 14 is a plan view showing an example in which the semiconductor connecting portion 14K of FIG. 12 is formed on the auxiliary electrode wiring 11C. The semiconductor connecting portion 14K is formed on the auxiliary electrode wiring 11C and connects adjacent semiconductor wirings 14L at the intersection of the auxiliary electrode wiring 11C and the source wiring 15L. Therefore, as in the case shown in FIG. 13, the semiconductor wiring 14 </ b> L can be connected in the display region 104 without reducing the aperture ratio.

  FIG. 15 is a diagram showing another configuration example of the main part of the TFT array substrate 100 according to the third embodiment of the present invention, and shows a semiconductor pattern 145 formed on the insulating substrate 10. In the semiconductor pattern 145, a large number of semiconductor connection portions 14 </ b> K are formed in the display region 104, and semiconductor connection portions 14 </ b> J are also formed outside the display region 104. For this reason, a manufacturing yield can be improved more effectively.

  According to the present embodiment, the semiconductor connecting portion 14K is extended along the gate line 11L to connect the adjacent semiconductor lines 14L in the display region 104. At this time, a part of the semiconductor connecting portion 14K is formed without overlapping the gate wiring 11L, and the active regions of the adjacent TFTs 105 are made discontinuous to prevent the TFTs 105 from being combined. ing. Therefore, the area of the semiconductor wiring 14L can be increased in the display region 104, and the occurrence of defects due to static electricity can be suppressed.

  Therefore, the semiconductor wiring 14L can be connected without providing the semiconductor connecting portion 14J outside the display region 104. Furthermore, by forming the semiconductor connection portion 14K in the display region 104 and the semiconductor connection portion 14K outside the display region 104, it is possible to more effectively suppress the occurrence of defects due to static electricity.

  13 and 14, an example in which the semiconductor coupling portion 14K is formed on the gate electrode 11L or the auxiliary electrode wiring 11C has been described. However, the semiconductor coupling portion 14K may be located at any position in the display region 104. Can be formed. That is, if the semiconductor wiring 14L can be connected in the display region 104, the area of the semiconductor wiring 14L can be increased in the display region 104, and the occurrence of defects due to static electricity can be suppressed.

It is the figure which showed one structural example of the liquid crystal display device containing the TFT array substrate by this invention. 4 is an enlarged plan view showing one pixel on the TFT array substrate 100. FIG. It is sectional drawing by the AA cut line and BB cut line in the TFT array substrate 100 of FIG. It is the top view which showed an example of the manufacturing process of a TFT array substrate. It is sectional drawing which showed an example of the manufacturing process of a TFT array substrate. It is the top view which showed one structural example about the principal part of the TFT array substrate 100 by Embodiment 1 of this invention. An enlarged plan view of the area A1 (near the upper edge of the display area 104) in FIG. 6 is shown. An enlarged plan view of the area A2 (near the lower edge of the display area 104) in FIG. 6 is shown. It is the figure which showed the other structural example about the principal part of the TFT array substrate 100 by Embodiment 1 of this invention. It is the figure which showed one structural example about the principal part of the TFT array substrate 100 by Embodiment 2 of this invention. It is the figure which showed the other structural example about the principal part of the TFT array substrate 100 by Embodiment 2 of this invention. It is the figure which showed one structural example about the principal part of the TFT array substrate 100 by Embodiment 3 of this invention. It is the top view which expanded and showed the semiconductor connection part 14K of FIG. FIG. 13 is a plan view showing an example in which the semiconductor connecting portion 14K of FIG. 12 is formed on the auxiliary electrode wiring 11C. It is the figure which showed the other structural example about the principal part of the TFT array substrate 100 by Embodiment 3 of this invention. In the manufacturing process of such a TFT array substrate, the inventors have found that damage considered to be caused by static electricity is observed in the semiconductor layer after the patterning process. FIG. 16 is a diagram showing an example of this state. It is the figure which showed an example of the damage of the semiconductor layer after the patterning process in the conventional TFT array substrate. It is the figure which showed an example of the dry etching process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Insulating substrate 11L Gate wiring 11G Gate electrode 11C Auxiliary capacity wiring 12 Insulating film 14J, 14K Semiconductor connection part 14T TFT semiconductor part 14L Semiconductor wiring 15L Source wiring 15S Source electrode 15D Drain electrode 16 Interlayer insulating film 17 Pixel electrode 20 Channel region 21 Contact hole 100 TFT array substrate 101 Control substrate 102 Gate drive module 103 Source drive module 104 Display region 140, 141, 142a, 142b, 143 to 145 Semiconductor pattern 105 TFT

Claims (7)

A number of gate wirings composed of a first metal layer;
A number of source lines made of a second metal layer and arranged to intersect the gate lines;
A TFT composed of a gate electrode made of the first metal layer, a source electrode and a drain electrode made of the second metal layer, and an insulating film and a semiconductor layer formed between the first metal layer and the second metal layer. When,
Made from the semiconductor layer and the same layer, they are respectively disposed under the source wiring, and the semiconductor wiring was distracted along the source wiring,
A TFT comprising the same layer as the semiconductor layer, and a semiconductor connecting portion for forming a series of semiconductor patterns together with two or more semiconductor wires under the different source wires, and connecting these semiconductor wires Array substrate. 2. The TFT array substrate according to claim 1 , wherein the semiconductor connecting portion connects two or more semiconductor wirings under different source wirings outside a display region. 3. The TFT array substrate according to claim 2 , wherein the semiconductor connection portion connects two or more semiconductor wirings under different source wirings on each of opposite side edges of the display region. 3. The TFT array substrate according to claim 2, wherein the semiconductor connecting portion connects the semiconductor wiring in parallel to an edge of the display region outside the display region. The TFT array substrate according to claim 1, wherein the semiconductor connection portion connects adjacent semiconductor wirings in a display region. 6. The semiconductor connecting portion according to claim 5, wherein the semiconductor connecting portion is disposed on the gate wiring, extends along the gate wiring, and has a non-overlapping region with the gate wiring between the different source wirings. TFT array substrate. Made from the first metal layer, are arranged parallel to the gate lines, a number of storage capacitor lines which are connected to each other,
The TFT array substrate according to claim 5, wherein the semiconductor connection portion is disposed on the auxiliary capacitance line and extends along the auxiliary capacitance line.

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