JP4031335B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including means for generating various control signals internally.
[0002]
[Prior art]
A semiconductor memory device configured to detect a change in an address value of an address signal and internally generate various control signals that become an activation level or an inactivation level for a predetermined period and control the operation of each unit. The longer the interval at which the address value changes, the smaller the ratio of the actual operation time to this access cycle, so that the current consumption can be reduced.
[0003]
In general, in a semiconductor memory device, a circuit that performs self-control by simulating an operation is often used for the purpose of suppressing unnecessary operation and reducing current consumption. A typical example is a dummy memory circuit. This simulates reading from the memory cell and detects whether reading is completed, thereby changing the internal activation signal to an inactive state.
[0004]
Usually, a semiconductor memory device selects a memory cell by an address signal, and reads / writes data from / to the selected memory cell. In the read mode, data from the memory cell is transmitted to the sense amplifier via the bit line pair, and the data with a slight potential difference is amplified there. A signal from the sense amplifier is output as a data output through an output circuit.
[0005]
In the write mode, the data input from the input circuit is transmitted to the bit line pair by the write buffer, and the selected memory cell is written.
[0006]
Here, the period in which the operation as the semiconductor memory device is necessary is until data in the read mode is output or until data writing to the memory cell in the write mode is completed. It is desirable to be stationary. In particular, when a current mirror type sense amplifier is used, a through current continues to flow after reading.
[0007]
In order to prevent such a problem, the dummy memory circuit is a circuit that monitors the operation of the memory in a pseudo manner, and controls the output circuit, the sense amplifier, the word line selection, and the like. For example, by monitoring the output state of the sense amplifier, output data can be latched and the activation state of the sense amplifier can be controlled, and word line selection can be controlled from the potential level of the bit line.
[0008]
This not only suppresses the through current in the sense amplifier, but also suppresses the bit line from swinging more than necessary for the sense amplifier to detect.
[0009]
When performing self-control using this dummy memory circuit, it is necessary to confirm that the output from the sense amplifier has been reliably performed, and to control the activation state of the sense amplifier and the word line. However, if an excessive operating margin is taken, the performance of the semiconductor memory device itself is lowered. On the other hand, if the timing of deactivation is too early, erroneous output of data will be caused. Therefore, a certain operating margin must be provided with certainty.
[0010]
Moreover, even if it is not a circuit that can output correct data against unpredictable factors such as variations in memory cells, sense amplifier characteristics, bit line capacitance, and resistance due to manufacturing variations, the yield is reduced. In addition, since the current consumption of the control circuit itself increases, a method that can secure an operation margin as easily as possible is preferable.
[0011]
Usually, a dummy circuit is used at the farthest end of the word line driver and an operation margin is to be secured by some method. For example, there is a configuration in which the dummy bit line pair is widened and the line spacing is narrowed to increase the parasitic capacitance of the dummy bit line and delay the output of the dummy memory circuit (for example, Patent Document 1). ). As another method, it has also been proposed to reduce the driving capability of the dummy memory cell.
[0012]
[Patent Document 1]
JP-A-8-273365 [0013]
[Problems to be solved by the invention]
According to the present invention, the dummy memory can be easily formed only on the layout without changing the characteristics of the dummy memory cell and the dummy bit line and without increasing the chip area and the consumption current by adding an extra control circuit. The purpose is to give an operation margin to a self-control circuit using a circuit.
[0014]
[Means for Solving the Problems]
The present invention relates to a memory array having a plurality of memory cells, a bit line pair for inputting / outputting complementary signals from the memory cell, a sense amplifier for amplifying a signal from the bit line pair, and an initial of the bit line pair. In a semiconductor memory device having a precharge circuit that maintains a state at a power supply potential and a dummy circuit that simulates reading from the memory cell, the dummy circuit operates in synchronization with the selection of the memory cell, A dummy memory cell having fixed data in advance, a dummy bit line pair connected to the dummy memory cell, a dummy sense amplifier for detecting and amplifying data from the dummy bit line pair, and the dummy bit line pair A dummy precharge circuit that maintains the initial state at the power supply potential, and from the dummy circuit Immediately before the data is read out, the dummy bit line on the “L” data output side of the dummy bit line pair is temporarily charged up to the power supply potential in the initial state by the coupling capacitor to delay the data reading. Features.
[0015]
The dummy circuit has a signal line arranged in parallel with the dummy bit line on the “L” data output side, and the signal line changes from “L” to “H” when a dummy memory cell is selected. The dummy bit line can be configured to be charged up by the coupling capacitance of these signal lines.
[0016]
The present invention also provides a divided word line type semiconductor memory device that includes a divided word line circuit that divides a word line by a row address and a column address and selects only the minimum necessary memory cells. The dummy circuit includes a dummy memory cell, a dummy bit line pair, a dummy sense amplifier, a dummy precharge circuit, and a dummy divided word line circuit, and simulates a column side word line selected by a column address. A signal line for driving the dummy divided word line circuit and a dummy bit line for outputting the “L” data are arranged in parallel, and the dummy bit line is charged up by a coupling capacitance between the lines. The reading from the dummy memory cell can be delayed.
[0017]
According to the configuration described above, the dummy bit line is charged up to a constant potential by the selection signal immediately before the dummy word line for selecting the dummy memory cell is selected. As a result, the output of the dummy bit line can be delayed for a certain period of time. By adjusting this charge-up amount, it can be used as an operating margin for characteristic changes due to manufacturing variations.
[0018]
The present invention also provides a memory array having a plurality of memory cells, a bit line pair for inputting / outputting complementary signals from the memory cell, a sense amplifier for amplifying a signal from the bit line pair, and the bit line pair. In a semiconductor memory device having a precharge circuit that keeps the initial state at the power supply potential and a dummy circuit that simulates reading from the memory cell, the dummy circuit operates in synchronization with the selection of the memory cell. A dummy memory cell having data fixed in advance, a dummy bit line pair connected to the dummy memory cell, a dummy sense amplifier for detecting and amplifying data from the dummy bit line pair, and the dummy bit line A dummy precharge circuit that maintains the initial state of the pair at the power supply potential, Immediately before reading the data, the dummy bit line that outputs “H” data in the pair of dummy bit lines is temporarily pulled down below the power supply potential in the initial state by a coupling capacitor to delay the data reading. And
[0019]
According to the above configuration, the dummy sense detection time can be delayed by temporarily pulling down the “H” read side of the dummy bit line.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an embodiment of a semiconductor memory device according to the present invention. In the embodiment shown in FIG. 1, a type in which the minimum necessary memory cells are selected in units of blocks from the row address and the column address is taken as an example.
[0021]
This semiconductor memory device has first and second data input / output terminals and, when in a selected state, writes and stores data in a complementary level relationship from these first and second data input / output terminals. A memory cell array 1 is provided in which a plurality of memory cells (MC) for reading data being read are arranged in a row direction and a column direction.
[0022]
In this embodiment, since the word line is divided and selected in the memory array 1 portion, divided word line cells (DWL cells) are arranged every plural bits, and the main output from the row decoder 2 is provided. The word line (MWL) and the Y gate selection signal (YG) output from the column decoder 4 are input. These memory cells (MC) and divided word line cells (DWL cells) are connected via a sub word line (SWL), and the sub word line (SWL) is a signal of the word line (MWL) and the Y gate selection signal (YG). Selected from. At this time, the number of memory cells (MC) connected to one sub word line (SWL) is not particularly limited, and can be arbitrarily determined in consideration of the memory configuration and performance. In the circuit using the divided word line cell (DWL cell), the bit line pair connected to the unselected Y gate does not select the sub word line (SWL), so that data output to the bit line is not performed, which is useless. There is an advantage that charging / discharging current can be suppressed.
[0023]
The semiconductor memory device includes first and second data input / output terminals corresponding to the first and second data input / output terminals of the memory cells (MC) in the corresponding columns provided corresponding to the respective columns of the plurality of memory cells (MC). A predetermined word line is set to a selected level in accordance with a plurality of bit line pairs formed of second bit lines (BL, BR) and a row address signal input to address input circuit 10 when the word line activation signal is at an activation level. In response to a row address decoder 2 that performs the precharge control signal in response to an activation level of the precharge control signal, a precharge circuit that precharges the plurality of bit line pairs to a predetermined potential, and a column address signal input to the address input circuit 10 A column address decoder 4 and a column gate circuit 5 of a column selection circuit for selecting a predetermined bit line pair among the plurality of bit line pairs. A sense amplifier 6 that amplifies and outputs the data of the bit line pair selected by the column selection circuit in response to the activation level of the sense amplification activation signal, and activates the data latch signal using the output data of the sense amplifier 6 An input / output circuit 8 that latches and outputs in response to a level and a write buffer circuit 7 that temporarily latches write data supplied from the input / output circuit 8 are provided.
[0024]
Further, the memory cell (MC) and the dummy memory cell (DMC) are connected to the same main word line (MWL) and selected in synchronization. The dummy memory cell (DMC) is connected to the dummy bit line pair (DBL, DBR), and data read from the dummy bit line pair (DBL, DBR) is supplied from the column gate 9 to the dummy sense amplifier 10.
[0025]
Then, “L” is read out to the DBL side of the dummy bit line pair (DBL, DBR). If the signal from the dummy bit line (DBL, DBR) is detected by the dummy sense amplifier 10, the output of the main sense amplifier 6 is determined and the sense amplifier 6 is changed from the activated state to the inactivated state. It is controlled by the internal control circuit 20 so as to be changed. Similarly, the word line (MWL) is changed to a non-selected state. As a result, it is possible to prevent the through current in the sense amplifier and the charge / discharge current in the bit line from being consumed more than the amount necessary for reading data.
[0026]
In the dummy memory circuit for monitoring the memory array configured using the DWL cell, it is necessary to configure a circuit including the DWL cell. FIG. 2 shows a configuration of a 6-transistor type SRAM used in a normal memory cell MC. FIG. 3 shows a dummy memory cell (DMC). Since it is necessary to always output the same data to the memory cell used in the dummy circuit, the internal node is fixed and “L” is always output from the BL side and “H” is always output from the BR side. Has been.
[0027]
The DWL cell may be composed of a NAND gate and an inverter, but a cell as shown in FIG. 4 is often used in consideration of the cell size.
[0028]
5 shows a configuration example of the sense amplifier and FIG. 6 shows a configuration example of the write buffer circuit.
[0029]
FIG. 7 shows layout wiring on the memory array 1. The word line (MWL), the bit line (BL, BR), and the Y gate line (YG) are arranged to be orthogonal. Here, the bit lines (BL, BR) represent n bits in one block. Also, a guard metal (G) is inserted between the signal line YG and the bit lines (BL, BR) in order to prevent the bit line from malfunctioning due to the influence of noise due to the change in the Y gate line (YG). Yes. The potential of the guard metal is fixed to the power supply potential or the GND potential to prevent noise from entering the bit line (BL0).
[0030]
A feature of the present invention is that a coupling capacitance between wirings is consciously wired in parallel without performing an insulating effect by a guard ring between a dummy bit line (DBL) and a dummy Y gate signal (DYG) in the dummy circuit. Give it. A signal change due to the dummy Y gate signal (DYG) is transmitted to the dummy bit line (DBL) by coupling noise. As a result, immediately before the dummy SWL signal for selecting the dummy memory cell (DMC) is selected, the dummy bit line (DBL) is charged up to a constant potential by the selection signal DYG. As a result, the output of the dummy bit line (DBL) can be delayed for a certain period of time. By adjusting this charge-up amount, it can be used as an operating margin for characteristic changes due to manufacturing variations.
[0031]
The effect of using the coupling noise will be described with reference to a timing diagram. FIG. 8 shows a conventional example in which the DBL is completely guarded and the configuration is the same as that of a normal memory cell. FIG. 9 is a timing chart showing the effect of the present invention.
[0032]
In the conventional example of FIG. 8, the YG signal is selected in synchronization with the clock CK, SWL is activated, and data is output to the BL pair. Since the same operation is performed in the dummy circuit, the dummy DBL pair has the same amplitude as the normal BL pair. Here, if the dummy sense amplifier 10 can detect the “L” output from the dummy DBL, it is assumed that the output can be detected by the normal sense amplifier 6, and the DSA signal is output to the internal control circuit 20 to stop the internal operation. The action to work works. However, not all of the memory circuits have the same finish, and there is a change in characteristics due to manufacturing variations and the like, so that the operation of DBL needs to have a certain margin as compared with normal BL.
[0033]
In FIG. 9, the potential of the BDL is temporarily charged up in synchronization with the rising edge of the YG signal (marked with a circle in the figure). Since “L” reading is performed from this state, the detection time of the dummy sense amplifier 10 is delayed as compared with normal. At this time, since the guard ring is performed between the normal BL side and the YG signal, the output can be performed earlier than the dummy circuit. The difference between the read initial potentials of BL and DML can be secured as an operation margin.
[0034]
The present invention can be easily controlled on the layout, and the operation margin can be easily changed without changing the circuit by changing the space between the wirings. In addition, since the coupling capacity varies with the length in the bit line direction, a new timing control circuit has been added to those used with varying memory capacity such as compiled cells. Without having to do so, it can be guaranteed with a certain operating margin.
[0035]
FIG. 10 shows another embodiment in which a coupling capacitor is provided between the dummy bit line (DBL) and the dummy Y gate signal (DYG) in the dummy circuit. As shown in FIG. 10, this embodiment uses inter-wiring capacitance generated by wiring DYG with DBL's upper layer metal. If a metal for shielding is arranged on a bit line normally used and a DYG signal is used on a dummy bit line (DBL), a layout capable of controlling the DBL without changing the parasitic capacitance value of the bit line can be created.
[0036]
As another configuration method of the present invention, a YGB signal selected at the falling edge can be used as a noise insertion signal to the dummy bit line (DBL). In this case, it works to lower the potential of the dummy bit line, so the sensitivity of the dummy sense amplifier is poor, and it is used for the purpose of speeding up the inactive state when the operation margin of the signal controlling the normal memory circuit is too large. be able to. The same effect can be obtained by temporarily controlling the potential on the DBR side instead of the DBL with the YG signal or the YGB signal.
[0037]
FIG. 11 shows a timing chart when pulling down DBR. As shown in FIG. 11, since the “H” read side of the dummy bit line is temporarily pulled down, the dummy sense detection time can be similarly delayed.
[0038]
In the present invention, the case of a memory circuit of the type using the divided word line method (DWL method) has been described as an example. However, the present invention can also be applied to a normal bit slice type memory cell, and the same effect can be obtained.
[0039]
【The invention's effect】
As described above, according to the present invention, the dummy memory circuit for monitoring the read state of the memory cell and controlling the activation state is added without adding a new circuit with a certain operation margin. It can be easily configured only on the layout. As a result, it is possible to reduce the consumption without degrading the operation performance, and it is possible to deal with cells of any memory size with a certain operation margin.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration in an embodiment of a semiconductor memory device of the present invention;
FIG. 2 is a circuit diagram showing an example of a memory cell.
FIG. 3 is a circuit diagram showing an example of a dummy memory cell.
FIG. 4 is a circuit diagram showing an example of a divided word line cell.
FIG. 5 is a circuit diagram illustrating an example of a sense amplifier.
FIG. 6 is a circuit diagram illustrating an example of a write buffer.
FIG. 7 is a schematic diagram showing a layout wiring according to an embodiment of the present invention.
FIG. 8 is a time chart when a conventional dummy memory circuit is used.
FIG. 9 is a time chart when the semiconductor memory device of the present invention is used.
FIG. 10 is a schematic diagram showing a layout wiring according to another embodiment of the present invention.
FIG. 11 is a time chart when the semiconductor memory device of the present invention is used.
[Explanation of symbols]
1 memory cell array 2 row decoder 4 column decoder 5 column gate 6 sense amplifier 7 write buffer circuit 8 input / output circuit 9 dummy column gate 10 dummy sense amplifier 11 address input circuit 20 internal control circuit MC memory cell DMC dummy memory cell DWL divided word line SWL sub word line MWL main word line YG Y gate selection signal BL, BR bit line pair DBL, DBR dummy bit line pair

Claims (4)

A memory array having a plurality of memory cells, a bit line pair for inputting / outputting complementary signals from the memory cell, a sense amplifier for amplifying a signal from the bit line pair, and an initial state of the bit line pair as a power supply potential In a semiconductor memory device having a precharge circuit held in the memory cell and a dummy circuit for simulating reading from the memory cell, the dummy circuit operates in synchronization with the selection of the memory cell and is fixed in advance. A dummy memory cell having data, a dummy bit line pair connected to the dummy memory cell, a dummy sense amplifier for detecting and amplifying data from the dummy bit line pair, and an initial state of the dummy bit line pair as a power source A dummy precharge circuit that holds the potential, and immediately before reading from the dummy circuit The dummy bit line that outputs "L" data in the dummy bit line pair is temporarily charged up to the power supply potential in the initial state by a coupling capacitor to delay data reading. Storage device. The dummy circuit has a signal line arranged in parallel with the dummy bit line on the “L” data output side, and the signal line changes from “L” to “H” when a dummy memory cell is selected. 2. The semiconductor memory device according to claim 1, wherein the dummy bit line is charged up by a coupling capacitance of these signal lines. In a divided word line type semiconductor memory device that includes a divided word line circuit that divides a word line by a row address and a column address and selects only a minimum necessary memory cell, a dummy circuit for simulating the memory circuit is A dummy memory cell, a dummy bit line pair, a dummy sense amplifier, a dummy precharge circuit, and a dummy divided word line circuit are provided, simulating a column side word line selected by a column address, and the dummy divided word A signal line that drives a line circuit and a dummy bit line that outputs the "L" data are arranged in parallel, and the dummy bit line is charged up by the coupling capacitance between the lines to read from the dummy memory cell. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is delayed. A memory array having a plurality of memory cells, a bit line pair for inputting / outputting complementary signals from the memory cell, a sense amplifier for amplifying a signal from the bit line pair, and an initial state of the bit line pair as a power supply potential In a semiconductor memory device having a precharge circuit held in the memory cell and a dummy circuit for simulating reading from the memory cell, the dummy circuit operates in synchronization with the selection of the memory cell and is fixed in advance. A dummy memory cell having data, a dummy bit line pair connected to the dummy memory cell, a dummy sense amplifier for detecting and amplifying data from the dummy bit line pair, and an initial state of the dummy bit line pair as a power source A dummy precharge circuit that holds the potential, and immediately before reading from the dummy circuit A semiconductor memory characterized in that the dummy bit line on the “H” data output side of the pair of dummy bit lines is temporarily pulled down below the power supply potential in the initial state by a coupling capacitor to delay data reading. apparatus.

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