JP4031752B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and more particularly, to a gate electrode / wiring of a MOS transistor in a system LSI in which element groups having fine repetitive patterns such as DRAM (Dynamic Random Access Memory) can be mixedly mounted. Alternatively, the present invention relates to a technique for forming a line pattern such as a metal wiring.

  In recent years, for example, as a semiconductor integrated circuit device in which DRAM is mixedly mounted, a system LSI having a mounted DRAM capacity exceeding 20 megabits is being mass-produced.

  Also, the mounting ratio of a memory circuit such as a DRAM, SRAM (Static Random Access Memory) or ROM (Read Only Memory) to one semiconductor chip (ratio of the area of the memory circuit to the area of the entire chip: hereinafter occupied area ratio) In the manufacturing process of a semiconductor integrated circuit device including a system LSI, which differs depending on the application or specifications, the unit circuits are not simply arranged repeatedly, but mask patterns with various layouts are used. Processing is required.

  Conventionally, the shape or dimension of a pattern (hereinafter referred to as a processing pattern) obtained by etching a film to be processed using a mask pattern varies depending on the mask pattern layout, that is, the arrangement of element patterns. The phenomenon is known.

  As an example, there is a pattern proximity effect that occurs when a resist pattern is formed in a photolithography process. This is because even if the patterns have the same design shape and design dimensions, how close the pattern is to other adjacent patterns, or what is the shape of other adjacent patterns This is a phenomenon in which the processing shape or processing dimension of the pattern varies depending on whether or not it is.

  Another example is the loading effect or microloading effect in the dry etching process. The loading effect is a phenomenon in which the etching rate changes depending on the size of the entire etching area on the semiconductor chip, which may cause a slight influence on the variation in pattern dimensions. The microloading effect is a phenomenon in which the etching rate is locally different depending on the density when the arrangement in the patterns laid out inside the same semiconductor chip is dense depending on the location. That is, even if the patterns are exactly the same, the etching rate differs between the places where they are sparsely arranged and the places where they are densely arranged, and this also has an indirect influence on the variation in pattern dimensions.

  In contrast to the above-described problems such as variation in pattern dimension depending on the mask pattern layout, the pattern has been conventionally used only at a mask location where the pattern dimension is considered to vary significantly depending on the mask pattern layout due to the proximity effect or loading effect. Design rules were added to compensate for dimensional variations.

  Further, in the manufacture of a system LSI capable of incorporating DRAM, the same processing method or processing conditions have been used regardless of whether DRAM is installed or the DRAM occupation area ratio (ratio of the area of the DRAM to the area of the entire chip). It was.

  However, with the progress of miniaturization of LSIs, more specifically, with the progress of miniaturization of integrated circuit pattern dimensions of 0.25 μm or less, particularly 0.15 μm or less, more accurate dimension control is required. As a result, dimensional variations caused by differences in the mask pattern layout cannot be ignored.

  FIG. 8 shows a semiconductor integrated circuit device (hereinafter referred to as a DRAM-equipped product) on which a 24-megabit DRAM is mounted and a semiconductor integrated circuit device (hereinafter referred to as a DRAM-uninstalled product) on which no DRAM is mounted. The frequency distribution of CD (critical dimension) loss, which is the difference between the dimension of the resist pattern before etching and the dimension of the completed gate electrode, when the gate electrode is formed by dry etching using the resist pattern as a mask in manufacturing is shown. . The results shown in FIG. 8 are obtained by adopting the same gate electrode processing process in the production of each of the DRAM-equipped and non-DRAM-equipped products. The CD loss calculation method is (size of resist pattern before etching) − (size of completed gate electrode).

  As shown in FIG. 8, although the same gate electrode processing process is used for each type, the pattern dimension dependency on the mask pattern occurs.

  In other words, in the conventional method of manufacturing a semiconductor integrated circuit device, even if the same gate electrode processing process is employed, the gate electrode dimensions vary due to the difference in the mask pattern layout accompanying the difference in product type. In other words, product type dependency occurs in the gate electrode dimensions. As a result, in a specific type of semiconductor integrated circuit device manufactured using a specific mask, the characteristics of the MOS transistor deviate from the design specification, and the operation margin becomes narrow. Such a problem cannot be ignored particularly when the design rule is 0.18 μm or less.

  In view of the foregoing, an object of the present invention is to prevent dimensional variations caused by differences in mask pattern layout when forming a line pattern such as a gate electrode / wiring or metal wiring of a MOS transistor. And

  In order to achieve the above object, the inventors of the present application have examined the cause of dimensional variations caused by differences in mask pattern layout.

  As a result, in a semiconductor integrated circuit device in which a logic circuit made of CMOS (Complementaly Metal-Oxide Semiconductor) is mounted and a memory circuit such as a DRAM in which gate electrodes and wirings are closely arranged is mounted, It was found that the pattern size fluctuates depending on the area occupied by the circuit.

  Further, it has been found that the phenomenon in which the dimensional variation is caused by the difference in the mask pattern layout is different in nature from the loading effect which occurs depending on the size of the etched area, that is, the size of the pattern area. Further, as is apparent from FIG. 8, this phenomenon is a phenomenon of a novel property that the pattern dimension varies over the entire chip, unlike the microloading effect that occurs depending on the density of the local pattern inside the chip. I found that there was.

By the way, as described above, the product type dependency in the processing dimension such as the gate electrode dimension occurs due to the CD loss. On the other hand, in the current dry etching process, in order to prevent side etching and achieve anisotropic dry etching, an etching gas having a sidewall protection effect (hereinafter referred to as a deposition gas) is used or has a sidewall protection effect. An etching reaction product is formed. For example, when a gate electrode is formed by performing dry etching on a polysilicon film, a chlorine-containing gas is often used as an etching gas and at the same time HBr gas is often used as a deposition gas. In this way, a low-volatility sidewall protective film made of SiBr ₄ that is a reaction product of HBr and polysilicon is formed on the sidewall of the polysilicon film. Further, when dry etching is performed on an aluminum film to form an aluminum wiring, CHF ₃ gas is often used as a deposition gas recently. Here, CHF ₃ gas, which is a fluorine-containing gas, is a deposition gas added to form the sidewall protective film, but does not contribute to the etching of the aluminum film.

  When the same gate electrode processing process is used regardless of the mask pattern layout, if the processing shape of the etching target film is controlled by the side wall protection effect, the unit of the etching target film to be protected increases as the area of the side wall increases. The inventors of the present application have found that the side wall protection effect per area is reduced, thereby increasing the CD loss.

  FIG. 9 shows the relationship between the peripheral length of the gate electrode per unit area (the length of the peripheral edge of the gate electrode) and the DRAM occupied area ratio in the products having various DRAM occupied area ratios including those not equipped with DRAM. Yes. In the graph of FIG. 9, the “peripheral length of the gate electrode per unit area” taken on the vertical axis is a value obtained by dividing the total peripheral length of the gate electrode on the predetermined circuit region by the area of the predetermined circuit region. means. Here, the predetermined circuit area may be the entire chip.

  As shown in FIG. 9, the gate electrode peripheral length per unit area increases as the DRAM occupation area ratio increases.

  FIG. 10 shows the relationship between the gate electrode peripheral length per unit area and CD loss in various varieties.

  As shown in FIG. 10, when the gate electrode peripheral length per unit area increases, the gate electrode dimension decreases (CD loss becomes positive), while when the gate electrode peripheral length per unit area decreases, the gate electrode dimension increases ( CD loss becomes negative). This is because the area of the side wall to be protected increases as the peripheral length of the gate electrode per unit area increases, thereby reducing the side wall protecting effect per unit area.

  The inventors of the present application pay attention to the fact that the CD loss monotonously changes from a negative value to a positive value as the peripheral length of the gate electrode per unit area increases (see FIG. 10). Regardless of the mask pattern layout difference, set the gate electrode perimeter per unit area within a predetermined range or adjust the process conditions according to the type of gate electrode perimeter per unit area. It has been found that it is possible to prevent the occurrence of dimensional variations due to the above.

  Specifically, a first method for manufacturing a semiconductor integrated circuit device according to the present invention includes a circuit pattern having a line pattern, and manufactures a plurality of semiconductor integrated circuit devices that share at least a part of the manufacturing process. Assuming a method for manufacturing a semiconductor integrated circuit device, the manufacturing process of each semiconductor integrated circuit device is performed on a film to be processed while adjusting dry etching conditions according to the peripheral length per unit area of the line pattern. Including a step of dry etching.

  According to the first method for manufacturing a semiconductor integrated circuit device, the dry etching is performed on the film to be processed while adjusting the dry etching conditions according to the peripheral length per unit area of the line-shaped pattern. Even when the mask pattern layout varies greatly depending on the type, the dimension of the line pattern can always be made equal to the predetermined value. Therefore, even in a system LSI in which the mounting rate of DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode or metal wiring can be made constant regardless of the mask pattern layout, so that the semiconductor integrated circuit in which the variation in operation margin is eliminated A device can be realized.

  In the first method for manufacturing a semiconductor integrated circuit device, the step of adjusting the dry etching conditions includes the step of setting one dry etching condition when the peripheral length per unit area of the line pattern is within one range. It is preferable to include.

  In this way, the dry etching conditions can be easily adjusted.

  A second semiconductor integrated circuit device manufacturing method according to the present invention includes a circuit pattern having a line pattern, and a semiconductor integrated circuit for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of a manufacturing process. Based on the manufacturing method of the circuit device, the manufacturing process of each semiconductor integrated circuit device forms a resist pattern corresponding to the line pattern while adjusting the dimension according to the peripheral length per unit area of the line pattern. Process.

  According to the second method for manufacturing a semiconductor integrated circuit device, the resist pattern corresponding to the line pattern is formed while adjusting the dimension according to the peripheral length per unit area of the line pattern. Even when the mask pattern layout varies greatly depending on the type of the line, the dimension of the line pattern can always be made equal to the predetermined value. Therefore, even in a system LSI in which the mounting rate of DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode or metal wiring can be made constant regardless of the mask pattern layout, so that the semiconductor integrated circuit in which the variation in operation margin is eliminated A device can be realized.

  A third method for manufacturing a semiconductor integrated circuit device according to the present invention includes a circuit pattern having a line pattern, and a semiconductor integrated circuit for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of a manufacturing process. Based on the manufacturing method of the circuit device, the manufacturing process of each semiconductor integrated circuit device includes a first step of forming a resist pattern corresponding to the line pattern on the film to be processed, and a film to be processed using the resist pattern as a mask. A second step of performing dry etching on the substrate, and the second step uses an etching gas having a side wall protecting effect for protecting the side wall formed on the film to be processed by etching, or has a side wall protecting effect. A method of processing in at least one of the first step and the second step, comprising the step of forming an etching reaction product having The physical condition, the area of the element groups and having a repeating pattern is included in the circuit pattern, adjusted in accordance with the ratio to the area of the arrangement region of the circuit pattern.

  According to the third method for manufacturing a semiconductor integrated circuit device, the first step of forming a resist pattern corresponding to the line pattern, or the second step of performing dry etching on the film to be processed using the resist pattern as a mask. In the process, the processing method or processing conditions are changed in accordance with the ratio of the area of the element group having the repetitive pattern to the area of the arrangement area of the circuit pattern (hereinafter referred to as element group occupation area ratio). Therefore, even when the area of the side wall formed on the film to be processed by etching differs due to the difference in the element group occupation area ratio, that is, the difference in the mask pattern layout, the side wall protection effect per unit area in the second step is improved. The resist pattern dimension can be adjusted in the first step so as to cancel the difference, or the etching conditions can be adjusted in the second step so as to obtain a desired side wall protection effect per unit area. . Therefore, when circuit patterns are formed by lithography technology and dry etching technology, it is possible to prevent the occurrence of dimensional variations due to differences in mask pattern layout, thereby performing highly accurate gate electrode processing or wiring processing, etc. Can do.

  In the third method for manufacturing a semiconductor integrated circuit device, the element group may be a memory such as a DRAM.

  In the third method for fabricating a semiconductor integrated circuit device, the first step preferably includes a step of increasing the size of the resist pattern as the element group occupation area ratio increases.

  In this case, even when the side wall area formed in the film to be processed by etching increases due to an increase in the element group occupation area ratio, the side wall protection effect per unit area decreases in the second step. Since the decrease in the side wall protection effect can be compensated, the dimensional variation of the constituent elements can be reliably suppressed.

  In the third method for manufacturing a semiconductor integrated circuit device, it is preferable that the second step includes a step of setting etching conditions so that the side wall protection effect increases as the element group occupation area ratio increases.

  In this case, even when the area of the side wall formed on the film to be processed by etching increases due to an increase in the element group occupation area ratio, a desired side wall protection effect per unit area can be obtained in the second step. Therefore, the dimensional variation of the constituent elements can be reliably suppressed.

  According to the present invention, even when the mask pattern layout varies greatly depending on the type of the semiconductor integrated circuit device, it is possible to prevent the dimensional variation from occurring in the line pattern due to the difference in the mask pattern layout. Therefore, even in a system LSI in which the mounting rate of DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode or metal wiring can be made constant regardless of the mask pattern layout, so that the semiconductor integrated circuit in which the variation in operation margin is eliminated A device can be realized.

(First embodiment)
Hereinafter, a semiconductor integrated circuit device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. The method for manufacturing a semiconductor integrated circuit device according to the first embodiment includes a circuit pattern having a line pattern, and for manufacturing a plurality of semiconductor integrated circuit devices that share at least a part of the manufacturing process. A manufacturing method of a semiconductor integrated circuit device is assumed.

  A feature of the first embodiment is that a dummy pattern is inserted in an arrangement region of a circuit pattern having a line-shaped pattern, whereby the total peripheral length per unit area of the line-shaped pattern and the dummy pattern is within a predetermined range. It is set to.

  FIG. 1 shows an example of a circuit pattern layout before inserting a dummy pattern in the semiconductor integrated circuit device according to the first embodiment. FIG. 2 shows a dummy pattern in the semiconductor integrated circuit device according to the first embodiment. An example of the layout of the circuit pattern after insertion is shown. 1 and 2 show the circuit pattern of the logic circuit. In the first embodiment, in addition to the logic circuit, a memory circuit such as a RAM or a ROM may be mounted on the chip. Good.

  As shown in FIG. 1, the circuit pattern is composed of an active region pattern 1 and a gate electrode pattern 2 of a MOS transistor. Further, as shown in FIG. 2, a strip-like or linear gate electrode dummy pattern 4 is inserted into an empty region 3 where the active region pattern 1 and the gate electrode pattern 2 are not provided.

In this way, the peripheral length of the gate electrode can be increased without increasing the chip area. Specifically, in the circuit pattern before inserting the dummy pattern shown in FIG. 1, the peripheral length of the gate electrode per unit area is 500 mm / mm ² , whereas the circuit pattern after inserting the dummy pattern shown in FIG. In FIG. ² , the peripheral length of the gate electrode per unit area is increased to 1600 mm / mm ² . That is, in the first embodiment, a result of a small occupation area ratio of a DRAM or ROM or the like in which gate electrode patterns are densely packed before insertion of a dummy pattern (or a result of no DRAM or ROM or the like being mounted). ) The peripheral length of the gate electrode per unit area was as small as 500 mm / mm ² . Therefore, in order to bring the gate electrode peripheral length per unit area of the gate electrode pattern 2 in the circuit pattern shown in FIG. 1 closer to the gate electrode peripheral length per unit area in other varieties having a large DRAM or ROM mounting ratio, FIG. As shown in FIG. 5, the gate electrode peripheral length per unit area of the gate electrode pattern 2 and the gate electrode dummy pattern 4 is greatly increased to 1600 mm / mm ² by inserting a large amount of the gate electrode dummy pattern 4. ing.

By the way, the variation in CD loss caused by the gate electrode processing process (specifically, gate electrode etching) due to the difference in the peripheral length of the gate electrode per unit area varies depending on the size measurement or reticle manufacturing. In order to suppress to 0 to 0.003 μm, it is necessary to suppress the difference in the peripheral length of the gate electrode per unit area in the range of about 500 mm / mm ² (see FIG. 10).

On the other hand, in the system LSI, the mounting rate of DRAMs or ROMs or the like in which gate electrode patterns are densely varies greatly depending on the product type. As a result, the peripheral length of the gate electrode per unit area varies greatly from product to product type. Here, the peripheral length of the gate electrode per unit area becomes the maximum in a general-purpose DRAM having a DRAM cell in which the gate electrode patterns are most dense, and the value is about 2500 mm / mm ² .

Therefore, in order to suppress the difference by varieties of the gate electrode periphery length per unit area in the range of about 500 mm / mm ^2, the standard range (predetermined range) may be set with 2000~2500mm / mm ² approximately . However, depending on the layout before inserting the dummy pattern, there may be a variety in which the dummy pattern cannot be inserted so as to satisfy the peripheral length of the gate electrode per unit area of 2000 mm / mm ² . Actually, it can be assumed that a system LSI on which DRAM is mounted with an occupation area ratio of 70% or more does not occur. Therefore, in this embodiment, 2000 mm / mm ² corresponding to the case where the DRAM occupation area ratio is 80% is set as the upper limit of the standard range of the peripheral length of the gate electrode per unit area, and 1600 to 2000 mm / mm ² is set as the unit area. It was set as the standard range of the peripheral edge length of the gate electrode.

  According to the first embodiment, by inserting the gate electrode dummy pattern 4, the peripheral length of the gate electrode per unit area in the entire chip, that is, the gate per unit area of the gate electrode pattern 2 and the gate electrode dummy pattern 4 in total. The electrode peripheral length (when a memory circuit (not shown) is mounted, the gate electrode peripheral length per unit area including other gate electrode patterns included therein) can be set within a predetermined range. Specifically, it is desirable to assume a gate electrode peripheral length per unit area of the memory circuit, that is, 70 to 100% of the largest gate electrode peripheral length per unit area as the predetermined range. At this time, in order to satisfy the standard, the peripheral length per unit area of the gate electrode dummy pattern 4 to be inserted (for example, the value obtained by dividing the peripheral length of the gate electrode dummy pattern 4 by the area of the empty region 3) ) Needs to be 70% or more of the peripheral length of the gate electrode per unit area of the memory circuit. In this way, even when the mask pattern layout varies greatly depending on the type of semiconductor integrated circuit device, the peripheral length of the gate electrode per unit area in the entire chip can be reliably set within a predetermined range. For example, since a specific circuit such as a memory circuit has a large gate electrode peripheral length per unit area, the gate electrode peripheral length per unit area in the entire chip greatly affects. Even when the area occupied by a specific circuit in a chip varies depending on the type, the dummy pattern is used as described above to suppress variations in the peripheral length of the gate electrode per unit area in the entire chip. it can. As a result, it is possible to prevent dimensional variations from occurring due to differences in the mask pattern layout. That is, the gate electrode pattern 2 can always be etched accurately with a constant dimension. Therefore, even in a system LSI in which the mounting rate of a DRAM or the like varies depending on the application or specification, the processing dimension of the gate electrode pattern 2 can be made constant regardless of the mask pattern layout. realizable.

In the first embodiment, the method of processing the gate electrode pattern 2 is not particularly limited. For example, a parallel plate RIE (reactive ion etching) apparatus is used and main dry etching is performed. By etching the polysilicon film by setting the Cl ₂ gas flow rate as 0.04 SLM (Standard Litter per Minute), the HBr gas flow rate as 0.08 SLM, the pressure as 20 Pa, and the RF power as 300 W as conditions, The gate electrode pattern 2 may be formed.

  In the first embodiment, the peripheral length per unit area of the line pattern constituting the circuit pattern such as the gate electrode pattern may be set within a predetermined range without using the dummy pattern.

  In the first embodiment, the gate electrode processing is targeted, but the present invention is not limited to this, and the target is microfabrication of a layer having another line pattern, for example, processing of a metal wiring made of aluminum or copper. The same high processing accuracy can be achieved.

(Second Embodiment)
A method for manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention will be described below with reference to the drawings. The method for manufacturing a semiconductor integrated circuit device according to the second embodiment includes a circuit pattern having a line pattern, and for manufacturing a plurality of semiconductor integrated circuit devices that share at least a part of the manufacturing process. A manufacturing method of a semiconductor integrated circuit device is assumed.

  The feature of the second embodiment is that the ratio between the number of exposure shots for transferring a circuit pattern having a line pattern and the number of exposure shots for transferring a dummy pattern is adjusted on a wafer to be exposed. By doing this, the total peripheral length per unit area of all the transferred linear patterns and all the transferred dummy patterns is set within a predetermined range.

  FIG. 3A shows an example of a pattern exposure shot map in a lithography process for forming a polysilicon gate electrode pattern in the method for manufacturing a semiconductor integrated circuit device according to the second embodiment. (B) shows an example of a dummy pattern used in the lithography process.

  In the method of manufacturing a semiconductor integrated circuit device according to the second embodiment, as shown in FIG. 3A, the number of first exposure regions 11 to which each circuit pattern is transferred (that is, to transfer the circuit pattern). And the number of second exposure regions 12 onto which the dummy patterns are transferred (that is, the number of exposure shots for transferring the dummy patterns) are adjusted on the wafer 10. Further, in each second exposure region 12, as shown in FIG. 3B, strip-like dummy patterns 13 composed of, for example, 0.2 μm wide lines and 0.2 μm wide spaces are simply laid. So that it is transcribed.

  Accordingly, for example, the peripheral length of the gate electrode per unit area on the wafer 10, that is, the total per unit area of the gate electrode pattern included in all the circuit patterns to be transferred and all the dummy patterns 13 to be transferred. The peripheral length of the gate electrode can be suppressed to a certain range that does not depend on the mask pattern layout of the semiconductor integrated circuit device, that is, the mask pattern layout corresponding to the circuit pattern.

  Specifically, in the present embodiment, a dummy reticle mask for transferring the dummy pattern 13 is used separately from the circuit pattern forming reticle mask, so that the entire wafer 10 is compared with the first embodiment. It is possible to further increase the peripheral length of the gate electrode per unit area.

Further, in the present embodiment, the second exposure region 12 is formed on the wafer 10 so that the peripheral length of the gate electrode per unit area of the entire wafer 10 is, for example, in the range of 1600 to 2000 mm / mm ² as in the first embodiment. The area ratio A occupying 10 can be calculated as follows. However, the peripheral length per unit area of the dummy pattern transferred to each second exposure region 12 is, for example, 5000 mm / mm ² , and the gate per unit area in the circuit pattern transferred to each first exposure region 11. It is assumed that the electrode peripheral length is, for example, 500 mm / mm ² .

That is,
1600 ≦ 5000 × A + 500 × (1-A) ≦ 2000
Since the relational expression of
0.244 ≦ A ≦ 0.333
It becomes. Thus, it is necessary to set the number of exposure shots for transferring the dummy pattern so that the area ratio of the second exposure region 12 on the wafer 10 is about 24.5% or more. Specifically, in the present embodiment, as shown in FIG. 3A, a first exposure region 11 for circuit pattern transfer is provided in an area of 3/4 (75%) on the wafer 10. The second exposure region 12 for transferring the dummy pattern is provided in the remaining 1/4 (25%) area on the wafer 10.

  According to the second embodiment, the ratio between the number of exposure shots for circuit pattern transfer and the number of exposure shots for dummy pattern transfer is set so that the peripheral length of the gate electrode per unit area in the entire wafer 10 is set within a predetermined range. adjust. Therefore, even when the mask pattern layout varies greatly depending on the type of semiconductor integrated circuit device, it is possible to prevent the dimensional variation in the gate electrode pattern due to the difference in the mask pattern layout. Therefore, even in system LSIs where the mounting rate of DRAM, etc. varies depending on the application or specifications, the processing dimensions of the gate electrode pattern can be made constant regardless of the mask pattern layout, thereby realizing a semiconductor integrated circuit device that eliminates variations in operation margins. it can.

  In the second embodiment, the peripheral length per unit area of the dummy pattern is preferably 70% or more of the peripheral length of the gate electrode per unit area in the memory circuit mounted on the semiconductor integrated circuit device.

  In the second embodiment, the circuit pattern is transferred so that the gate electrode peripheral length per unit area in the entire wafer is set to 70 to 100% of the gate electrode peripheral length per unit area in the memory circuit. It is preferable to adjust the ratio between the number of exposure shots for transferring the number of exposure shots for transferring the dummy pattern.

  In the second embodiment, the gate electrode processing is targeted, but the present invention is not limited to this, and the target is microfabrication of a layer having another line pattern, for example, processing of a metal wiring made of aluminum or copper. The same high processing accuracy can be achieved.

(Third embodiment)
A method for manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention will be described below with reference to the drawings. The method for manufacturing a semiconductor integrated circuit device according to the third embodiment includes a circuit pattern having a line pattern, and is used for manufacturing a plurality of semiconductor integrated circuit devices that share at least a part of the manufacturing process. A manufacturing method of a semiconductor integrated circuit device is assumed.

  The feature of the third embodiment is that dry etching is performed on the film to be processed while adjusting the dry etching conditions according to the peripheral length per unit area of the line pattern constituting the circuit pattern. Hereinafter, a case will be described as an example where the size dependency of the gate electrode pattern on the mask pattern layout of the semiconductor integrated circuit device is suppressed by selecting the dry etching conditions for forming the gate electrode pattern.

FIG. 4 is a diagram showing parameters of the gate electrode peripheral length per unit area on a chip when a polysilicon gate electrode pattern is formed by dry etching in manufacturing a plurality of types of semiconductor integrated circuit devices in which circuits of various layouts are incorporated. Parameter S1: 600 mm / mm ² , parameter S2: 1000 mm / mm ² , parameter S3: 1400 mm / mm ² , parameter S4 : 1800 mm / mm ² ), the relationship between the flow rate of the dry etching gas and the CD loss of the gate electrode pattern It is a graph which shows the result calculated | required by experiment. Here, the experimental results shown in FIG. 4 are obtained by using a mixed gas of HBr and Cl ₂ and a cooling gas such as He as the etching gas and making the gas flow rate of HBr out of the mixed gas variable. It is what was done.

  As shown in FIG. 4, even if the HBr gas flow rate is the same, if the peripheral length of the gate electrode per unit area is different, the CD loss of the gate electrode pattern is also changed accordingly. On the other hand, if the HBr gas flow rate is changed for any value of the peripheral length of the gate electrode per unit area, the CD loss can be made substantially zero at a specific flow rate.

  Therefore, in the method of manufacturing a semiconductor integrated circuit device according to the third embodiment, the peripheral length of the gate electrode per unit area in the circuit pattern of each semiconductor integrated circuit device is obtained in advance, and at the same time as shown in FIG. The relationship between dry etching conditions and CD loss is experimentally determined. Then, with respect to the obtained gate electrode peripheral length per unit area, dry etching conditions such that the CD loss of the gate electrode pattern is substantially zero to the extent permitted by design (HBr gas flow rate in FIG. 4). In other words, dry etching conditions are selected such that the dimension of the gate electrode pattern is equal to the target dimension determined by design, and dry etching is performed on the polysilicon film serving as the gate electrode.

  By the way, for example, in the manufacture of a plurality of types of semiconductor integrated circuit devices on which a memory circuit and a logic circuit are mounted, the method described above is used when the target dimension of the processing pattern is the same for each type but the layout is greatly different. In principle, accurate pattern etching can be performed regardless of the layout. However, in practice, it is not preferable in terms of mass productivity to obtain the dry etching conditions for each type having different layouts, that is, to change the dry etching conditions for each type.

  Therefore, in this embodiment, the gate electrode peripheral length per unit area is divided into a plurality of ranges, and one dry etching condition is set for each gate electrode peripheral length per unit area in each range. Also good.

  [Table 1] shows the optimum conditions of the dry etching process for each range of the peripheral length of the gate electrode per unit area when the polysilicon gate electrode pattern is formed by dry etching.

［表１］に示すように、単位面積当たりのゲート電極周縁長を複数の範囲に区切って、各範囲毎に異なるドライエッチング条件（具体的には異なるＨＢｒガス流量）が適用されている。［表１］に示すドライエッチング条件を用いた場合、図４との対応関係から明らかなように、単位面積当たりのゲート電極周縁長の各範囲（Ｓ１〜Ｓ４）に対してゲート電極パターンのＣＤロスがほぼ０±０．００２μｍ以内の小さい値に収まっている。これにより、０．１μｍ以下の設計ルールのデバイスの製造においても十分なパターン精度を得ることができる。

As shown in [Table 1], the gate electrode peripheral length per unit area is divided into a plurality of ranges, and different dry etching conditions (specifically, different HBr gas flow rates) are applied to each range. When the dry etching conditions shown in [Table 1] are used, as is clear from the correspondence with FIG. 4, the CD of the gate electrode pattern for each range (S1 to S4) of the peripheral length of the gate electrode per unit area (S1 to S4). The loss is within a small value within about 0 ± 0.002 μm. Thereby, sufficient pattern accuracy can be obtained even in the manufacture of a device having a design rule of 0.1 μm or less.

  That is, according to the third embodiment, the dry etching is performed on the polysilicon film while adjusting the dry etching conditions for the polysilicon film serving as the gate electrode according to the peripheral length of the gate electrode per unit area. Even when the mask pattern layout varies greatly depending on the type of semiconductor integrated circuit device, the dimensions of the gate electrode pattern can always be made equal to a predetermined value. Therefore, even in a system LSI in which the mounting rate of DRAM or the like varies depending on the application or specification, the processing dimension of the gate electrode can be made constant regardless of the mask pattern layout, so that it is possible to realize a semiconductor integrated circuit device in which variation in operation margin is eliminated. .

  Further, according to the third embodiment, the gate electrode peripheral length per unit area is divided into a plurality of ranges, and one dry etching condition is set for each range. Compared with the case of changing, the dry etching conditions can be easily adjusted.

  In the third embodiment, the CD loss of the gate electrode pattern is controlled by adjusting the HBr gas flow rate in the dry etching for forming the polysilicon gate electrode. It is possible to set the optimum dry etching conditions by adjusting the flow rate, the etching gas pressure, or the RF power of the dry etching apparatus.

  In the third embodiment, when an organic coating film that becomes an antireflection film is formed on a polysilicon film that becomes a gate electrode in a lithography process, for example, or a hard mask is formed by, for example, a CVD (Chemical Vapor Deposition) method. In the case where the silicon oxide film or the like to be formed on the polysilicon film to be the gate electrode, the etching conditions for the organic coating film or the CVD silicon oxide film are adjusted instead of the etching conditions for the polysilicon film. May be.

  In the third embodiment, the gate electrode processing is targeted. However, the present invention is not limited to this. Fine processing of a layer having another line pattern, for example, etching processing of metal wiring, or formation of a trench for embedded wiring is formed. The same high processing accuracy can be achieved even when etching the insulating film for the purpose.

(Fourth embodiment)
A semiconductor integrated circuit device manufacturing method according to the fourth embodiment of the present invention will be described below with reference to the drawings. Note that the method for manufacturing a semiconductor integrated circuit device according to the fourth embodiment includes a circuit pattern having a line pattern, and for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of the manufacturing process. A manufacturing method of a semiconductor integrated circuit device is assumed.

  In the third embodiment, the dry etching conditions are adjusted according to the peripheral length per unit area of the line pattern constituting the circuit pattern. On the other hand, the feature of the fourth embodiment is that a resist pattern corresponding to the line pattern constituting the circuit pattern is formed while adjusting the dimension according to the peripheral length per unit area of the line pattern. It is. Hereinafter, an example will be described in which the dimension dependency of the gate electrode pattern on the mask pattern layout of the semiconductor integrated circuit device is suppressed by adjusting the dimension of the resist pattern corresponding to the gate electrode pattern.

Specifically, in the fourth embodiment, when a polysilicon gate electrode pattern is formed by dry etching in the manufacture of a plurality of types of semiconductor integrated circuit devices incorporating various layout circuits, HBr is used as an etching gas. In addition, a mixed gas of Cl ₂ and a cooling gas such as He is used, and the gas flow rate of HBr in the mixed gas is fixed to 0.07 SLM. That is, in the fourth embodiment, the dry etching conditions are the same as the recipe No. shown in [Table 1] of the third embodiment. Fix to PS3 dry etching conditions (standard conditions). When the dry etching conditions are fixed in this way, for example, as shown in FIG. 4 of the third embodiment, the value of the CD loss of the gate electrode pattern varies depending on the mask pattern layout.

  Therefore, in the method of manufacturing a semiconductor integrated circuit device according to the fourth embodiment, first, the relationship between the gate electrode peripheral length per unit area in the circuit pattern of each semiconductor integrated circuit device and the CD loss of the gate electrode pattern is obtained. deep. Then, in order to compensate for the obtained CD loss size, that is, the pattern dimension change that occurs depending on the peripheral length of the gate electrode per unit area, the dimension of the resist pattern serving as a dry etching mask can be changed to a photo, such as an exposure amount, for example. Adjust according to lithography conditions.

  [Table 2] shows the gate electrode pattern for each range of the peripheral length of the gate electrode per unit area when a resist pattern corresponding to the polysilicon gate electrode pattern is formed and dry etching is performed using the resist pattern. Each of the CD loss (A), the target dimension (B) in the photolithography process, and the design dimension (C) of the gate electrode pattern after dry etching is shown.

［表２］において、ＣＤロス（Ａ）は［表１］に示すレシピＮｏ．ＰＳ３のドライエッチング条件を用いた場合の値である。また、目標寸法（Ｂ）は、前述のようにＣＤロス（Ａ）の大きさを考慮して調整されたレジストパターンの最適寸法である。また、本実施形態においては、設計寸法（Ｃ）を０．１５０μｍとしている。

In [Table 2], CD loss (A) is the recipe No. shown in [Table 1]. This is the value when PS3 dry etching conditions are used. The target dimension (B) is the optimum dimension of the resist pattern adjusted in consideration of the CD loss (A) as described above. In the present embodiment, the design dimension (C) is 0.150 μm.

here,
Target dimension (B) = CD loss (A) + design dimension (C)
Therefore, the target dimension (B), that is, the value of the optimum dimension of the resist pattern as shown in [Table 2] can be specifically set by using the relational expression. In other words, by adjusting the target dimension (B) in the photolithography process, it becomes possible to cancel the adjustment amount and the CD loss (A).

  In this embodiment, the design dimension (C) is 0.150 μm, and the dry etching conditions are recipe Nos. Shown in [Table 1]. Paying attention to PS3 (HBr gas flow rate: 0.07 SLM), for example, each range of gate electrode peripheral length per unit area (S1 to S4) when the HBr gas flow rate is 0.07 SLM in FIG. The target dimension (B) in the photolithography process can also be easily set by reading the CD loss corresponding to. In this embodiment, the recipe No. shown in [Table 1] is used as the dry etching condition. PS3 is used for the following reason. That is, as apparent from [Table 2], the recipe No. When PS3 is used, the amount of adjustment of the target dimension (B) corresponding to the size of the CD loss (A) is the largest with respect to the peripheral length of the gate electrode per unit area realized in each type of semiconductor integrated circuit device. This is because it becomes smaller.

  As described above, according to the fourth embodiment, the resist pattern corresponding to the gate electrode pattern is formed while adjusting the dimension according to the peripheral length of the gate electrode per unit area. Even when the mask pattern layout varies greatly depending on the type of the product, the dimension of the gate electrode pattern can always be equal to the predetermined value. Therefore, even in a system LSI in which the mounting rate of DRAM or the like varies depending on the application or specification, the processing dimension of the gate electrode can be made constant regardless of the mask pattern layout, so that it is possible to realize a semiconductor integrated circuit device in which variation in operation margin is eliminated. .

  In the fourth embodiment, for adjusting the target dimension in the photolithography process, that is, adjusting the dimension of the resist pattern corresponding to the gate electrode pattern, for example, the most effective method is to increase or decrease the exposure amount in the exposure of the resist film. Convenient. Moreover, you may correct | amend dimensions, such as a light shielding pattern (for example, chromium pattern) on a photomask. In this case, it is not necessary to increase or decrease the exposure amount, which is advantageous in the operation of the manufacturing process.

  In the fourth embodiment, the gate electrode processing is targeted, but the present invention is not limited to this, and the microfabrication of a layer having another line pattern, for example, processing of a metal wiring made of aluminum or copper is targeted. The same high processing accuracy can be achieved.

(Fifth embodiment)
Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment of the present invention will be described with reference to the drawings. Note that the method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment includes a circuit pattern having a line pattern, and for manufacturing a plurality of semiconductor integrated circuit devices in which at least a part of the manufacturing process is common. A manufacturing method of a semiconductor integrated circuit device is assumed. Further, in the following description, a method for forming a gate electrode in a system LSI capable of mounting a memory having a repetitive pattern such as a DRAM is taken as an example.

  FIGS. 5A to 5D are cross-sectional views showing respective steps of a method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment.

  First, as shown in FIG. 5A, a silicon oxide film 22 having a thickness of about 5 nm serving as a gate insulating film is formed on a silicon substrate 21, and then a thickness serving as a gate electrode is formed on the silicon oxide film 22. A polysilicon film 23 having a thickness of about 200 nm is formed, and then an organic coating film 24 having a thickness of about 100 nm is formed on the polysilicon film 23 as a light reflection preventing film in the lithography process (see FIG. 5B). .

  Next, as shown in FIG. 5B, the minimum line width (gate) corresponding to the gate electrode 26 having a line pattern (see FIG. 5D) is formed on the organic coating film 24 by using a lithography technique. A resist pattern 25 (thickness is about 600 nm) of 0.15 μm is formed.

  Next, as shown in FIG. 5C, dry etching is performed on the organic coating film 24 using the resist pattern 25 as a mask.

In this case, when the semiconductor integrated circuit device is a DRAM not mounted varieties, for example, into the chamber the pressure is set to 10 Pa, an etching gas comprising a mixed gas of SO ₂ gas and O ₂ gas, the SO ₂ gas The flow rate is 20 cc / min, the flow rate of O ₂ gas is introduced at a flow rate ratio of 20 cc / min, and 200 W high frequency power (RF power) is applied to the sample stage to perform dry etching. When the semiconductor integrated circuit device is a DRAM-equipped product, for example, an etching gas made of a mixed gas of SO ₂ gas and O ₂ gas is introduced into a chamber set at a pressure of 10 Pa, and the flow rate of SO ₂ gas: Introducing at a flow rate ratio of 25 cc / min, O ₂ gas flow rate: 20 cc / min, high-frequency power of 200 W is applied to the sample stage to perform dry etching. In the present embodiment, the gas flow rate is expressed using the flow rate per minute in the standard state (0 ° C., 1 atm).

That is, in the dry etching process for the organic coating film 24, the etching conditions are changed depending on whether or not the DRAM is mounted. Specifically, in the case of a product equipped with DRAM, the flow rate of SO ₂ gas having an effect of protecting the side wall formed on the organic coating film 24 by etching is changed from 20 cc / min in the product not equipped with DRAM to 25 cc / min. And increase. Thereby, even when the area of the side wall of the organic coating film 24 is increased by mounting the DRAM, the desired side wall protection effect per unit area can be obtained. Can be patterned to have the desired dimensions (0.15 μm).

  Next, after the dry etching is performed on the polysilicon film 23 using the resist pattern 25 or the patterned organic coating film 24 as a mask, the resist pattern 25 and the organic coating film are formed as shown in FIG. 24 is removed by ashing, and a gate electrode 26 made of the polysilicon film 23 is formed. At this time, since the organic coating film 24 is patterned so as to have a desired dimension regardless of whether or not the DRAM is mounted, the occurrence of CD loss is prevented, and the gate electrode 26 having a desired dimension (0.15 μm). Can be formed.

Incidentally, in the dry etching process for the polysilicon film 23, for example, in a chamber in which the pressure is set to 20 Pa, Cl ₂ gas and HBr gas are mixed in the DRAM non-loading type or the DRAM mounting type. An etching gas composed of a mixed gas is introduced at a flow rate ratio of Cl ₂ gas: 40 cc / min and HBr gas: 80 cc / min, and high-frequency power of 300 W is applied to the sample stage to perform dry etching. . That is, different equipment and conditions are used in the dry etching process for each of the polysilicon film 23 and the organic coating film 24.

As described above, according to the fifth embodiment, whether or not DRAM is mounted in the step of dry etching the organic coating film 24 using the resist pattern 25 corresponding to the gate electrode 26 having a line pattern as a mask. The etching conditions are changed according to the conditions. Specifically, the flow rate of SO ₂ gas having an effect of protecting the side wall formed on the organic coating film 24 by etching is increased in the case of the DRAM mounted product type as compared with the case of the DRAM non-installed product type. For this reason, even when the area of the side wall of the organic coating film 24 is increased by mounting the DRAM, the desired side wall protection effect per unit area can be obtained, so that the organic coating film 24 has a desired size. Can be patterned. Therefore, by performing dry etching on the polysilicon film 23 using the patterned organic coating film 24 as a mask, the gate electrode 26 having a desired dimension can be formed. That is, the dimensional variation of the gate electrode 26 due to the difference in the mask pattern layout depending on whether or not the DRAM is mounted can be surely suppressed, and thereby accurate gate electrode processing can be performed.

  FIG. 6 shows CD loss (resist before etching) in the case where varieties having various DRAM occupation area ratios including varieties not equipped with DRAM are manufactured by using the method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment. A value obtained by subtracting the dimension of the completed gate electrode from the dimension of the pattern) and the DRAM occupation area ratio are shown.

  As shown in FIG. 6, according to the fifth embodiment, it was possible to realize the desired gate electrode size of 0.15 μm by suppressing the occurrence of CD loss regardless of whether or not DRAM is mounted.

  FIG. 7 shows the CD loss and the DRAM occupied area ratio when a variety of DRAM occupied area ratios including those not equipped with DRAM are manufactured using the same etching conditions regardless of whether or not the DRAM is mounted as a comparative example. Shows the relationship.

  As shown in FIG. 7, according to the comparative example, generation of CD loss can be suppressed in the products not equipped with DRAM, while CD loss of about +0.013 μm on average occurs in the products equipped with DRAM.

In the fifth embodiment, the etching condition of the organic coating film 24 (specifically, the flow rate of SO ₂ gas having an effect of protecting the side wall of the organic coating film 24) is changed according to whether or not the DRAM is mounted. The etching conditions for the polysilicon film 23 are made common regardless of whether or not the DRAM is mounted. Instead, the etching conditions for the organic coating film 24 are made common regardless of whether or not the DRAM is mounted. The etching conditions for the polysilicon film 23 may be changed according to the above. At this time, for example, the flow rate of HBr gas for forming an etching reaction product (SiBr ₄ or the like) having an effect of protecting the side wall of the polysilicon film 23 as the side wall protective film is changed depending on whether or not the DRAM is mounted. Also good. When a structure in which a silicon oxide film or the like is formed on a polysilicon film is adopted as the gate electrode structure, the gate electrode resulting from the presence or absence of DRAM mounting can be changed by changing the etching conditions of the silicon oxide film. The dimensional variation of the may be suppressed.

  In the fifth embodiment, the etching conditions are changed according to whether or not the DRAM is mounted. Instead, the etching conditions may be finely changed according to the DRAM occupation area ratio.

  In the fifth embodiment, the formation of the gate electrode is targeted. However, the present invention is not limited to this, and the formation of another line pattern such as a metal wiring may be targeted.

  In the fifth embodiment, a system LSI capable of mounting a memory such as a DRAM is targeted. However, the present invention is not limited to this, and other element groups in which a plurality of semiconductor elements are arranged so as to have a repeating pattern are provided. It is also possible to target system LSIs that can be mounted.

(Sixth embodiment)
A semiconductor integrated circuit device manufacturing method according to the sixth embodiment of the present invention will be described below with reference to the drawings. Note that the method for manufacturing a semiconductor integrated circuit device according to the sixth embodiment includes a circuit pattern having a line pattern, and for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of the manufacturing process. A manufacturing method of a semiconductor integrated circuit device is assumed. Further, in the following description, a method for forming a gate electrode in a system LSI capable of mounting a memory having a repetitive pattern such as a DRAM is taken as an example. Furthermore, sectional views showing respective steps of the method of manufacturing the semiconductor integrated circuit device according to the sixth embodiment are shown in FIGS. 5A to 5D, similarly to the fifth embodiment.

  The sixth embodiment is different from the fifth embodiment as follows. That is, in the fifth embodiment, a step of performing dry etching on the organic coating film 24 using the resist pattern 25 corresponding to the gate electrode 26 having a line pattern as a mask (see FIGS. 5C and 5D). The etching conditions were changed depending on whether DRAM was installed. On the other hand, in the sixth embodiment, in the step of forming the resist pattern 25 (see FIG. 5B), the dimension of the resist pattern 25 is changed according to the DRAM occupation area ratio.

Specifically, in the sixth embodiment, for example, as shown in FIG. 7, the CD loss (the value obtained by subtracting the dimension of the completed gate electrode from the dimension of the resist pattern before etching) and the DRAM occupation area ratio By acquiring the relationship in advance, for example, the following formula (resist pattern dimensions)
= (DRAM occupation area ratio and corresponding CD loss prediction value)
+ (Target size of gate electrode)
Is used to set the dimension of the resist pattern.

  As shown in FIG. 7, the CD loss increases as the DRAM occupation area ratio increases. Therefore, according to the above formula, the dimension of the resist pattern 25 is increased as the DRAM occupation area ratio increases. If it does in this way, the following effects will be acquired in a 6th embodiment. That is, the side wall area formed on the polysilicon film 23 or the organic coating film 24 by etching using the resist pattern 25 as a mask increases due to an increase in the area ratio occupied by the DRAM, and the side wall protection effect per unit area decreases. Even in this case, the decrease in the side wall protection effect can be compensated by adjusting the dimensions of the resist pattern 25. Therefore, the dimensional variation of the gate electrode 26 caused by the difference in the mask pattern layout accompanying the difference in the DRAM occupation area ratio can be surely suppressed, and thereby the gate electrode can be processed with high accuracy.

  [Table 3] shows a target size of 0.15 μm in the case of manufacturing a variety of DRAM occupied area ratios including a non-DRAM mounted type using the method of manufacturing a semiconductor integrated circuit device according to the sixth embodiment. The dimensions of the resist pattern for forming the gate electrode are shown. For reference, in [Table 3], the estimated value of the CD loss corresponding to each DRAM occupation area ratio is shown.

レジストパターン２５の寸法を［表３］に示すように設定することによって、第６の実施形態において、ＤＲＡＭ占有面積率に関わらず、所望のゲート電極寸法である０．１５μｍを実現することができた。

By setting the dimensions of the resist pattern 25 as shown in [Table 3], in the sixth embodiment, a desired gate electrode dimension of 0.15 μm can be realized regardless of the DRAM occupation area ratio. It was.

  In the sixth embodiment, the dimension of the resist pattern 25 is changed according to the DRAM occupation area ratio. However, instead of this, the dimension of the resist pattern 25 may be changed roughly according to whether or not the DRAM is mounted. .

  In the sixth embodiment, as a specific method for adjusting the size of the resist pattern 25, for example, a method for adjusting the exposure amount, a method for adjusting the mask pattern size on the reticle, or the like may be used.

  In the sixth embodiment, the formation of the gate electrode is targeted. However, the present invention is not limited to this, and the formation of another line pattern, such as a metal wiring, may be targeted.

  In the sixth embodiment, a system LSI capable of mounting a memory such as a DRAM is targeted. However, the present invention is not limited to this, and other element groups in which a plurality of semiconductor elements are arranged so as to have a repetitive pattern are provided. It is also possible to target system LSIs that can be mounted.

  The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and is applied to the formation of a line pattern such as a gate electrode of a MOS transistor in a system LSI capable of mounting an element group having a fine repetitive pattern such as a DRAM. It is particularly useful.

It is a figure which shows an example of the layout of the circuit pattern before dummy pattern insertion in the semiconductor integrated circuit device which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the layout of the circuit pattern after dummy pattern insertion in the semiconductor integrated circuit device which concerns on the 1st Embodiment of this invention. (A) is a figure which shows an example of the pattern exposure shot map in the lithography process for forming a polysilicon gate electrode pattern in the manufacturing method of the semiconductor integrated circuit device which concerns on the 2nd Embodiment of this invention, ( b) is a diagram showing an example of a dummy pattern used in the lithography process. When a polysilicon gate electrode pattern is formed by dry etching in the manufacture of a plurality of types of semiconductor integrated circuit devices, the flow rate of the dry etching gas and the CD of the gate electrode pattern are measured using the peripheral length of the gate electrode per unit area on the chip as a parameter. It is a figure which shows the result of having calculated | required the relationship with loss by experiment. (A)-(d) is sectional drawing which shows each process of the manufacturing method of the semiconductor integrated circuit device which concerns on the 5th or 6th Embodiment of this invention. Using the method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment of the present invention, the CD loss and the DRAM occupied area ratio in the case of manufacturing a variety of DRAM occupied area ratios including those not equipped with DRAMs. It is a figure which shows the relationship. As a comparative example, the relationship between the CD loss and the DRAM occupied area ratio in the case of manufacturing a variety of DRAM occupied area ratios including those not equipped with DRAM using the same etching conditions regardless of whether or not the DRAM is mounted. FIG. It is a figure which shows frequency distribution of CD loss at the time of manufacturing the DRAM mounting | wearing type | mold with which DRAM was mounted, and the DRAM non-mounting | wearing type | mold each using the same gate electrode processing process. It is a figure which shows the relationship between the gate electrode peripheral length per unit area and DRAM occupation area ratio in the kind which has various DRAM occupation area ratios including DRAM non-mounting kind. It is a figure which shows the relationship between the gate electrode peripheral length per unit area and CD loss in various varieties.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Active area pattern 2 Gate electrode pattern 3 Empty area 4 Gate electrode dummy pattern 10 Wafer 11 1st exposure area 12 2nd exposure area 13 Dummy pattern 21 Silicon substrate 22 Silicon oxide film 23 Polysilicon film 24 Organic coating film 25 Resist Pattern 26 Gate electrode

Claims (11)

A method of manufacturing a semiconductor integrated circuit device for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a line-shaped pattern and sharing at least a part of a manufacturing process,
Using the peripheral length per unit area of the line pattern as a parameter, a step of obtaining a relationship between dry etching conditions and CD loss, which is a difference between the dimension of the resist pattern before etching and the dimension of the completed line pattern ( a) and
After the step (a), dry etching is performed on the film to be processed by selecting a dry etching condition in which the CD loss is within a desired value according to the peripheral length per unit area of the line pattern. and a step (b) only contains,
In the step (b), the gas flow rate of one etching gas under the dry etching conditions, the total flow rate of all etching gases, the etching gas pressure, or the RF of the dry etching apparatus so that the CD loss is within a desired value. A method of manufacturing a semiconductor integrated circuit device, wherein any one of powers is adjusted . In the manufacturing method of the semiconductor integrated circuit device according to claim 1 ,
The step (b) includes a step of setting one dry etching condition when the peripheral length per unit area of the line pattern is within one range. . In the manufacturing method of the semiconductor integrated circuit device according to claim 1 or 2 ,
The method of manufacturing a semiconductor integrated circuit device, wherein the desired value is within 0 ± 0.002 μm. A method of manufacturing a semiconductor integrated circuit device for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a line-shaped pattern and sharing at least a part of a manufacturing process,
A step (a) for determining a relationship between a peripheral length per unit area of the line-shaped pattern and a CD loss which is a difference between a dimension of the resist pattern before etching and a dimension of the completed line-shaped pattern;
After the step (a), a step (b) of forming a resist pattern having dimensions adjusted in consideration of the size of the CD loss according to the peripheral length per unit area of the line-shaped pattern;
Look including a step of performing dry etching (c) with respect to the processed film using the resist pattern as a mask,
In the step (b), the dimension of the resist pattern is adjusted by an exposure amount in photolithography . A method of manufacturing a semiconductor integrated circuit device for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a line-shaped pattern and sharing at least a part of a manufacturing process,
A step (a) for determining a relationship between a peripheral length per unit area of the line-shaped pattern and a CD loss which is a difference between a dimension of the resist pattern before etching and a dimension of the completed line-shaped pattern;
After the step (a), a step (b) of forming a resist pattern having dimensions adjusted in consideration of the size of the CD loss according to the peripheral length per unit area of the line-shaped pattern;
And (c) performing dry etching on the film to be processed using the resist pattern as a mask,
In the step (b), the dimension of the resist pattern is adjusted by correcting the dimension of the light shielding pattern on the photomask. A method of manufacturing a semiconductor integrated circuit device for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a line-shaped pattern and sharing at least a part of a manufacturing process,
Forming a resist pattern corresponding to the line pattern on the film to be processed;
Using the resist pattern as a mask, an etching gas having a sidewall protective effect for protecting the sidewall formed on the workpiece film by etching is used for the film to be processed, or an etching reaction product having the sidewall protective effect. And (b) performing dry etching by forming
In the step (a), the exposure amount is adjusted according to the ratio of the area of the element group included in the circuit pattern and having the repeated pattern to the area of the arrangement region of the circuit pattern , or on the reticle. A method of manufacturing a semiconductor integrated circuit device, comprising adjusting a dimension of the resist pattern by using a method for adjusting a mask pattern . The method for manufacturing a semiconductor integrated circuit device according to claim 6,
The step (a) includes a step of increasing the size of the resist pattern as the ratio increases. A method of manufacturing a semiconductor integrated circuit device for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a line-shaped pattern and sharing at least a part of a manufacturing process,
Forming a resist pattern corresponding to the line pattern on the film to be processed;
Using the resist pattern as a mask, an etching gas having a sidewall protective effect for protecting the sidewall formed on the workpiece film by etching is used for the film to be processed, or an etching reaction product having the sidewall protective effect. And (b) performing dry etching by forming
In the step (b), the gas of one etching gas under dry etching conditions according to the ratio of the area of the element group included in the circuit pattern and having the repeated pattern to the area of the arrangement region of the circuit pattern A method for manufacturing a semiconductor integrated circuit device, characterized by adjusting a flow rate . The method of manufacturing a semiconductor integrated circuit device according to claim 8 .
The step (b) includes a step of setting the dry etching conditions so that the side wall protection effect increases as the ratio increases. In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 6 to 9 ,
A method of manufacturing a semiconductor integrated circuit device, wherein the element group is a memory. In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 6 to 9 ,
A method of manufacturing a semiconductor integrated circuit device, wherein the memory is a DRAM.

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