JP4032927B2 - Initialization circuit for large-scale integrated circuits - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an initialization circuit for a large-scale integrated circuit that improves the efficiency of circuit initialization when power is turned on.
[0002]
[Prior art]
As is well known, in a large-scale integrated circuit (hereinafter referred to as LSI), initialization of registers, flip-flops, SRAMs (static RAMs) and the like is necessary when power is turned on. Therefore, in the LSI, a reset signal is input when the power is turned on, and the flip-flop and the like are initialized by the reset signal. By the way, circuit elements such as a shift register and SRAM cannot be initialized only by a reset signal, and require a clock. For example, the SRAM is initialized by sequentially changing addresses according to a clock and writing data “0”. However, when a clock is supplied to the LSI from the outside, the supply of the external clock is often delayed from the reset signal.
[0003]
FIG. 4 is a timing chart showing such a state. In the example shown in this figure, the power supply rises, a reset signal (active L (low)) is input, and after the reset signal rises, a clock is input. As described above, in consideration of the delay of the clock, it is necessary to set the initialization period T1 until a predetermined time after the clock rises as shown in the figure. For this reason, the conventional LSI takes time for initialization, and has a drawback that it is necessary to make a peripheral circuit in consideration of initialization.
[0004]
As a conventional initialization circuit, one disclosed in Patent Document 1 is known. The initialization circuit described in this document is intended to prevent an abnormal current at the time of initialization, and the internal state is initialized using a one-shot pulse generation circuit. However, this initialization circuit cannot be applied to a circuit (for example, a shift register) that requires a clock that is continuous for initialization, and the internal address counter is operated to initialize the SRAM or the like. I can't do that either.
[0005]
[Patent Document 1]
Japanese Laid-Open Patent Publication No. 3-1167772
[Problems to be solved by the invention]
The present invention has been made in consideration of such circumstances, and the purpose thereof is an LSI (large scale) that can be initialized in a short time without requiring any special device for initialization. It is to provide an initialization circuit of an integrated circuit.
[0008]
[Means for Solving the Problems]
The present invention has been made to solve the above problems, the invention according to claim 1 is activated powered on at the same time, it generates a clock for initialization, after receiving the switching signal from the outside a clock generating circuit for generating a normal operation clock synchronized to an external clock, power outputs pre Symbol for Initial forming clock to the individual circuit components in the time of turn-on, after receiving the switching signal from the outside before SL through normal Switching means for outputting an operation clock to each part of the circuit , the clock generation circuit having a voltage controlled oscillator and generating the normal operation clock by a PLL, and the voltage controlled oscillator And an initialization clock generation circuit for generating the initialization clock by using an initialization circuit for a large-scale integrated circuit.
According to a second aspect of the present invention, there is provided a first frequency dividing circuit that divides and outputs the initialization clock generated by the clock generation circuit to the switching means, and the clock generation circuit generates the first frequency dividing circuit. And a second frequency dividing circuit for frequency-dividing and outputting the normal operation clock to the switching means.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an initialization circuit configured in an LSI. In this figure, reference numeral 1 denotes a terminal to which a clock is input from the outside, and the input clock is supplied to the input terminal B of the selection circuit 3 as the clock CK1 through the amplifier 2. Reference numeral 4 denotes an initialization clock generation circuit. The inverters 5 and 6 connected in series, the NOR circuit 7 in which the output of the inverter 6 is input to the first input terminal, and the output of the NOR circuit 7 are delayed for a predetermined time. The delay circuit 8 is fed back to the input terminal of the inverter 5. The clock CK2 generated by the clock generation circuit 4 is input to the input terminal A of the selection circuit 3. The selection circuit 3 outputs the clock at the input terminal A when the signal SELB input to the select terminal S is “0”, and the clock at the input terminal B when the signal SELB is “1”.
[0010]
Reference numeral 10 denotes a terminal to which a switching signal is input from the outside, and the switching signal input to the terminal 10 is supplied as a switching signal K to the reading terminal of the register 12 through the buffer 11. Reference numeral 14 denotes a terminal to which a reset signal is input from the outside. The reset signal input to the terminal 14 is supplied as a reset signal R to the reset terminal of the register 12 via the buffer 15 and to each part of the LSI. Is done. The register 12 is a 1-bit register that is reset by the reset signal R and set by the switching signal K, and its output is input to the second input terminal of the NOR circuit 7 and the select terminal S of the selection circuit 3.
[0011]
Next, the operation of the above-described circuit will be described with reference to the timing chart shown in FIG.
When power is supplied to the LSI (see FIG. 2A), a reset signal (Low) is input to the terminal 14 at the same time. When the reset signal is input to the terminal 14, the reset signal R (FIG. 2B) is input from the buffer 15 to the register 12, and the register 12 is reset. As a result, a “0” (Low) signal is input to the second input terminal of the NOR circuit 7, the clock generation circuit 4 starts oscillating, and the clock CK 2 is input to the input terminal A of the selection circuit 3. At this time, the “0” signal (Low) is input from the register 12 to the select terminal S of the selection circuit 3, and as a result, the selection circuit 3 outputs the clock CK2 of the input terminal A from the output terminal, and each part of the LSI (See (d) of FIG. 2). Each part of the LSI is initialized by the reset signal R and the clock CK2.
[0012]
Next, the reset signal R rises, and a switching signal is input to the terminal 10 from the outside at a subsequent time point ta (FIG. 2D). When the switching signal is input to the terminal 10, the signal K (FIG. 2 (e)) rises, the register 12 is set, the output becomes “1”, and this “1” signal is supplied to the NOR circuit 7. The signal SELB (FIG. 2 (f)) is supplied to the selection circuit 3. When the “1” signal is input to the NOR circuit 7, the oscillation of the clock generation circuit 4 stops (FIG. 2D). When a “1” signal is input to the selection circuit 3, the signal at the input terminal B is output from the selection circuit 3. In this state, when an external clock is applied to the terminal 1, the clock CK1 is output from the amplifier 2 ((c) in FIG. 2) and supplied to each part of the LSI via the selection circuit 3.
[0013]
As described above, in the initialization circuit of FIG. 1, when the power supply of the LSI rises, the internal clock CK2 rises and is supplied to each part of the LSI when the reset signal R is “0” (Low). The clock CK2 is supplied to each part of the circuit until the signal K rises. As a result, while the reset signal R is “0” (Low), a circuit such as a shift register that requires a clock for initialization is also initialized. That is, the initialization of each part of the LSI is performed during the initialization period T2 shown in FIG.
[0014]
Next, an LSI initialization circuit according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, an externally input clock is used in the LSI, but in this case, a clock synchronized with an externally input clock is generated in the LSI. In FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals.
In FIG. 3, reference numeral 21 denotes a clock generation circuit using a PLL (phase locked loop). In this clock generation circuit 21, 22 is a terminal to which a series connection circuit of an externally connected resistor 23 and capacitor 24 is connected. Reference numeral 25 denotes a terminal to which a reference signal (clock) is input from the outside. The external reference signal input to the terminal 25 is input to the first input terminal of the phase comparator 27 via the buffer 26. The phase comparator 27 performs phase comparison between the output of the buffer 26 described above and the output of the frequency dividing circuit 28 input to the second input terminal, and outputs a signal corresponding to the phase difference between them. The output of the phase comparator 27 is input to the charge pump circuit 29.
[0015]
The charge pump circuit 29 controls the output level of the phase comparator 27 and outputs it to the input terminal B of the voltage selection circuit 30. A series connection circuit of the resistor 23 and the capacitor 24 connected to the output terminal of the charge pump circuit 29 removes a high frequency component of the output of the charge pump circuit 29 and functions as a loop filter of the PLL circuit. The voltage selection circuit 30 selects the signal at the input terminal A when the signal SELB input to the select terminal S is “0” (Low), and selects the signal at the input terminal B when the signal SELB is “1” (High). Output to the control oscillator 31. The variable resistor 32 outputs a constant voltage to the input terminal A of the voltage selection circuit 30. The VCO 31 generates a clock CK having a frequency corresponding to the output of the voltage selection circuit 30 and outputs the clock CK to the PLL frequency dividing circuit 28 and also to the normal operation clock frequency dividing circuit 35 and the initialization clock frequency dividing circuit 36. To do. The PLL frequency divider 28 divides the output of the VCO 31 and outputs it to the second input terminal of the phase comparator 27.
[0016]
The normal operation clock frequency dividing circuit 35 divides the clock CK into a clock CK 1 and outputs it to the input terminal B of the selection circuit 3. The initialization clock frequency dividing circuit 36 divides the clock CK into a clock CK 2 and outputs it to the input terminal A of the selection circuit 3. Here, the frequency of the clock CK2 is set lower than the frequency of the clock CK1. The selection circuit 3 outputs the clock CK1 at the input terminal B when the signal input to the select terminal S is “1”, and outputs the clock CK2 at the input terminal A when the signal is “0”.
Terminals 10 and 14, buffers 11 and 15, and register 12 are the same as those in FIG.
[0017]
Next, the operation of the circuit described above will be described. The timing chart of this operation is the same as FIG.
When power is supplied to the LSI (FIG. 2A), the VCO 31 starts oscillating. When a reset signal is input to the terminal 14 simultaneously with power-on (FIG. 2B), the register 12 is reset and “0” is applied to the select terminal S of the voltage selection circuit 30 and the select terminal S of the selection circuit 3. (Low) signal is input. When a “0” (Low) signal is input to the select terminal S of the voltage selection circuit 30, a constant voltage output from the variable resistor 32 is input to the VCO 31, whereby the VCO 31 has a frequency corresponding to the same constant voltage. The clock CK is output. This clock CK is frequency-divided by the frequency dividing circuit 36 and input to the selection circuit 3 as the clock CK2. At this time, a “0” (Low) signal is input to the select terminal S of the selection circuit 3, and as a result, the clock CK2 (FIG. 2 (d)) is output from the selection circuit 3 to each part of the LSI. Supplied. The LSI components are initialized by the clock CK2 and the reset signal R output from the buffer 15.
[0018]
Next, the reset signal rises, and at the subsequent time ta (FIG. 2D), the external reference signal is supplied to the terminal 25, and at the same time, the switching signal is supplied to the terminal 10. When the switching signal is supplied to the terminal 10, the register 12 is set, and a "1" (High) signal is output from the output terminal. As a result, the voltage selection circuit 30 outputs the output signal of the charge pump circuit 29 to the VCO 31. As a result, thereafter, the VCO 31 outputs a clock CK having a frequency corresponding to the external reference signal, and this clock CK is divided by the frequency dividing circuit 35 and input to the selection circuit 3 as the clock CK1 (FIG. 2 (c)). The At this time, since the “1” (High) signal is supplied to the select terminal S of the selection circuit 3, the clock CK1 described above is supplied as a clock to each part of the LSI via the selection circuit 3.
[0019]
As described above, also in the second embodiment, when the power is turned on, the internal clock CK2 is generated and supplied to each part of the LSI. Thereby, each part of the LSI can be reset at the timing of the reset signal.
[0020]
【The invention's effect】
As described above, according to the present invention, the clock generation circuit that is activated at the time of power-on and generates an initialization clock, and the clock output from the clock generation circuit at the time of power-on are output to each part of the circuit. After receiving the switching signal from the outside, it is equipped with switching means for outputting an external clock to each part of the circuit, so there is no need for any special device for initialization, and initialization is performed in a short time The effect that can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an LSI initialization circuit according to a first embodiment of the present invention;
FIG. 2 is a timing chart for explaining the operation of the embodiment;
FIG. 3 is a circuit diagram showing a configuration of an LSI initialization circuit according to a second embodiment of the present invention;
FIG. 4 is a timing chart for explaining an initialization operation of a conventional LSI.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,10,14 ... Terminal, 3 ... Selection circuit, 4 ... Initialization clock generation circuit, 5, 6 ... Inverter, 7 ... NOR circuit, 8 ... Delay circuit, 12 ... Register, 21 ... Clock generation circuit (PLL) , 22, 25 ... terminals, 27 ... phase comparator, 28 ... PLL frequency divider, 29 ... charge pump circuit, 30 ... voltage selection circuit, 31 ... VCO, 32 ... variable resistance, 35 ... frequency division for normal operation clock Circuit 36: initialization clock frequency divider.

Claims (2)

Power-on and is activated at the same time, generates a clock initialization, a clock generating circuit for generating a normal operation clock synchronized with the external clock after receiving a switching signal from the outside,
The switching means for outputting Previous SL through normal operation clock circuits each unit after outputting the previous SL for Initial forming clock to the individual circuit components, receiving the switching signal from the outside in at power,
Equipped with,
The clock generation circuit includes:
A normal operation clock generation circuit that has a voltage controlled oscillator and generates the normal operation clock by a PLL; and an initialization clock generation circuit that generates the initialization clock using the voltage control oscillator. An initialization circuit for a large-scale integrated circuit. A first frequency dividing circuit that divides the initialization clock generated by the clock generation circuit and outputs the divided clock to the switching means;
A second frequency dividing circuit for frequency-dividing the normal operation clock generated by the clock generation circuit and outputting it to the switching means;
The initialization circuit for a large-scale integrated circuit according to claim 1, comprising:

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