JP4032991B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit capable of controlling skew between clock signals.
[0002]
[Prior art]
In recent years, LSIs (Large Scale Integrated Circuits) have been operating with signals and clock signals with frequencies on the order of gigahertz, and the speed has been further increased. Along with this, load variation in the chip, wiring system variation, process variation, etc., which have not been a major problem in the past, have a significant effect on the delay of the clock signal for each area where the clock signal is distributed. As a result, a large delay difference (skew) is generated between the clock signals, which becomes a limitation on the transmission speed. It is extremely difficult to completely eliminate such variations at the LSI design stage, and variations occur between chips, so uniform design is becoming increasingly difficult. In view of this, various skew adjustment circuits have been devised, for example, a method of performing skew adjustment by providing a delay gate (see, for example, Patent Document 1), and a skew gate by forming a delay gate in a tree shape. A method of performing adjustment (for example, see Patent Document 2) has been proposed. Such a method of inserting a dummy buffer is the mainstream of such skew adjustment.
[0003]
[Patent Document 1]
JP 2002-189698 A (3rd, 4th page, FIG. 1)
[Patent Document 2]
JP 2000-236025 A (3rd page, FIG. 1-5)
[0004]
[Problems to be solved by the invention]
However, any of the above-described methods has disadvantages such as excessively operating the delay gates, resulting in an increase in power consumption and an accompanying increase in the amount of power supply noise. It was a trade-off with disadvantages. Also, due to local differences in the amount of power supply noise, it is possible that the skew once adjusted and within the allowable range may move toward the outside of the allowable range over time, and future high-speed clock signal distribution Stricter adjustments are required.
[0005]
The present invention has been made in view of such a problem, and an object of the present invention is to use no delay gate, and to prevent a skew amount that is less than an allowable value from fluctuating over time or time. A semiconductor integrated circuit having a skew control unit that can be easily readjusted even if it fluctuates, and a skew control method.
[0006]
[Means for Solving the Problems]
To achieve the above object, according to the present invention, a semiconductor integrated circuit having a plurality of clock distribution area clock signal distributed from a single global clock signal is input is supplied, said global clock signal The clock signal distributed between the clock distribution regions is controlled by controlling the output voltage output to the clock distribution region by the power source provided in the clock distribution region. Based on the detection circuit that detects the difference in delay amount (skew amount) or phase difference between the clock signals supplied to the clock distribution area to be controlled , and the skew amount or phase difference output from the detection circuit, skew control having a power control circuit for controlling the output voltage of the power supply provided in the clock distribution area When the the interface for inputting the external signal to the clock distribution for each area, by inputting a clock signal that is distributed to the signal and the clock distribution area is input via the interface, the detection circuit the output And a phase comparison circuit for providing a semiconductor integrated circuit.
[0007]
And preferably, the said power supply is comprised by the DC-DC converter.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[ Reference example ]
FIG. 1 is a block diagram of a semiconductor integrated circuit according to a reference example of the present invention. The semiconductor integrated circuit 20 includes a skew control unit 30 having a skew detection circuit 13 and a power supply control circuit 12, and a plurality of clock signal distributions. Regions 1 ₁ to 1 _N. The clock signal distribution areas 1 ₁ to 1 _N are respectively provided with DC-DC converters 11 _{1 to} 11 _{N serving} as power sources thereof. The clock signal distribution areas 1 ₁ to 1 _N are composed of, for example, logic circuits, and a clock signal distributed from a single global clock signal GCLK is supplied to each clock signal distribution area. At this time, a delay difference (skew) is caused between the clock signals distributed to the clock signal distribution areas 1 ₁ to 1 _N due to variations in distribution paths. As the clock frequency becomes higher, the ratio of the skew amount to one cycle of the clock signal becomes relatively large, and it becomes difficult to keep it below the allowable value from the delay design. The skew detection circuit 13 calculates and detects the skew amount from the difference in the delay amount of the clock signal between the clock signal distribution areas, and outputs the detected skew amount to the power supply control circuit 12. The power supply control circuit 12 controls the power supply voltage output from the DC-DC converter, which is the power supply in the clock signal distribution area, according to the skew amount. It is a well-known fact that when the power supply voltage is increased, the operation of such a semiconductor integrated circuit becomes faster. Therefore, the amount of skew can be controlled by controlling the power supply voltage from the DC-DC converter. It is.
[0009]
Hereinafter, the operation of the skew control unit of this reference example will be described in more detail. FIG. 2A shows the amount of delay of the clock signal observed in each clock signal distribution region when the skew control unit 30 is not operating. In this case, N = 8. ΔT is the amount of skew between the two clock signal distribution areas. The output power supply voltage from the DC-DC converter is unified to 1.00V. Focusing on the clock signal distribution region _{1 1} and _{1 2} and the delay amount of the clock signal of the clock signal distribution region _{1 1} and _{1 2,} as shown in FIG. 3, respectively, 120 ps, is 160 ps. Therefore, the skew amount ΔT = 40 ps. When skew control unit 30 operates, the skew detection circuit 13, the skew amount, by inputting the clock signal of the clock signal distribution region 1 ₁ and 1 _2, by taking the difference of those delay amount detected . Next, the skew detection circuit 13 outputs this skew amount to the power supply control circuit 12. The power supply control circuit 12 controls the output power supply voltage of the DC-DC converter, which is the power supply for the clock signal distribution area, according to the skew amount. Here, based on the delay amount of the clock signal distribution region 1 ₁ of the clock signal, consider the case to match the delay amount of the clock signal for all other clock signal distribution area on the reference amount of delay. In this case, the delay amount of the clock signal distribution region 1 _second clock signal, since larger than the delay amount of the clock signal distribution region 1 ₁ of the clock signal, the power control circuit 12, a clock signal distribution region 1 ₂ DC-DC increasing the output power supply voltage of the converter 11 _2. For example, the power control circuit 12, a clock signal distribution area 1 ₂ output power supply voltage of the DC-DC converter 11 ₂ will be increased in 1% increments, the detection level of the skew amount skew detection circuit 13 or less, and / or When the skew amount is less than the allowable value, this control is stopped. Therefore, the clock signal distribution area _{1 2} of the power supply voltage (output voltage of the DC-DC converter 11 ₂₎ is, as shown in FIG. 3, determined to 1.12 V. In this case, next to the clock signal delay amount of the clock signal distribution region 1 ₂ 121PS, the amount of skew between the clock signal distribution region 1 ₁ is turned and 1 ps, equal to or less than the allowable value of the skew quantity. For example, when the DC-DC converter is a switching regulator, the power supply voltage of the DC-DC converter can be controlled by changing the pulse occupation ratio. That is, if the pulse occupation ratio is increased, the power supply voltage is increased, and if the pulse occupation ratio is decreased, the power supply voltage is decreased. The power supply control circuit 12 inputs the skew amount from the skew detection circuit 13, and controls the pulse occupancy so that the skew amount is equal to or less than an allowable value.
[0010]
The above and similar process, by performing with the clock signal distribution region 1 ₁ and all other clock signal distribution area, as shown in FIG. 2 (b), the amount of skew between all of the clock signal distribution area The delay amounts of the clock signals in all the clock signal distribution regions are uniform so that the value is less than the allowable value of the skew amount.
[0011]
Note that the skew amount itself does not necessarily have to be calculated. By suppressing the phase difference of the clock signal between the clock signal distribution areas to be below the allowable value, the skew amount is effectively controlled to be below the allowable value. Is possible. This is because (clock signal period) × (phase difference) / (2π) is equal to the skew amount. The phase difference between the clock signals is obtained as an output when the clock signals in the two clock signal distribution regions are input to, for example, two inputs of an EX-OR (exclusive OR) circuit. Further, the delay amount of the reference clock signal is set to the minimum delay amount [the delay amount of the clock signal distribution area ₁₈ in FIG. 2A], and all other clock signal distributions are set to this minimum delay amount. The delay amount of the area may be matched.
[0012]
As is clear from the above description, according to the present reference example , there is no increase in power consumption due to an extra dummy gate or the like. In addition, since the difference in the clock signal delay amount or phase difference between the clock signal distribution regions is detected and the power supply voltage in the clock signal distribution region is adjusted, the skew amount between the clock signal distribution regions is set to a certain value. It is less than the allowable value, and it does not exceed the allowable value over time. Furthermore, since the power supply is stabilized by the DC-DC converter for each clock signal distribution area, an effect of noise reduction is also expected.
[0013]
First Embodiment
FIG. 4 is a block diagram of the semiconductor integrated circuit according to the first embodiment of the present invention. 4, parts that are the same as the parts in FIG. 1 are given the same reference numerals, and redundant descriptions will be omitted as appropriate. This embodiment differs from the reference example shown in FIG. 1 in that a test IF (interface) 15 and a phase comparison circuit 40 in which the test IF is connected to the input side are formed for each clock signal distribution region. That is, the output of the phase comparison circuit 40 is input to the skew detection circuit 13.
[0014]
The phase comparison circuit 40 is composed of a series circuit of an EX-OR circuit and a low-pass filter. A clock signal distributed to each clock signal distribution region is input to one input of the EX-OR circuit. A test signal is input to the other input of the EX-OR circuit via the test IF 15 when testing the semiconductor integrated circuit after completion of the semiconductor integrated circuit 20. The test signal is a clock signal having the same period as the global clock signal, and is input in the same phase to the test IF 15 provided for each of the clock distribution regions 1 ₁ to 1 _N.
[0015]
FIG. 5 shows an input signal and an output signal of the EX-OR circuit of the phase comparison circuit 40. As shown in FIG. 5, the output signal is a signal proportional to the phase difference between the test signal and the clock signal distributed to each clock signal distribution region. The low-pass filter connected in series to the EX-OR circuit removes high-frequency components from the output of the EX-OR circuit and smoothes the output of the EX-OR circuit.
[0016]
The skew detection circuit 13 receives the output of each phase comparison circuit 40 and compares the phase difference between the two clock signal distribution areas of them to thereby compare the phase difference between the clock signals in the two clock signal distribution areas. And the phase difference is output to the power supply control circuit 12. That is, the skew detection circuit 13 effectively detects the amount of skew between the clock signals by detecting the phase difference between the clock signals in the two clock signal distribution areas. The subsequent process is the same as in the reference example .
[0017]
It is clear that this embodiment has the same effect as the reference example . However, if the skew amount fluctuates outside the allowable range over time, it does not automatically return to the allowable range, but the skew amount can be returned to the allowable range by inputting a test signal to the test IF again. Is possible.
[0018]
Although the present invention has been described based on the preferred embodiments thereof, the semiconductor integrated circuit of the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. Semiconductor integrated circuits subjected to these changes are also included in the scope of the present invention. For example, the power source of each clock signal distribution region is not limited to a DC-DC converter using a switching regulator, and may be configured by, for example, a charge pump and a low-pass filter. There may be.
[0019]
【The invention's effect】
As described above, since the semiconductor integrated circuit according to the present invention does not use an extra dummy gate, it is possible to suppress power consumption. In addition, the semiconductor integrated circuit according to the present invention detects the difference in the delay amount or the phase difference of the clock signal between the clock signal distribution areas and adjusts the power supply voltage in the clock signal distribution area. The amount of skew between the regions is less than a set allowable value and does not vary with time, or can be readjusted easily even with time variation. Furthermore, the semiconductor integrated circuit according to the present invention has an effect of reducing noise because the power source is stabilized by the DC-DC converter for each clock signal distribution region.
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor integrated circuit according to a reference example of the present invention.
2 is a graph for explaining a delay amount before adjustment ([a)] and after adjustment [(b)] of a clock signal distributed to each clock signal distribution region of the semiconductor integrated circuit of FIG. 1;
3 is a table for explaining a relationship between a skew amount before and after adjustment between a clock signal distributed to two clock signal distribution regions of the semiconductor integrated circuit of FIG. 1 and a power supply voltage;
FIG. 4 is a block diagram of the semiconductor integrated circuit according to the first embodiment of the present invention.
5 is a time chart for explaining the operation of the phase comparison circuit of FIG. 4;
[Explanation of symbols]
1 ₁ to 1 _N clock signal distribution area 11 _{1 to} 11 _N DC-DC converter 12 power supply control circuit 13 skew detection circuit 15 test IF
20 Semiconductor Integrated Circuit 30 Skew Control Unit 40 Phase Comparison Circuit

Claims (2)

A semiconductor integrated circuit having a plurality of clock distribution regions to which a clock signal distributed from a single global clock signal is supplied and inputted, and using the clock signal distributed from the global clock signal , the clock The clock signal supplied to the clock distribution area , which controls the skew amount of the clock signal between the clock distribution areas by controlling the output voltage output to the clock distribution area by the power source provided in the distribution area a detection circuit for detecting a difference (skew amount) or the retardation amount of delay between the said skew amount is output from the detection circuit or on the basis of the phase difference, the output voltage of the power supply provided in the clock distribution area a power control circuit for controlling a skew control unit with an external signal to said clock distribution for each region And interfaces for power, by inputting the clock signal being distributed to the signal and the clock distribution area is input via the interface, a phase comparator circuit for providing an output to the detection circuit, that it has a A semiconductor integrated circuit.   The semiconductor integrated circuit according to claim 1, wherein the power source is a DC-DC converter.

Images