JP4033438B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a flash memory using a three-layer metal wiring technique.
[0002]
[Prior art]
In general, the capacity unit of the flash memory that can be electrically written or erased is 64 KB (= 512 Kbits), so that the memory cell array in the chip is separated in that unit. For example, in the case of a 16 Mb flash memory, 32 64 KB sub memory cell arrays are arranged, and a decoder circuit for selecting a word line and a bit line is provided in each sub memory cell array in order to select a memory cell. Since there are mainly two types of decoding circuits, they will be described in the following order.
[0003]
FIG. 14 is a schematic diagram of a flash memory using a double word line decoding method.
[0004]
In this double word line decoding system, the number of memory cells connected to one word line is reduced to reduce the word line capacity and to increase the operation speed.
[0005]
In FIG. 14, a plurality of sub memory cell arrays 1b including a plurality of memory cells connected to the sub word lines 15 are provided in the column direction, and a block decoder 18 and a row sub decoder 11 are provided in each sub memory cell array 1b. Further, the main word line 14 and the row main decoder 10 are provided in common in the memory sub-array 1b in the same column. These configurations are usually repeated a plurality of times in the row direction.
[0006]
In the double word line decoding system, one main word line 14 is selected by the row main decoder 10 based on, for example, row addresses A0-A6, and the remaining row address A7- is selected by the block decoder 18 and the row sub-decoder. One sub word line 15 is selected based on A9. That is, any of the plurality of sub word lines 15 is connected to the main word line 14.
[0007]
Therefore, since a smaller number of memory cells are connected to the main word line 14 than the total number of memory cells in the row direction, the word line delay is small even if the memory capacity is large.
[0008]
In addition, by using a multilayer wiring technique for this hierarchical decoding, the main word line 14 can be stacked on the sub word line 15, the circuit area required for decoding the memory cell is reduced, and input to each decoder. The routing distance of the address signal line is also shortened.
[0009]
FIG. 15 is a schematic diagram of a flash memory using a double bit line decoding system.
[0010]
This double bit line decoding method is hierarchical decoding for bit lines.
[0011]
In FIG. 15, a plurality of sub memory cell arrays 1b including a plurality of memory cells connected to the sub bit lines 17 are provided in the row direction, and a sub bit line selector 12a is provided in each sub memory cell array 1b. Further, the main bit line 16 and the main bit line selector 12b are provided in common in the memory sub-array 1b in the same row. These configurations are usually repeated multiple times in the column direction.
[0012]
Similar to the double word line described above, the hierarchical decoding is used, so the area is reduced, and the main bit line 16 is connected to the sense amplifier, so the wiring capacity from the memory cell to the sense amplifier is reduced and high-speed reading is possible. become.
[0013]
[Problems to be solved by the invention]
In an actual flash memory, all the units that can be written or erased are not 64 KB, but a small memory sub-array of 8 KB called a boot cell array coexists. This is for storing stored program data and the like that are desired to be rewritten in units smaller than 64 KB.
[0014]
For example, in a 16 Mbit flash, the memory cell array has an irregular configuration with 31 64 KB cell arrays and 8 8 KB cell arrays. These structures are conventionally arranged as shown in FIG. 16, and a double word line decoding system has been adopted.
[0015]
On the upper side, eight 8KB cell arrays 1b are arranged so as to sandwich the row sub decoder 11 for selecting the sub word line 15 of each cell array, and the row main decoder 10 for selecting the main word line 14 on the left side is common. Is arranged. A column selector for selecting a bit line and a block decoder for selecting a row subdecoder 11 are arranged on the upper side of the 8 KB cell array.
[0016]
On the lower side, two 64 KB cell arrays 1b are arranged so as to sandwich the row sub decoder 11 for selecting the sub word line 15 of each cell array. On the left side, the row main decoder 10 for selecting the main word line 14 is arranged. Commonly arranged. 64 Below the KB cell array, a column selector for selecting a bit line and a block decoder for selecting a row subdecoder 11 are arranged.
[0017]
The number of columns connected to the I / O data line is smaller in the 8 KB cell array 1b than in 64 KB. In order to select two types of cell arrays with the same selection signal, sub-data lines are drawn over a plurality of 8 KB cell arrays 1b to match the number of columns of the 64 KB cell array.
[0018]
Thus, since the number of rows in the 8 KB and 64 KB cell arrays 1b is the same, the double word line decoding method can be easily introduced.
[0019]
However, in order to increase the operation speed, in order to adopt the double bit line decoding method in addition to the double word line decoding method, the following inconsistency in the column direction becomes a problem in the conventional structure. .
[0020]
1) The column selectors (main bit line selector 12b, sub bit line selector 12a) for the 8 KB cell array have a different pitch and irregular arrangement from those for the 64 KB cell array.
[0021]
2) The arrangement of the erase decoder circuit for erasing data for the 8 KB cell array and the block decoder circuit necessary for the double bit line decoding method does not match the column pitch.
[0022]
For this reason, when the double bit line decoding method is adopted in addition to the conventional double word line decoding method, not only the layout is complicated, but also a dead space caused by the sub data line and the like is generated, and the data line is constricted. As a result, the wiring resistance increases and the speeding up of the operation is hindered.
[0023]
Therefore, the present invention provides a flash memory having a memory sub-array having different capacities while simultaneously adopting a double word line and double bit line decoding system and capable of suppressing an increase in chip area and enabling a high speed operation. The purpose is to provide.
[0024]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes a plurality of nonvolatile memory cells arranged in a matrix and a predetermined number of nonvolatile memory cells in the same row The Sub word line A plurality of sub memory cell arrays connected to the In addition, a main word line is commonly connected to a plurality of sub word lines in the same row via a row selector. , Above Sub memory cell array The total number is smaller than plural Nonvolatile memory cells are arranged in a matrix, and a predetermined number of nonvolatile memory cells in the same row The Sub word line A plurality of boot cell arrays connected to the In a semiconductor memory device in which main word lines are commonly connected to a plurality of sub word lines in the same row via a row selector, Each Above Sub memory cell array A predetermined number of nonvolatile memory cells in the same column The Sub bit line In connection, And in the sub memory cell array A main bit line is commonly connected to a plurality of sub bit lines via a column selector, Each Above Boot cell array A certain number of non-volatiles in the same column sex Memory cell The Sub bit line In connection, And in the sub memory cell array A main bit line is commonly connected to a plurality of sub bit lines via a column selector, Main bit line of boot cell array The above Sub memory cell array Main bit line To align And placing Sub memory cell array and In the boot cell array, Each sub bit line Total number of Are the same number, The length of each sub word line is made substantially the same, the interval between the main bit lines is made substantially the same, the main bit line of the sub memory cell array and the main bit line of the boot cell array are made independent and connected to different sense amplifiers Each of the sub memory cell arrays and each of the boot cell arrays is an independently erasable capacity unit, and the storage capacity of the sub memory cell array and the total storage of the plurality of boot cell arrays A special sub memory cell array having the same capacity and at least one of the sub memory cell arrays is accessed in a different manner from the other sub memory cell arrays. It is characterized by that.
[0025]
With this configuration, it is possible to provide a flash memory that can suppress the increase in chip area and can operate at high speed while simultaneously adopting the double word line and double bit line decoding methods.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing the main part of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
[0027]
The address input from the external terminal is decoded through the address buffer 3. A memory cell corresponding to the decoded value is selected by row main decoders 10 and 20, row sub-decoders 11 and 21 and column selectors 12 and 22, and read / write / erase is performed according to the output of control circuit 7. The read data is output via the sense amplifier 5 and the output buffer 6. The main potential necessary for each operation is generated by the voltage control circuit 9 and applied to the memory cell and the circuit for performing various controls.
[0028]
For example, the potential VDDH (for example, 10V) generated by the voltage control circuit 9 is applied to the source of the selected memory cell at the time of erasing, and VDDH is applied to the word line of the selected memory cell at the time of writing. Also, when reading, Pressure A potential VDDR (for example, 4.7 V) generated by the control circuit 9 is applied to the word line of the selected memory cell.
[0029]
2 and 3 are a schematic configuration diagram and a detailed configuration diagram of the memory cell array according to the first embodiment, respectively.
[0030]
It is assumed that there are two types of writing or erasing units, 64 KB unit and 8 KB unit. Hereinafter, the larger capacity is referred to as a regular cell array 1a, and the smaller capacity is referred to as a boot cell array 2.
[0031]
In this embodiment, the regular cell array 1a has 1024 rows × 512 columns, and the boot cell array 2 has 128 rows × 512 columns. As shown in FIG. 2, eight regular cell arrays 1a are arranged on the upper side with two column sub-decoders 11 between them, and the column main decoder 10 is arranged on the leftmost side. Similarly, eight boot cell arrays 2 are arranged on the lower side with two column sub-decoders 11 sandwiched therebetween, and a column main decoder 20 is arranged on the leftmost side. Corresponding block decoders and column selectors 12 and 22 are arranged between the regular cell array 1a and the boot cell array 2, respectively.
[0032]
According to this embodiment, since the column pitches of the two types of memory cell arrays do not change, there is no layout problem even if the double bit line system is adopted for each memory cell array. Furthermore, since the main bit line 16 can be shared by two types of memory cell arrays, the degree of freedom in layout around the sense amplifier is increased.
[0033]
In the two types of memory cell arrays, the number of columns of memory cells connected to the I / O data lines is the same, so that it is not necessary to route the sub-data lines across a plurality of boot cell arrays 1c, which is conventionally required. Become. Therefore, in laying out the data line from the main bit line 16 to the sense amplifier, an increase in chip area can be suppressed.
[0034]
Since the number of rows of the boot cell array 2 is 1/8 of the regular cell array 1a, the number of row decode circuits on the boot cell array 2 side is changed to 1/8 of the row decode circuit on the regular cell array 1a side. The double word line system can also be easily introduced. For signals RB0-RB1023 for selecting the row subdecoders 11 of each regular cell array 1a, signals for selecting the row subdecoders 21 of the eight boot cell arrays are RB0-RB127, RB128-RB255,..., RB896-RB1023 This is because two types of memory cell arrays can be selected with the same signal.
[0035]
Further, as shown in FIG. 3, since the length of the sub word line 15 is equal between the boot cell array 2 and the regular cell array 1a, the boot cell array 2 is not treated irregularly in the row direction. The layout is more flexible than before. For example, the sense amplifier can be arranged in the vicinity of the boot cell array 2 or can be arranged far from the boot cell array 2. If it is arranged in the vicinity of the boot cell array 2, the distance between the I / O pads from the boot cell array 2 can be shortened via the sense amplifier, so that the boot cell array 2 can be accessed at a higher speed.
[0036]
4 and 5 are a cross-sectional view of the memory cell array along the bit line direction and a cross-sectional view along the word line direction, respectively.
[0037]
A plurality of double wells are formed on a P-type semiconductor substrate, memory cells are formed in one well, and column selectors 12 and 22 or row selectors 11 and 21 are formed in another well. As shown in FIG. 4, the sub bit line 17 is composed of a first layer metal M1, and the main bit line 16 is composed of a third layer metal M3. As shown in FIG. 5, the sub word line 15 is made of poly Si silicided, for example, Poly Si / WSi, and the main word line 14 is made of the second layer metal M2. M1 is made of, for example, W silicide. M2 and M3 are composed of a metal layer such as Al, Al alloy, or Cu alloy, and usually an antireflection film is formed on the upper layer, or a barrier metal or both are formed on the lower layer. The antireflection film and barrier metal are composed of a single layer or multiple layers such as a Ti film and a Ti / TiN film. In FIG. 5, a field oxide film is used for element isolation, but trench isolation may be used.
[0038]
Each memory cell has a MOS structure in which a floating gate 51, a composite insulating film, and a control gate 52 are stacked. These sources and drains are shared by adjacent ones. By injecting electrons into the floating gate 51 or withdrawing electrons from the floating gate 51, the data value of the memory cell can be changed.
[0039]
Hereinafter, read and write operations will be described.
[0040]
FIG. 6 is a table showing basic operating voltage conditions of the memory cell.
[0041]
At the time of erasing, the control gate 52 is set to -7.5V, the drain is floated, and the source and the semiconductor substrate are set to 10V with respect to the selected memory cell. Since electrons are extracted from the floating gate to the semiconductor substrate by the Fowler-Nordheim current, the threshold value of the memory cell is positive (data is “0”).
[0042]
At the time of writing, the control gate is set to VDDH (for example, 10 V), the drain is set to VDDP (for example, 5 V), and the source and semiconductor substrate are set to 0 V for the selected memory cell. Since electrons are injected from the semiconductor substrate / drain into the floating gate 51 by the hot electron effect, the threshold value of the memory cell becomes negative (data is “1”).
[0043]
At the time of reading, VDDR (for example, about 4.7V) is set to the control gate 52, the drain is set to 0.8V, and the source is set to 0V for the selected memory cell. If the threshold value of the memory cell is negative (data is “1”), the memory cell is on, and if the threshold value is positive (data is “0”), the memory cell is off. Therefore, data can be read by sensing the bit line potential.
[0044]
Incidentally, when supplying the voltage necessary for the operation to the source / drain / control gate, the voltage generated by the voltage control circuit 9 is actually selectively supplied to the decoder circuit by the decoder voltage control circuit 90.
[0045]
FIG. 7 is a schematic block diagram of the decoder voltage control circuit.
[0046]
The voltage control circuit 9 has a plurality of charge pump circuits for generating a boosted voltage, and VDDH, VDDR, VBB, and VDDP are generated from each of them. Each voltage is selectively supplied to the column main decoder 10, the column sub-decoders 11 and 21, and the block decoder 18 using the decoder voltage control circuit 90.
[0047]
Usually, the decoder voltage control circuit 90 is arranged within the length of the memory cell array 1 in the row direction. Since the length in the row direction is about 1/8 in the boot cell array 2, in this embodiment, the decoder voltage control circuit 90 for the boot cell array is arranged on the regular memory cell array 1 side as shown in FIG.
[0048]
As described above, according to the present embodiment, the layout of the peripheral circuit becomes easy and the increase of the chip area can be suppressed while simultaneously adopting the double word line and double bit line decoding methods. High-speed operation is also possible.
[0049]
The second embodiment according to the present invention will be described below.
[0050]
FIG. 8 is a block diagram showing the main part of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.
[0051]
The difference from the first embodiment is that a special memory area (hereinafter referred to as Hidden ROM 1c) for storing confidential user information such as a password is added.
[0052]
The Hidden ROM 1c is selected in the same manner as the normal memory cell array 1 by the address A0-An. In other words, the memory cell array 1 is normally accessed, but when the Hidden ROM selection signal is generated from the control circuit 7, the Hidden ROM is selected.
[0053]
FIG. 9 is a schematic configuration diagram of a memory cell array according to the second embodiment.
[0054]
Since the Hidden ROM 1c has a writing or erasing unit of 64 KB, the Hidden ROM 1c has 1024 rows × 512 columns and the same configuration as the regular cell array described in the first embodiment.
[0055]
In FIG. 9, the row main decoder 10 is shared by seven regular cell arrays 1a and one Hidden ROM 1c. Seven regular cell arrays 1a and one Hidden ROM 1c are arranged on the upper side, eight boot cell arrays are arranged on the lower side, and the main bit line 16 is shared between the upper and lower arrays. That is, the Hidden ROM 1c also shares the main bit line 16 with the boot cell array 2 in the same column.
[0056]
As in the first embodiment, in the second embodiment, since the column direction can be laid out at the same pitch, it is not necessary to perform a complicated layout even in a double bit line structure. The degree of freedom in circuit layout increases.
[0057]
In the case of a 16 Mb flash memory, if the boot cell array 2 is configured to be 8 KB × 8, the regular cell array 1 a is 64 KB × 31. If eight regular cell arrays 1a are arranged in the row direction, seven cells are arranged in the last row, resulting in a dead space. If the Hidden ROM 1c is arranged there as in this embodiment, in addition to the effects of the first embodiment, there is a merit that the dead space can be effectively used.
[0058]
The third embodiment according to the present invention will be described below.
[0059]
FIG. 10 is a schematic configuration diagram of a memory cell array according to the third embodiment.
[0060]
As in the second embodiment, seven regular cell arrays 1a and one Hidden ROM 1c are arranged on the upper side, and eight boot cell arrays 2 are arranged on the lower side.
[0061]
Unlike the previous embodiments, in this embodiment, the main bit lines 16 are independent in the upper and lower arrays. The main bit lines 16 corresponding to each are connected to different sense amplifiers in order to separate the readout system.
[0062]
This allows dual operation. That is, when writing into the memory cell of the boot cell array 2, a read operation can be performed on the regular cell array 1a. On the other hand, when the memory cell of the boot cell array 2 is being read, the regular cell array 1a can be written.
[0063]
Since the double word line decoding system is adopted as in the other embodiments, it is needless to say that high-speed row access is possible. Since the sub bit line 17 of the boot cell array 2 is shorter than the regular cell array 1a, the capacity is increased. Is light and high-speed read operation is possible. Furthermore, this embodiment is suitable for processing by a high-speed CPU because dual operation is possible.
[0064]
FIG. 11 is a diagram illustrating an example of dual operation.
[0065]
In this example, the boot cell array 2 is read and simultaneously written to the regular cell array 1a.
[0066]
In the boot cell array 2, 4.7 V is supplied to the row main decoder 20 and the sub decoder 21 by the decoder voltage control circuit 90, and 0.8 V is supplied to the bit line by the bias circuit in the sense amplifier.
[0067]
In the regular cell array 1a, 5V is supplied to the row main decoder 10 and the sub decoder 11 by the decoder voltage control circuit 90, and 10V is supplied to the main bit line 16 and the sub bit line 17 from the write load (write Tr).
[0068]
Thus, in order to execute different operations simultaneously, it is necessary to control the power supply of the decoder separately. This unit for voltage control is usually treated as a bank. Since the configuration according to the present invention is applicable to the memory cell array 1 having a large number of banks, there is an advantage that the degree of freedom of the memory space in which the user can perform dual operation can be increased.
[0069]
In this embodiment, the same operation for both cell arrays, for example, reading and reading is impossible, but a control circuit is further provided so that both data do not collide with each other in the I / O buffer, or the I / O system is separately set. This is possible. For example, if a latch circuit is provided and the data for the boot cell array 2 is operated with priority, the data for the regular cell array 1a is held by the latch circuit, and when the operation for the boot cell array 2 is completed, the regular cell array 1a is accessed. The same operation is possible.
[0070]
Further, when the I / O system is made independent, the power-on reset is made different from the normal one so that only the regular cell array 2 is reset to the read state and the boot cell array 2 is reset to another mode. good.
[0071]
In the first to third embodiments, the regular cell array 2 has only one block in the row direction. However, it is possible to add more blocks in the row direction. FIG. 12 is a schematic configuration diagram of a memory cell array according to an application example relating to the third embodiment of the present invention.
[0072]
Regular cell array so that main bit line 16 is arranged in the longitudinal direction of the chip 1a And Hidden ROM 1c Is arranged. A boot cell array 2 is arranged on the chip end side. The boot cell array 2 is divided into a plurality of sections in the main bit line 16 direction. Since one section is treated as an erase unit, the memory cell array constituting one section is separated from the semiconductor substrate by a double well. According to the present embodiment, even when the capacity of the boot cell array 2 is increased, the double word line and the double bit line can be easily applied.
[0073]
Other layouts are possible. FIG. 13 is a schematic diagram of a memory cell array according to another application example of the third embodiment of the present invention. In this embodiment, there are 128-X 64 Mbit 64 KB regular cell arrays 1 a, X 64 KB Hidden ROMs, and 8 8 KB boot cell arrays 2 in a bundle. Usually, X is 1, for example, as shown in FIG. 13, the boot cell array 2 is arranged only on the lower left side, and the voltage control circuit 90 for the boot cell array 2 is also arranged only on the lower left side. On the other hand, when X is set to 2, the boot cell array can be arranged symmetrically across the peripheral circuit as shown in FIG.
[0074]
In addition, this invention is not limited to the said Example. The layout of the memory cell array 1 and peripheral circuits can be changed as appropriate.
[0075]
Further, a redundant memory cell array may be further provided in the regular cell array 1a so that the sub bit line to which the defective memory cell is connected can be replaced with the sub bit line of the redundant memory cell array, or the sub word lines can be replaced with each other. In other words, dummy word lines and dummy bit lines that are not actually used may be arranged in the regular cell array 1a. Further, dummy word lines and dummy bit lines may be provided in the boot cell array 2 as well. In this case, each dummy bit line in the regular cell array 1a and the boot cell array 2 may be connected to a common main bit line.
[0076]
Alternatively, a redundant memory cell array may be provided separately from the regular cell array 1a.
[0077]
Further, the memory cell is not limited to the above-described double gate. For example, the present invention can be applied to a structure having three layers of composite insulating films and a control gate thereon, or a structure having control gates having a composite insulating film on both sides of a word gate.
[0078]
Note that the present invention can be applied not only to a single nonvolatile semiconductor memory device but also to a product in which a memory and an ASIC are mixedly mounted on a single chip, or a package in which a plurality of chips are stacked. And the effect of enabling high-speed operation.
[0079]
Further, the capacity of the regular cell array 1a and the boot cell array 2 is not limited to the above-described embodiment, and the double word line and double bit line structure can be efficiently obtained by applying the present invention to any capacity. be able to.
[0080]
In addition, various modifications can be made without departing from the scope of the invention.
[0081]
【The invention's effect】
Since the present invention is configured as described above, it is possible to provide a flash memory capable of operating at high speed while suppressing the increase in chip area while simultaneously adopting the double word line and double bit line decoding methods. .
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main part of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of a memory cell array according to the first embodiment of the present invention.
FIG. 3 is a detailed configuration diagram of a memory cell array according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view taken along the bit line direction of the memory cell array.
FIG. 5 is a cross-sectional view taken along the word line direction of the memory cell array.
FIG. 6 is a table showing basic operating voltage conditions of a memory cell.
FIG. 7 is a schematic block diagram of a decoder voltage control circuit.
FIG. 8 is a block diagram showing a main part of a nonvolatile semiconductor memory device according to a second example of the present invention.
FIG. 9 is a schematic configuration diagram of a memory cell array according to a second embodiment of the present invention.
FIG. 10 is a schematic configuration diagram of a memory cell array according to a third embodiment of the present invention.
FIG. 11 is a schematic diagram for explaining an operation example in the third embodiment of the present invention.
FIG. 12 is a schematic configuration diagram of a memory cell array according to an application example of the third embodiment of the present invention.
FIG. 13 is a schematic configuration diagram of a memory cell array according to another application example of the third embodiment of the present invention.
FIG. 14 is a schematic diagram of a flash memory using a double word line decoding method.
FIG. 15 is a schematic diagram of a flash memory using a double bit line decoding method.
FIG. 16 is a schematic diagram of a conventional flash memory using a double word line decoding scheme for memory sub-arrays of different capacities.
[Explanation of symbols]
1 Memory cell array
1a Regular cell array
1c Hidden ROM cell array
2 Boot cell array
3 Address buffer
4 Address decoder
5 sense amplifiers
6 Input buffer / Output buffer
7 Control circuit
9 Voltage control circuit
10,20 line main decoder
11,11c, 21 row subdecoder
12,12c, 22 column selector
14 Main word line
15 Sub word line
16 Main bit line
17 Sub-bit line
51 floating gate
52 Control gate
90 Voltage control circuit

Claims (5)

Arranging a plurality of nonvolatile memory cells in a matrix, the sub-memory cell array connected a predetermined number of non-volatile memory cells in the same row in the sub-word lines and arrayed in a row direction, and a plurality of sub-word lines of the same row Connect the main word line in common via the row selector ,
Wherein as compared with the sub-memory cell array by arranging a plurality of nonvolatile memory cells less the total number in a matrix, arranges a plurality boot cell array in the row direction connecting a predetermined number of the nonvolatile memory cell to the sub-word line in the same row, In a semiconductor memory device in which main word lines are commonly connected to a plurality of sub word lines in the same row via a row selector,
A predetermined number of nonvolatile memory cells in the same column of each sub memory cell array are connected to sub bit lines, and a main bit line is commonly connected to a plurality of sub bit lines in the sub memory cell array via a column selector. And
A predetermined number of non-volatile memory cells in the same column of the boot cell array each connected to the sub-bit line, and connects the main bit line in common through a column selector to a plurality of sub-bit lines of the sub-memory cell array ,
While Aligns main bit line of the boot cell array to the main bit line of the sub-memory cell array, the length of the in sub-memory cell array and the boot cell array, and the same number of total number of each sub-bit line, each word line Substantially the same, and the interval between the main bit lines is substantially the same,
The main bit line of the sub-memory cell array and the main bit line of the boot cell array are independent, and can be operated separately by connecting to different sense amplifiers,
Each of the sub memory cell arrays and each of the boot cell arrays is an independently erasable capacity unit, and the storage capacity of the sub memory cell array is equal to the total storage capacity of the plurality of boot cell arrays. At least one of which is a special sub-memory cell array accessed by a method different from that of the other sub-memory cell arrays . 2. The semiconductor memory device according to claim 1, wherein the capacities of the sub memory cell arrays are equal to each other, and the storage capacities of the boot cell arrays are equal to each other. 3. The special sub memory cell array is selected by an address signal in the same range as the sub memory cell array when a special sub memory cell array selection signal is generated from an internal control circuit. The semiconductor memory device described in 1. 3. The semiconductor memory device according to claim 1, wherein the special sub memory cell array is a redundant memory cell array that can be replaced with a defective sub memory cell array generated in the sub memory cell array in the same row. In the same row as the sub memory cell array, at least one redundant memory cell array replaceable with a defective sub memory cell array generated in the sub memory cell array in the same row is further arranged, and a sub word line of the redundant memory cell array is connected to a row selector. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a main word line in common.

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