JP4034017B2 - Image signal processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image signal processing circuit mounted with a CCD camera, for example, for monitoring the front of a vehicle travel line and generating an alarm when a danger comes or used for an alarm of a protrusion from a white line. .
[0002]
[Prior art]
First, a rear-end collision alarm device that monitors the front of a running line using a CCD camera and generates a warning when a danger such as rear-end collision occurs will be described below with reference to FIG.
That is, reference numerals 1 and 2 denote first and second CCD cameras, which are a plurality of CCD elements for storing optical images from the outside as data, that is, storage registers 1a and 2a, and charge sweep signals XSUB (second storage) to the storage registers. charge stored between the output to the output of the transfer signal XSG (first signal) signal), accumulation register 1a, first and second transfer registers 1b respectively from 2a, the transfer signal instructing transfer 2b The first and second transfer registers 1b and 2b are transferred from the storage registers 1a and 2a each time they are supplied.
[0003]
The first and second CCD cameras 1 and 2 are provided in front of the left and right symmetrical positions with respect to the center axis of the vehicle. From the timing signal generating means 5 described later, the first and second CCD cameras are provided. A plurality of CCD drive control signals (horizontal synchronization signal HD (FIG. 4D), vertical synchronization signal VD) output in parallel via first and second drivers 3 and 4 provided corresponding to each of 1 and 2. (FIG. 4C), a signal generated from the shutter speed T or the like) is received (FIG. 4E).
[0004]
Further, each of the first and second CCD cameras 1 and 2 is synchronized with a signal generated based on the vertical synchronization signal VD from a timing signal generating means 5 described later, and a charge readout signal XSG (third signal: FIG. 4B low level state), image data obtained by the first and second CCD cameras 1 and 2 are respectively provided from the first and second accumulation registers 1a and 2a correspondingly. It transfers to the 1st and 2nd transfer registers 1b and 2b (refer FIG. 4F).
[0005]
Still further, the first and second CCD cameras 1 and 2 are arranged so that the timing signal generating means 5 has the horizontal synchronizing signal HD and the vertical synchronizing signal VD regardless of the timing at which the charge sweep signal XSUB (low level state in FIG. 4A) is supplied. The image data stored in the first and second transfer registers 1b and 2b is supplied to the corresponding first and second video signal processing means 6 and 7 on the basis of the charge read signal XSG having a constant period. (The same timing as in FIG. 4C) is supplied based on the CSYNC signal supplied from the timing signal generating means 5 to the first and second video signal processing means 6 and 7.
[0006]
That is, each of the first and second A / D conversion means 8 and 9 in relation to the signal processing speed while synchronizing with the signal created based on the vertical synchronization signal VD, as shown in FIG. For example, among the three data of the image data (FIG. 4F) transferred to the first and second video signal processing means 6 and 7 in synchronization with only the first one of the three input pulses of the vertical synchronizing signal VD. Two data are thinned out, and only one data is A / D converted.
The image data stored in the storage registers 1a and 2a provided corresponding to the first and second CCD cameras 1 and 2 respectively, that is, the image data stored in a plurality of CCD elements, is stored in the charge sweep signal XSUB. Canceled after receiving.
[0007]
The timing signal generator 5 receives a CCD drive control signal, a charge readout signal XSG, and a charge read signal XSG for the first and second drivers 3 and 4 while receiving an operation instruction signal such as a shutter speed T from a controller 10 described later. A charge sweep signal XSUB is supplied in accordance with a predetermined rule, and a CSYNC signal, a blank signal, a CCD sample hold signal, etc. for creating a video signal are supplied to each of the first and second video signal processing means 6 and 7. To do.
Since the CCD drive control signal is a clock signal for each of the first and second CCD cameras 1 and 2, the frequency thereof is extremely higher than the frequency of the charge read signal XSG and the charge sweep signal XSUB. Is set.
[0008]
The controller 10 reads image data for one screen supplied from each of corresponding first and second A / D conversion units 8 and 9 described later from the same address, and stores the image data for one screen read last time. One frame is compared with the same address, and the distance from the horizontal deviation of the read image data at that time to the preceding vehicle is calculated using a known triangulation method, When the distance is less than a predetermined value, that is, when the distance is too close, an alarm signal is output. Further, the controller 10 extracts the center line from the degree of change in brightness of the luminance signal constituting the adjacent image data, and also outputs an alarm signal when it is determined that the vehicle protrudes from the center line. Note that the protrusion from the center line is also determined using a known method.
[0009]
The first and second video signal processing means 6 and 7 receive the CSYNC signal from the timing signal generating means 5 as described above, and convert the image data supplied from the first and second transfer registers 1b and 2b into video signals. Then, the corresponding first and second A / D conversion means 8 and 9 are supplied.
The first and second A / D converters 8 and 9 are connected to the first and second transfer registers 1b and 2b based on the vertical synchronization signal VD supplied to the first and second video signal processors 6 and 7, respectively. A / D conversion is performed for one screen, that is, one frame while thinning out two screens in synchronization.
[0010]
That is, when the timing signal generating means 5 receives the operation instruction signal for instructing the shutter speed T or the like from the controller 10 and first supplies the CCD drive control signal to the first and second CCD cameras 1 and 2, Image data is sent from the first and second transfer registers 1b and 2b provided in the first and second CCD cameras 1 and 2 to the first and second video signal processing means 6 and 7 provided corresponding to the first and second transfer registers 1b and 2b, respectively. Is output.
As a result, the controller 10 creates and outputs various vehicle driving support data such as the inter-vehicle distance based on the digitized video signals supplied from the first and second A / D conversion processing means 8 and 9. .
[0011]
[Problems to be solved by the invention]
However, the CCD camera failure diagnosis described above is disclosed in Japanese Patent Application Laid-Open No. 11-27704, but the product does not require very high quality. However, there was no need to injure humans, so high quality assurance was never required, but when used as a safe driving support device for automobiles, high quality assurance was not possible. It is required and the need to perform diagnosis during use is required.
[0012]
In this case, there are the following problems.
(1) An analog signal that is susceptible to noise is transmitted to the signal lines from the CCD cameras 1 and 2 to the A / D conversion means 8 and 9, and in the present invention, a minute signal change of the analog signal must be captured. Therefore, a high S / N ratio is required.
[0013]
(2) Since a high-frequency clock pulse of 10 MHz or more exists in the output signals of the first and second drivers 3 and 4, particularly the CCD drive control signal, diagnosis is performed from the output terminals of the first and second drivers 3 and 4. Radiation noise is generated in the transmission line to the controller 10 having the function, and the first and second A / D conversion means 8 and 9 are connected from the output terminals of the first and second CCD cameras 1 and 2 near the transmission line. Signal lines exist through the first and second video signal processing means 6 and 7, and radiation noise is superimposed before the input to the first and second A / D conversion means 8 and 9, resulting in image data. The S / N ratio will decrease.
[0014]
(3) Among the CCD drive control signals output as a plurality of signal lines from the timing signal generating means, for example, when a signal line for outputting a horizontal drive signal generated based on the horizontal synchronization signal HD is disconnected When the obtained image data is viewed in units of screens, a vertical stripe pattern appears, which can be obtained in a normal state, such as a railing with a ladder next to it, a gate door, a partition fence between a road and a sidewalk, etc. This coincides with the image data when the image is taken by the CCD camera, and there is a possibility that the signal processing is performed as normal image data despite the failure of the timing signal generating means.
[0015]
Therefore, the present invention has been made in view of the above problems, and the first object is to provide a failure diagnosis function with a simple configuration to facilitate the discovery of a failure location, and the second object to be reliable. In addition, the failure diagnosis with high accuracy can be performed. The focus of the second invention is that the CCD camera is set to send out image data for a large number of screens per unit time, but the controller in the present invention requires all of the sent out image data. Instead, only one screen image data out of the three screen image data sent out is required.
[0016]
[Means for Solving the Problems]
An image signal processing circuit according to the present invention includes a CCD camera having a storage register for storing a front image and a transfer register for storing the image data from the storage register while updating the image data from the CCD camera into a digital quantity. A / D conversion means for converting, a first signal for instructing the CCD camera to start the shutter operation, and clearing the charge of the accumulation register by the image data, instructing the end of the shutter operation, and the image data A timing signal generating means for outputting a second signal for instructing transfer from the storage register to the transfer register, a third signal for transferring image data from the transfer register to the A / D conversion means, and the timing signal generating means Instructing the shutter speed of the CCD camera and based on the time difference between the first signal and the second signal. The shutter speed is calculated, and the calculated shutter speed is compared with the shutter speed instructed to the timing signal generating means to determine whether the timing signal generating means is normal. A controller for notifying or stopping the operation when it is determined.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described below with reference to FIG.
In FIG. 1, the same or equivalent components already described in FIG. 3 are denoted by the same reference numerals and detailed description thereof is omitted, and different portions, that is, the diagnostic function of the added controller 10 and its components are omitted. An additional circuit accompanying the addition of the diagnostic function will be described below.
[0018]
Reference numeral 11 denotes a voltage dividing circuit. The maximum amplitude value output from the output terminals of the first and second drivers 3 and 4 is 20V or more, and each voltage of the high-frequency CCD drive control signal is divided by resistance to 5V. Reduced to output.
Reference numeral 12 denotes a buffer IC with a gate terminal (G), which is commercially available, for example, in the form of HC541. In an equivalent circuit, a plurality of digital switches (normally in an OFF state) are individually independent, that is, electric Each of the digital switches is molded into one, and each input terminal is connected to the corresponding output terminal of the voltage dividing circuit 11 on a one-to-one basis. Each output terminal is connected to each corresponding input port of the controller 13. When a gate ON signal is supplied from the output port of the controller 13 to the gate terminal (G) of the buffer IC 12, all the digital switches are simultaneously turned ON.
[0019]
Controller 13 is with respect to the timing signal generating means 14, and issues an instruction of the shutter speed of the C CD camera 1,2. Therefore, the timing signal generating means 14 receives the instruction of the shutter speed, generates the charge readout signal XSG and the charge sweep-out signal XSUB, and supplies them to the CCD cameras 1 and 2 via the first and second drivers 3 and 4. Yes.
[0020]
The controller 13 receives the charge readout signal XSG and the charge sweep-out signal XSUB output from the timing signal generator 14, and determines whether the output time difference matches the instructed shutter speed to generate a timing signal. It is determined whether or not the means 14 is operating normally. If it is determined that there is a failure, a notification is made if necessary, or the operation of the apparatus is stopped.
[0021]
The controller 13 also has the following diagnostic function.
1). A point for supplying a gate ON signal to the gate terminal (G) of the buffer IC 12 is additionally provided, and a point for diagnosing whether the CCD drive control signal supplied from the buffer IC 12 is normal is added.
That is, the gate ON signal corresponds to the first and second video signal processing means 6 and 7 from the first and second video signal processing means 6 and 7 by the controller 13 via the timing signal generating means 14. The first and second A / D converters 8 and 9 do not output a signal permitting the supply of the video signal, that is, the first and second A / D converters 8 and 9 it is outputted during the time not performed D converter T '(Figure 2I see), with it in each of whether not there is supply of CCD driving control signal determined for each input port of the controller 13 from the buffer IC12 Based on this, the controller 13 diagnoses the first and second drivers 3 and 4, the timing signal generating means 14, and the signal lines connecting them, and if it is determined that a failure has occurred, reports are made as necessary. Or stop the operation of the device.
[0022]
2). The controller 13 is to first and second video signal processing means 6 through the timing signal generator 14, and supplies the C SYNC signal, performs an instruction to supply the image data which is a video signal of In the same manner as described above, an instruction to supply image data converted into a video signal is issued.
[0023]
At this time, since each of the first and second video signal processing means 6 and 7 superimposes the synchronization signal included in the CSYNC signal on the output image data, the controller 13 outputs the first and second video signals. Among the video signal image data output from each of the signal processing means 6 and 7, the synchronizing signal separation circuits 15 and 16 provided at the outputs of the first and second video signal processing means 6 and 7, respectively. The synchronization signals extracted by the first and second video signal processing means 6 and 7 are normal by determining whether or not the synchronization signals are extracted by the synchronization signal separation circuits 15 and 16. If it is determined that there is a malfunction, a notification is made if necessary, and the operation of the apparatus is stopped.
[0024]
3). The controller 13 diagnoses each of the first and second drivers 3 and 4, the timing signal generation means 14, and the first and second video signal processing means 6 and 7. If it is determined, it is notified as necessary, or the operation of the apparatus is stopped.
[0025]
【The invention's effect】
As described above, according to the present invention, the controller instructs the timing signal generating means to the shutter speed of the CCD camera and determines the time difference between the first signal and the second signal output from the timing signal generating means. When the shutter speed is calculated based on the result, the calculated shutter speed is compared with the shutter speed instructed to the timing signal generating means, and it is determined whether the timing signal generating means is normal. Is configured to notify or stop the operation, so that it is possible to easily find the fault location and to perform fault diagnosis with high accuracy and reliability.
[0026]
Further, even if radiation noise is radiated from the high-frequency digital signal line to the analog signal line from the CCD cameras 1 and 2 to the A / D conversion means, the analog signal can be reliably processed without being affected by the radiation noise.
[0027]
Further, of the plurality of signal lines of the CCD drive control signal supplied to the CCD camera, for example, when the signal line of the horizontal drive signal is disconnected, the railing, the gate door, the road having a structure in which the ladder is laid down It is possible to detect at an early stage that it cannot be distinguished from a partition fence or the like with the sidewalk, and the reliability of the apparatus can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a circuit block according to an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of each circuit block in FIG. 1;
FIG. 3 is an explanatory diagram of a conventional circuit block.
4 is a timing chart for explaining the operation of each circuit block in FIG. 3;
[Explanation of symbols]
1, 2 CCD camera 5, 14 Timing signal generating means 6, 7 Video signal processing means 8, 9 A / D conversion means 10, 13 Controller 11 Resistance dividing circuit 12 Buffer IC
15, 16 Sync signal separation circuit

Claims (1)

A CCD camera having a storage register for storing a front image and a transfer register for storing image data from the storage register while being updated;
A / D conversion means for converting image data from the CCD camera into a digital quantity;
A first signal for instructing the CCD camera to start the shutter operation and clearing the charge of the storage register by the image data, instructing the end of the shutter operation, and transfer from the image data storage register to the transfer register A timing signal generating means for outputting a second signal for instructing, a third signal for transferring image data from the transfer register to the A / D conversion means,
Instructs the shutter speed of the CCD camera with respect to the timing signal generating means calculates a shutter speed based on the time difference between the first signal and the second signal, said timing signal generator and the calculated shutter speed A controller that compares the shutter speed instructed with the means to determine whether or not the timing signal generating means is normal, and notifies or stops the operation when the timing signal is determined to be faulty. Image signal processing circuit.

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