JP4034477B2 - Interposer, manufacturing method thereof, and circuit module using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit board, and in particular, a circuit board suitable as a semiconductor chip carrier (referred to as an interposer) when a semiconductor chip is mounted on a wiring board such as a mother board or a daughter board, a manufacturing method thereof, and a circuit using the circuit board Regarding modules.
[0002]
[Prior art]
When a semiconductor chip is mounted on a wiring board (motherboard or daughter board), a method of mounting the package on an intermediate board called an interposer is often used. By adopting this interposer, the protection function of the semiconductor chip and the pitch conversion function of the connection terminals are ensured, and various economic effects are brought about.
[0003]
For example, since the handling of the semiconductor chip becomes easy, it becomes easy to inspect, and the rise in chip sorting can be suppressed. In addition, when considering the cost of infrastructure development for bare chip mounting and flip chip mounting, it is a great advantage that the conventional infrastructure used in the packaging process can be used.
[0004]
Recently, in semiconductor chips, the operation speed has increased year by year as the density of integrated circuit elements (hereinafter referred to as ICs) has increased. It is known that when the operation speed of the IC increases, the characteristics deteriorate due to switching noise generated inside the semiconductor chip and signal reflection at the connection portion of the signal line.
[0005]
In order to reduce switching noise, it is effective to install a decoupling capacitor between the ground terminal and the power supply terminal, and in order to suppress signal reflection, it is effective to provide a termination resistor on the signal line.
[0006]
It is effective to install the decoupling capacitor and the terminating resistor as close to the IC as possible, and it is desirable to form them directly on the semiconductor chip. However, in this case, the manufacturing process of the semiconductor chip is complicated and long, and the yield of the semiconductor chip is lowered due to the defect of the decoupling capacitor and the termination resistance.
[0007]
Further, if a decoupling capacitor and a termination resistor are arranged on the wiring board as external components, the connection distance between these components and the semiconductor chip becomes long, and the effects thereof become insufficient.
[0008]
In order to cope with these problems, it has been reported or proposed that a decoupling capacitor or a termination resistor is built in an interposer (semiconductor chip carrier).
[0009]
For example, an interposer with a built-in termination resistor is reported in Hitachi Review 73 (1991), pages 41 to 48, and interposers with a built-in decoupling capacitor are disclosed in Japanese Patent Laid-Open Nos. 6-318672 and 8-48595. Japanese Patent Laid-Open No. 9-213835 proposes an interposer in which both a decoupling capacitor and a terminating resistor are incorporated.
[0010]
[Problems to be solved by the invention]
Conventionally, ceramic substrates such as alumina, glass ceramic (consisting of borosilicate glass, cordierite glass, anorthite glass, etc.), mullite ceramic, etc. have been mainly used as the base substrate of the interposer. . As other base substrates, materials such as organic or inorganic polymers, polyimide-epoxy, epoxy-fiber glass, Teflon, silicon and the like have been proposed in JP-A-6-318672.
[0011]
In the conventional interposer described above, when a conductive via that electrically connects the two main surfaces of the base substrate is used for the signal line, the impedance is not controlled and reflection occurs, so that the electromagnetic shield No consideration has been given to the possibility of deterioration of the characteristics of the semiconductor chip as the IC operating speed increases, such as the occurrence of crosstalk.
[0012]
Accordingly, a first object of the present invention is to provide an interposer having a conductive via having a novel structure that eliminates the problems of reflection and crosstalk when the conventional conductive via is used as a signal line. .
[0013]
In general, a ceramic substrate having conductive vias that electrically connect two main surfaces of the front and back is manufactured by a so-called co-fired green sheet multilayer process including steps such as printing, drying, and firing of a thick film paste. For this reason, there is a change in dimensions that causes the sheet to shrink during firing, and its main surface is not necessarily smooth. For this reason, a matching layer for absorbing variations in dimensional change is required, and in order to form capacitors and resistors on the main surface, flattening and smoothing are required. This flattening / smoothing is difficult due to the presence of voids and the like. Accordingly, there is a concern that the interposer using the ceramic base substrate has a longer manufacturing process, lowers the manufacturing yield, and increases the manufacturing cost.
[0014]
In order to cope with this, it is conceivable to produce a decoupling capacitor and a terminating resistor by simultaneous firing. However, when the capacitor is built in the interposer, the material such as the dielectric is limited depending on the material of the base substrate and the manufacturing conditions, and it is necessary to increase the thickness of the dielectric layer, so that a low inductance capacitor is obtained. It is difficult. Even when a termination resistor is built in, it is basically difficult to require resistance value accuracy as the termination resistor.
[0015]
Accordingly, a second object of the present invention is to provide a circuit board configuration and a manufacturing process thereof that can simplify and shorten a manufacturing process in an interposer formation process as compared with a case where a ceramic substrate is used as a base substrate. is there.
[0016]
If organic (or inorganic) polymer, polyimide-epoxy, epoxy-fiber glass, or Teflon is used as the base substrate, the materials and processes used are limited due to its heat resistance and mechanical properties, and circuit boards that have the desired characteristics are not always available. It is not necessarily obtained. For example, even if a capacitor having a high capacitance density is incorporated in a circuit board using a perovskite compound having a high dielectric constant, an organic insulating substrate cannot perform a heat treatment process at 600 ° C. or higher. The dielectric constant cannot be realized.
[0017]
The third object of the present invention is to provide a circuit board with less process restrictions in forming an interposer compared to a case where an organic insulating resin such as an organic or inorganic polymer, polyimide-epoxy, epoxy-fiber glass, or Teflon is used as a base substrate. It is to provide a configuration and its manufacturing process.
[0018]
A fourth object of the present invention is to provide a highly reliable circuit module in which a semiconductor chip is mounted on a circuit board via the interposer.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, the present inventors have conducted various experiments and studies in consideration of forming a circuit module by mounting a semiconductor chip on a circuit board via an interposer (semiconductor chip carrier). As a result, the base substrate constituting the interposer is made of a conductive member, and the conductive via structure for electrically connecting the two main surfaces of the base substrate is a coaxial structure. We have obtained effective knowledge that an interposer consisting of an easily manufactured circuit board can be easily realized.
[0020]
The present invention has been made based on such knowledge. In summary, the interposer of the present invention forms the base substrate with a conductive member and electrically connects the two main surfaces of the base substrate. The conductive via has a coaxial structure.
[0021]
The characteristic points of the interposer of the present invention capable of achieving the first object will be specifically described below.
That is, the interposer of the present invention includes a base substrate made of a conductive member, a through hole connecting the two main surfaces of the base substrate, a first insulating layer filled in the through hole, and the first substrate. A conductive via provided in one insulating layer and electrically connecting the two main surfaces of the base substrate, and a mounting connection terminal formed on the two main surfaces of the base substrate The conductive via is provided in the base substrate via a first insulating layer to form a coaxial structure.
[0022]
According to this configuration, since the conductive via is surrounded by the conductive base substrate via the first insulating layer, a circuit board having the same structure as the coaxial cable and having the conductive via as a coaxial structure is provided. it can. Therefore, the impedance of the conductive via can be controlled by adjusting the dimensions of the conductive via, the first insulating layer, and the base substrate.
[0023]
Further, the circuit board of this configuration is provided with a semiconductor chip mounted on one main surface (referred to as a first main surface) of the circuit board and provided on the opposite main surface (second main surface). It is obvious that the present invention can be applied as an interposer by connecting a wiring board to the connection terminals. Here, when the connection terminals are bumps, surface mounting is possible, and the mounting density can be increased.
[0024]
Preferably, at least a part of the conductive via in which the two main surfaces of the base substrate are electrically connected to form a coaxial structure is formed of the same conductive member as the base substrate. Accordingly, the conductive via can be formed by processing the base substrate around the conductive via, and the manufacturing process of the circuit board can be simplified.
[0025]
The method of manufacturing an interposer according to the present invention capable of achieving the second and third objects relates to a method of forming a conductive via electrically insulated from a base substrate in a base substrate made of a conductive member. And at least (1) a step of forming a first through hole in the conductive base substrate, (2) a step of filling the first through hole with a first insulating layer, and (3) the first through hole. A step of forming a second through hole in the insulating layer; and (4) a step of filling the second through hole with a conductive material to form a conductive via having a coaxial structure.
[0026]
Further, the second and third objects are to at least (1) leave a region for forming the core portion of the conductive via on the first main surface of the conductive base substrate, and to have a predetermined depth in the outer periphery of this region. Forming a first annular groove, and (2) a first conductive via forming step of embedding a first insulating layer in the first annular groove;
(3) A second annular groove is formed on the second main surface of the base substrate in the same manner as the step of forming the first annular groove on the first main surface to form the first annular groove. And (4) a second conductive via forming step of exposing the buried first insulating layer and embedding the second insulating layer in the second annular groove, and forming a remaining region of the base substrate It is also achieved by a method for manufacturing an interposer, characterized in that a conductive via having a coaxial structure as a core wire is formed.
[0027]
Furthermore, (1) a first recess pattern having a predetermined depth to be a conductive via formation region is formed on the first main surface of the conductive base substrate, and (2) a first recess pattern is formed in the first recess pattern. 1 is embedded, and (3) a second recess pattern is formed in the first insulating layer, and then (4) a first conductive material is embedded in the second recess pattern. A conductive via forming step,
(5) A third recess pattern is formed on the second main surface of the base substrate in the same manner as the first recess pattern is formed on the first main surface, and the first insulating layer and (1) exposing the first conductive material, (6) embedding the second insulating layer in the third concave pattern, and (7) forming a fourth concave pattern in the second insulating layer. A second conductive via forming step of exposing the first conductive material again and then embedding the second conductive material in the fourth recess pattern. This can also be achieved by a method of manufacturing an interposer, characterized in that a conductive via having a coaxial structure having first and second conductive material buried layers as cores is formed in the region.
[0028]
In this case, when the first conductive via is formed as a part of the conductive via on the first main surface side, the second main surface side portion of the base substrate serves as a support portion of the circuit board. In the case where the second conductive via is formed as a part of the conductive via on the main surface side of 2, the portion on the first main surface side of the base substrate becomes a support portion of the circuit board.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
As the material of the base substrate constituting the interposer of the present invention, a refractory metal material having a melting point of 1000 ° C. or higher is desirable. Therefore, it is shown that the temperature up to 1000 ° C. is allowed for the base substrate itself, and the heat resistance of the base substrate does not become a factor of process limitation at temperatures below 1000 ° C.
[0030]
Therefore, when forming a capacitor on the base substrate, it is possible to form a dielectric layer made of a perovskite compound that requires heat treatment at, for example, 600 ° C. to 900 ° C.
[0031]
In addition, by using a refractory metal material for the base substrate, there are problems such as heat shrinkage during sintering in ceramic substrates and difficulties in surface smoothing and flattening due to voids, etc., heat resistance in organic insulating substrates, etc. This problem can also be avoided.
[0032]
Examples of such a refractory metal material include tungsten (W), tantalum (Ta), molybdenum (Mo), nickel (Ni), or at least nickel (Ni), chromium (Cr), cobalt (Co), aluminum ( The material can be appropriately selected from a metal group of an iron (Fe) alloy containing any one of (Al), and all of these materials have a melting point of 900 ° C. or higher.
[0033]
In the interposer of the present invention, it is desirable to form a thin film protective layer on the base substrate. The purpose of providing the thin film layer is to protect the base substrate from the process atmosphere, and considering the formation of a capacitor using a perovskite compound as a dielectric layer, a material having a heat resistance of up to about 1000 ° C. in an oxidizing atmosphere is provided. preferable.
[0034]
Examples of the material for the thin film protective layer include indium oxide, tin oxide, indium oxide / tin oxide mixture, zinc oxide, ruthenium oxide, rhodium oxide, rhenium oxide, iridium oxide, osmium oxide and other conductive oxides, Pt and Rd. The material may be selected from platinum group materials such as silicon oxide, silicon oxide, silicon nitride, aluminum oxide, titanium oxide, and other inorganic insulating materials. If necessary, it may be a multilayer film made of two or more kinds of materials.
[0035]
In order to improve the adhesion between the thin film protective layer and the base substrate, for example, titanium (Ti), tantalum (Ta), hafnium (Hf), tungsten (W), A thin film layer made of a material selected from chromium (Cr) and nitrides thereof, nickel (Ni), and titanium / tungsten (TiW) may be inserted.
[0036]
In the interposer of the present invention, the second insulating layer can be formed on at least one of the two main surfaces of the base substrate so as to be in contact with at least one of the base substrate and the thin film protective layer. With this configuration, an electric circuit element such as a resistance element or a capacitor can be formed on a base substrate made of a conductive member.
[0037]
In the method for manufacturing an interposer according to the present invention, when an electric circuit element such as a resistor element or a capacitor is built in, the resistor element and the capacitor are previously formed on the base substrate, and then the method for manufacturing the interposer described above is used. A conductive via having a coaxial structure may be formed in the base substrate.
[0038]
According to this method, even when a material having no heat resistance is used for the conductive via portion in the circuit element formation, a temperature process up to 1000 ° C. is allowed. For example, a dielectric layer made of a perovskite compound that requires heat treatment at 600 ° C. to 1000 ° C. can be formed, and a capacitor using these materials can be formed on the base substrate. The effect of using a refractory metal material having a melting point of can be utilized.
[0039]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0040]
1 to 6 show an interposer (circuit board) to which the present invention is applied in a cross-sectional view of a main part. FIGS. 7 to 9 are cross-sectional views of essential parts of a circuit board in which a thin film multilayer circuit, a capacitor, a resistance element, and the like are built in based on the circuit board shown in FIGS. is there.
[0041]
10 to 11 are cross-sectional views showing a principal part of a semiconductor device (circuit module) manufactured by applying the present invention.
[0042]
FIG. 12 is a cross-sectional view of an essential part showing an example of a circuit board formed by combining the circuit boards of FIGS. 1 to 9 to which the present invention is applied in multiple layers. 13 to 21 show manufacturing process diagrams of the respective examples.
[0043]
<Example 1>
FIG. 1 is a cross-sectional view of a principal part of three types of circuit boards according to the first embodiment of the present invention. The circuit boards 100, 101, and 102 shown in FIGS. 1A, 1B, and 1C have conductive vias 3 having the same structure, but an insulating layer on the base substrate. There are some differences in the presence or absence of the protective film and the structure of the terminals connected to the conductive via 3.
[0044]
In these drawings, the reference numerals are common to the respective drawings, 1 is a base substrate made of a conductive member, 2 is a first insulating layer, 3 is two main surfaces (front and back surfaces of the base substrate 1). 1 is a conductive via for electrically connecting the main surface 1 and the second main surface which is the back surface, 4 is a second insulating layer, and 5 is a conductive thin film formed on the second insulating layer 4. 6 and 7 are connection terminals, 8 is a thin film protective layer provided between the base substrate 1 and the second insulating layer 4, and 41 is a third layer formed on the second insulating layer. The insulating layer, 10 is the first main surface (front surface) side of the circuit board (or base substrate 1), and 20 is the second main surface (back surface) side of the circuit board (or base substrate 1). Yes.
[0045]
The first insulating layer 2 is provided between the base substrate 1 and the conductive via 3 in order to electrically insulate the base substrate 1 and the conductive via 3, and thereby the conductive via 3 is coaxial. Forming a structure. The second insulating layer 4 is an insulating layer formed in contact with the main surface of the base substrate 1. The third insulating layer 41 is an insulating layer formed above the second insulating layer 4 depending on the application.
[0046]
As shown in FIGS. 1A and 1C, the connection terminals 6 and 7 are in direct contact with the conductive via 3 and the second conductive thin film layer 5 in the circuit board 100 and the circuit board 102, respectively. 1B, the circuit board 101 in FIG. 1B is formed so as to be in electrical contact with the conductive via 3 through a through hole provided in the third insulating layer 41. . This is the difference between the circuit board 100 and the circuit board 102 and the circuit board 101.
[0047]
As shown in FIG. 1C, in the circuit board 102, the thin film protective layer 8 is sandwiched between the base substrate 1 and the second insulating layer 4. The presence or absence of the thin film protective layer 8 is different between the circuit board 100 and the circuit board 102.
[0048]
The conductive member applied in this embodiment is preferably a material having a melting point of 1000 ° C. or higher in consideration of the case where a circuit pattern, a capacitor, or the like is formed on the circuit board using a thick film paste. Examples of such a material include tungsten, nickel, molybdenum, tantalum, and the like. Also, iron alloys containing nickel, chromium, cobalt, aluminum, etc. are promising. The reason is that the processing is easy as used in the lead frame, and the thermal expansion coefficient and permeability can be adjusted by the composition.
[0049]
According to this configuration, the conductive via 3 is surrounded by the base substrate 1 made of a conductive member via the first insulating layer 2, and can have the same structure as the coaxial cable. In this case, the base substrate 1 is kept at the ground potential. That is, the interposer having the coaxial structure of the conductive vias 3 that electrically connect the two main surfaces of the front and back surfaces of the base substrate 1 can be realized by the circuit boards 100 to 102 shown in FIGS. 1 (a) to 1 (c). .
[0050]
The insulating member used for the first insulating layer 2 and the second insulating layer 4 may be selected in consideration of process consistency with the steps after these insulating layers are formed. For example, if the temperature process in the subsequent step is 400 ° C. or lower, application of an organic insulating resin is possible. When an organic insulating resin is used as the first insulating layer 2, it serves as a stress relaxation layer when a wiring board (not shown) or a semiconductor chip (not shown) is connected to the connection terminals 6 and 7. Can do.
[0051]
If the temperature process in the subsequent step is 400 ° C. or higher, silicon oxide, silicon nitride, aluminum oxide, or various ceramic materials may be used. In this case, considering the heat-resistant temperature of the base substrate 1, processes up to 1000 ° C are allowed in the post-process, and compared with the case where a base substrate made of an organic insulating resin material is used, the process limitations in circuit board formation Can be reduced.
[0052]
The material of the conductive via 3 may be selected in consideration of process consistency with the process after the formation of the conductive via 3 and ease of formation, but it is desirable to use a material having as low a resistivity as possible.
[0053]
In the circuit board 101 shown in FIG. 1B, a third insulating layer 41 is provided to protect the base substrate 1 and the conductive via 3 from the outside. Further, the third insulating layer 41 can relieve the stress received at the connection terminals 6 and 7 by connection to another circuit board (not shown) or a semiconductor chip (not shown), Generation of electromagnetic radiation noise can be suppressed. In this case, it is desirable to use an organic insulating resin as the third insulating layer 41.
[0054]
The circuit board 102 shown in FIG. 1C has a structure in which a thin film protective layer 8 is inserted between the main surface of the base substrate 1 and the second insulating layer 4 in the circuit board 100 of FIG. Yes. The thin film protective layer 8 is provided to protect the base substrate 1 or improve the adhesion between the base substrate 1 and the second insulating layer 4. Therefore, the thin film protective layer 8 is preferably an inorganic insulating material or noble metal excellent in environmental resistance and heat resistance, or a conductive oxide excellent in oxidation resistance.
[0055]
Examples of such inorganic insulating materials include silicon oxide, silicon nitride, aluminum oxide, and titanium oxide, white metal materials such as Pt and Ru as noble metals, and indium oxide, tin oxide, and indium oxide as conductive oxides. There are tin oxide mixtures (ITO), zinc oxide, ruthenium oxide, rhodium oxide, rhenium oxide, iridium oxide, osmium oxide and the like.
[0056]
Further, in order to improve the adhesion between the thin film protective layer 8 and the base substrate 1 or the second insulating layer 4, a new thin film layer may be inserted between the base substrate 1 or the second insulating layer 4. good. The material of the thin film layer to be inserted is preferably a refractory metal such as titanium, tantalum, hafnium, tungsten, chromium, nitrides thereof, titanium / tungsten alloy, or the like.
[0057]
In the circuit board 100 and the circuit board 102 shown in FIGS. 1A and 1C, the connection terminals 6 and 7 do not extend to the outside of the conductive thin film layer pattern 5, but the conductive thin film layer pattern 5 However, it may be formed on the conductive thin film layer 5 or the conductive via 3.
[0058]
In addition, in the circuit board 101 shown in FIG. 1B, the connection terminals 6 and 7 are formed so as to be in contact with only the conductive via 3, but at least one of the conductive via 3 and the conductive thin film layer 5 is used. If it is in contact with either one, it does not matter.
[0059]
The connection terminals 6 and 7 are stopped at the stage of terminal metallization, but providing a solder bump on this is different from the circuit board 100, 101, 102 on a wiring board (not shown) or semiconductor chip ( This is effective for soldering to a not-shown).
[0060]
In this embodiment, the second insulating layer 4 and the conductive thin film layer 5 are provided, but may be omitted if there is no practical problem.
Next, a method for manufacturing each circuit board 100, 101, 102 shown in FIGS. 1 (a) to 1 (c) will be described.
[0061]
13 (a) to 13 (h) are process flow diagrams showing an example of a manufacturing process of the circuit board 100 shown in FIG. With reference to this figure, the manufacturing process of the circuit board 100 is demonstrated sequentially.
[0062]
Fig. 13 (a) Process: Preparation of base substrate
The conductive member is cut to an appropriate size, and surface polishing is performed as necessary to make the base substrate 1 smooth. Next, the base substrate 1 is degreased and washed with a neutral or alkaline detergent to clean the surface.
[0063]
FIG. 13 (b) process: forming the first through hole in the base substrate
The first through hole 91 is formed in the base substrate 1 using a known method such as a photo etching method (including wet etching and dry etching) and a laser processing method.
[0064]
FIG. 13 (c) step: filling of the first insulating layer and formation of the second insulating layer
A first insulating layer 2 and a second insulating layer 4 are formed by filling the first through hole 91 with an organic insulating resin by a dip method and applying the organic insulating resin to the surface of the base substrate 1 and curing. If necessary, polishing or back etching is performed to flatten the surface. Although the dipping method is used here, other methods such as a printing method, spray coating, and transfer method may be used. Here, the first insulating layer 2 and the second insulating layer 4 are formed in the same process, but may be formed in separate processes by separating the processes.
[0065]
For example, a process including the steps of filling the first insulating layer 2, flattening / smoothing between the base substrate 1 and the first insulating layer 2, and forming the second insulating layer 4 can be considered. In this case, the selection range of the means for forming the second insulating layer 4 is greatly expanded. For example, a physical method such as a spin coating method, a sol-gel method, a sputtering method, a chemical vapor deposition method, or the like can be easily applied.
[0066]
FIG.13 (d) process: Formation of conductive thin film layer
The conductive thin film layer 5 is formed using a known method such as a physical method such as a sputtering method, a chemical vapor deposition method, a sol-gel method, or a plating method. The material of the conductive thin film layer 5 needs to be selected in consideration of consistency with subsequent processes such as the process of forming the conductive via 3. For example, when the conductive via 3 is formed of a copper plating film, it is effective to use a Cu / Cr laminated film (copper Cu is laminated on chromium Cr) as the material of the conductive thin film layer 5. is there. This is because the conductive via 3 can be formed by a conventional printed circuit board manufacturing process.
[0067]
FIG. 13 (e) process: formation of the second through hole in the first insulating layer
The second through hole 92 is formed in the first insulating layer 2 and the conductive thin film layer 5 by using a known method such as a photo etching method (including wet etching or dry etching) or a laser processing method. .
[0068]
Step 13 (f): Formation of conductive vias
A conductive via 3 is formed by filling a second through hole 92 provided in the first insulating layer 2 with a conductive member. If necessary, the flatness and smoothness of the surface of the circuit board 100 are ensured by polishing or the like. The conductive member selected to fill the second through hole 92 to form the conductive via 3 is a metal, a metal alloy, a composite of metal and nonmetal, or the like. As a formation method, a known method such as a physical method such as a plating method or a sputtering method, a chemical vapor deposition method, or a printing method is used.
[0069]
Figure 13 (g) Process: Separation of connection terminal
The unnecessary portion of the conductive thin film layer 5 other than the connection terminal region is removed by a known method such as photoetching. At this time, if the material constituting the conductive via 3 is present in an unnecessary region on the conductive thin film layer 5, it is also removed.
[0070]
Fig. 13 (h) Process: Connection terminal formation
A material suitable for the selected connection method is formed by a well-known film formation method such as sputtering, vacuum evaporation, or plating, and patterning is performed by a well-known method such as photo-etching to form connection terminals 6 and 7. To do. The material used for the connection terminal metallization is selected according to the connection method. However, when solder connection is assumed, an Au / Ni / Cr multilayer film, a Ni—Cu / Cr multilayer film, or the like is used. Here, A / B indicates that A is stacked on B.
[0071]
Thus, the circuit board 100 shown in FIG. 1A is completed. As is clear from the above description, according to this embodiment, it is possible to avoid the problem of surface unevenness due to the dimensional change of the circuit board 100 or voids, which is seen when the ceramic substrate is used as the base substrate 1. .
[0072]
Further, by using an organic insulating resin for the first insulating layer 2, effects such as stress relaxation can be obtained in connection with other wiring boards and semiconductor chips. In this embodiment, an organic insulating resin is used as the first insulating layer 2 and the second insulating layer 4, but inorganic insulating materials such as silicon oxide, silicon nitride, aluminum oxide and various ceramic materials. Can be used.
[0073]
In the case of the circuit board 100 shown in FIG. 1 (a), the method of manufacturing the circuit board 101 shown in FIG. 1 (b) applies the steps from FIG. 13 (a) to FIG. 13 (g). Is almost the same. In the case of the circuit board 101, the steps after FIG. 13 (g) are different from the case of the circuit board 100. The manufacturing process after FIG. 13 (g) will be described with reference to FIG.
[0074]
FIG. 14 (h) process: formation of third insulating layer
The third insulating layer 41 is formed by applying an organic insulating resin by a technique such as spin coating, drying and curing. Next, a through hole 93 is formed by a known method such as a photoetching method. In this case, the manufacturing process can be shortened by forming the third insulating layer 41 having the through hole 93 by the coating, drying, exposure, development, and curing processes using a photosensitive material as the organic insulating resin.
[0075]
Fig. 14 (i) Process: Connection terminal formation
A material suitable for the selected connection method is formed by a well-known film formation method such as sputtering, vacuum evaporation, or plating, and patterning is performed by a well-known method such as photo-etching to form connection terminals 6 and 7. To do. The material used for the connection terminal metallization is selected depending on the connection method. However, when solder connection is assumed, it is preferable to use an Au / Ni / Cr multilayer film, a Ni—Cu / Cr multilayer film, or the like. Here, A / B indicates that A is laminated on B.
[0076]
Thus, the circuit board 101 shown in FIG. 1B is completed. Even in this embodiment, it is obvious that the effects obtained by the method of manufacturing the circuit board 100 can be obtained. The effects obtained by providing the third insulating layer 41 are as described above.
[0077]
Next, the circuit board 102 shown in FIG. 1 (c) forms the thin film protective layer 8 after cleaning and cleaning the base substrate 1, and the processes after FIG. 13 (b) in the process shown in FIG. If done, it will be completed.
In this embodiment, an organic insulating resin is used as the third insulating layer 41, but inorganic insulating materials such as silicon oxide, silicon nitride, aluminum oxide, and various ceramic materials may be used.
[0078]
<Example 2>
FIG. 2 shows a cross-sectional view of the main part of a circuit board according to a second embodiment of the present invention. As shown in FIG. 2A, in the circuit board 200, the connection terminals 6 and 7 are directly in contact with the conductive thin film layer 5 on the second insulating layer 4 formed on the base substrate 1. In the circuit board 201 shown in FIG. 2B, the electrical connection with the conductive thin film layer 5 is made through a through hole in the third insulating layer 41 provided on the conductive thin film layer 5. It is formed to make contact. This is the difference between the circuit board 200 shown in FIG. 2 (a) and the circuit board 201 shown in FIG. 2 (b).
[0079]
The second embodiment is different from the first embodiment in the place where the connection terminals 6 and 7 are installed. In the case of the first embodiment, the connection terminals 6 and 7 are formed directly on the conductive via 3. On the other hand, in the second embodiment, connection terminals 6 and 7 are disposed on the conductive thin film layer 5 on the surface of the base substrate 1. Therefore, in the case of the second embodiment, the conductive via 3 and the connection terminals 6 and 7 are connected via the conductive thin film layer 5. Other structures, manufacturing methods, and the application of the present invention are the same as in the first embodiment. Therefore, also in the second embodiment, the same effects as in the first embodiment can be obtained by applying the present invention.
[0080]
It is also effective to have a structure in which the first embodiment and the second embodiment are combined. An example is shown in FIG. In this figure, reference numeral 160 denotes a circuit board having a structure in which the first embodiment and the second embodiment are combined. Other symbols are the same as those in FIG. 1 and FIG. In this embodiment, the connection terminal 6 is disposed on the conductive via 3 and the connection terminal 7 is disposed on the base substrate 1.
[0081]
When a semiconductor chip (not shown) is connected to the connection terminal 6 and a wiring board (motherboard, not shown) is connected to the connection terminal 7, the members constituting the base board 1 are selected according to the thermal expansion coefficient of the wiring board. When the first insulating layer 2 is made of an organic resin, the stress generated between the circuit board 160 and the wiring board is extremely small, and the stress generated between the circuit board 160 and the semiconductor chip is the first insulating layer. 2 Relaxed by the whole. That is, it is possible to provide a mounting system having excellent connection reliability between the substrates.
[0082]
<Example 3>
FIG. 3 shows a cross-sectional view of a relevant part of a circuit board according to a third embodiment of the present invention. As shown in FIG. 3A, the circuit board 300 has a structure in which the third insulating layer 41 is provided on the surface of the circuit board 100 shown in the first embodiment, and the circuit shown in FIG. The substrate 301 has a structure in which a third insulating layer 41 is provided on the surface of the circuit substrate 200 shown in the second embodiment. Other structures and the places where the present invention is applied are the same. Therefore, also in the third embodiment, the same effects as in the first embodiment can be obtained by applying the present invention.
[0083]
The feature of this embodiment resides in the manufacturing method, and the manufacturing method of the circuit board 300 will be described with reference to the process diagram of FIG. First, the steps from FIG. 13 (a) to FIG. 13 (f) shown in FIG. 13 of Example 1 are performed, and then the steps from FIG. 15 (g) to FIG. 15 (i) shown in FIG. I do. 15 (f) in FIG. 15 is the same as FIG. 13 (f) in FIG.
[0084]
Figure 15 (g) process: Formation of connection terminal layer
The connection terminal layers 60 and 70 are formed from a material suitable for the selected connection method by a known film formation method such as sputtering, vacuum deposition, or plating. The material selection of the connection terminal layers 60 and 70 to be formed is selected according to the connection method. However, when solder connection is assumed, an Au / Ni / Cr laminated film, a Ni-Cu / Cr laminated film, etc. Will be used. Here, A / B indicates that A is stacked on B.
[0085]
FIG.15 (h) process: Formation of connection terminal pattern
The connection terminals 6 and 7 are formed by removing unnecessary portions of the connection terminal layers 60 and 70 and the conductive thin film layer 5 by a known method such as a photoetching method.
[0086]
FIG. 15 (i) process: formation of third insulating layer
The third insulating layer 41 is formed by applying an organic insulating resin by a technique such as spin coating, drying and curing. Next, a through hole 93 is formed by a known method such as a photoetching method. In this case, the manufacturing process can be shortened by forming the third insulating layer 41 having the through hole 93 by the coating, drying, exposure, development, and curing processes using a photosensitive material as the organic insulating resin.
[0087]
Thus, the circuit board 300 is completed. In this embodiment, the connection terminal layers 60 and 70 are formed before the processing of the conductive thin film layer 5 and the formation of the third insulating layer 41. This is different from the first embodiment and the second embodiment.
[0088]
According to the manufacturing process in the present embodiment, the connection terminal layers 60 and 70 can be formed with little damage or contamination on the surface of the conductive thin film layer 5 or the conductive via 3, so that the connection terminal formation process is stable. Thus, the adhesion between the connection terminal layers 60 and 70 and the conductive thin film layer 5 and the conductive via 3 can be improved.
[0089]
In this embodiment, an organic insulating resin is used as the third insulating layer 41 in anticipation of stress relaxation after connection with another substrate. However, silicon oxide, silicon nitride, aluminum oxide, various kinds of materials are used. An inorganic insulating material such as a ceramic material may be used.
[0090]
<Example 4>
FIG. 4 shows a cross-sectional view of a relevant part of a circuit board according to a fourth embodiment of the present invention. The difference between the circuit board 400 shown in FIG. 4A and the circuit board 200 shown in FIG. 2A of the second embodiment, and the circuit board 401 shown in FIG. 4B and FIG. The difference of the circuit board 201 shown in FIG. That is, in the circuit boards 400 and 401 in the present embodiment, the conductive member is formed only on the side wall of the through hole 92 provided in the first insulating layer 2, and the core portion of the through hole 92 is not filled. It is. Such a conductive via 3 can be easily manufactured by using a conventional printed board manufacturing method. When the structure other than the conductive via 3 and the present invention are applied, the manufacturing method is the same as that in the second embodiment. Therefore, the effect obtained in the second embodiment by applying the present invention can also be obtained in the present embodiment.
[0091]
The surface area of the conductive via in this embodiment is larger than that in the second embodiment. For this reason, when the frequency of the signal to be handled becomes high and the influence of the skin effect becomes a problem, this embodiment is useful for preventing transmission characteristic deterioration.
[0092]
<Example 5>
FIG. 5 shows a cross-sectional view of a relevant part of a circuit board according to a fifth embodiment of the present invention. In FIGS. 5A and 5B, reference numerals 500 and 501 denote circuit boards of this embodiment, respectively, 21 and 22 denote a first insulating layer, and 31 and 32 denote conductive vias. The conductive vias 3 and the first insulating layer 2 in the circuit boards 100 and 101 shown in the first embodiment are the same as the conductive vias 31 and 32 and the first insulating layers 21 and 22 in the circuit boards 500 and 501 of the present embodiment. It is divided into each.
[0093]
In addition, although the second insulating layer 4 is provided on the base substrate 1 in the first embodiment, it is not provided in the present embodiment. This is the difference between the present embodiment and the first embodiment.
[0094]
The presence of the second insulating layer 4 is not an essential condition for the present invention, and may be provided as necessary. In addition, the conductive via 3 (31, 32) and the first insulating layer 2 (21, 22) may be integrated or separated. Therefore, the first embodiment and the present embodiment are basically the same in structure. That is, the circuit board 100 shown in the first embodiment corresponds to the circuit board 500 of this embodiment, and the circuit board 101 shown in the first embodiment corresponds to the circuit board 501 of this embodiment.
[0095]
As is clear from the above description, the effects obtained in the first embodiment can be obtained in this embodiment by applying the present invention. The apparent difference between this example and Example 1 is caused by the difference in the manufacturing method. Hereinafter, the manufacturing process of the circuit board 500 will be described with reference to the process diagrams of FIGS.
[0096]
Fig. 17 (a) Process: Preparation of base substrate
The conductive member is cut to an appropriate size, and surface polishing is performed as necessary to make the base substrate 1 smooth. Next, the base substrate 1 is degreased and washed with a neutral or alkaline detergent to clean the surface.
[0097]
Fig. 17 (b) Process: Thin film protective layer deposition
A thin film protective layer 8 is formed on the two main surfaces (front surface 10 and back surface 20) of the base substrate 1 using a well-known method such as a physical method such as a sputtering method, a chemical vapor deposition method, a sol-gel method, or a plating method. To do. The thin film protective layer 8 is selected from ceramic materials having excellent environmental resistance, precious metals, and conductive oxides having excellent oxidation resistance. In consideration of the process conditions, the reliability of the circuit board 500, and the like, it may be omitted if not necessary.
[0098]
FIG. 17 (c) process: formation of the first through hole in the base substrate
A first through hole 91 is formed in one main surface (for example, surface 10) of the base substrate 1 using a known method such as a photoetching method or a laser processing method. In this case, the through hole 91 is stopped in the middle of the base substrate 1 without being a through hole.
[0099]
FIG. 17 (d) process: Filling the first insulating layer
The first insulating layer 21 is formed by filling the first through hole 91 provided on the surface with an organic insulating resin by dipping and curing. If necessary, polishing or back etching is performed to flatten the surface. Although the dipping method is used here, other methods such as a printing method, spray coating, and transfer method may be used.
[0100]
FIG. 17 (e) Process: Formation of conductive thin film layer
The conductive thin film layer 5 is formed on the first main surface 10 provided with the through holes 91 by using a well-known method such as a physical method such as a sputtering method, a chemical vapor deposition method, a sol-gel method, or a plating method. The material of the conductive thin film layer 5 needs to be selected in consideration of consistency with subsequent processes such as a conductive via formation process. For example, when the conductive via is formed of a copper plating film, it is effective to use a chromium-copper laminated film (copper is laminated on chromium) as the conductive thin film layer 5. This is because a conductive via can be formed by a conventional printed circuit board manufacturing process.
[0101]
FIG. 17 (f) process: formation of the second through hole in the first insulating layer
A second through hole 92 is formed in the first insulating layer 21 using a known method such as a photo etching method or a laser processing method. Next, the process will be described with reference to the process diagram of FIG.
[0102]
FIG.18 (g) process: Formation of conductive via
A conductive via 31 is formed by filling a second through hole 92 provided in the first insulating layer 21 with a conductive member. If necessary, the flatness and smoothness of the surface of the circuit board 500 are secured by polishing or the like. The conductive member for filling the through hole 92 to form the conductive via 31 may be selected from a metal, a metal alloy, a composite of metal and nonmetal, and the like. As a forming method, a known method such as a physical method such as a plating method or a sputtering method, a chemical vapor deposition method, or a printing method is used.
[0103]
Fig. 18 (h) Process: Back side processing
While protecting the first main surface 10 on which the conductive via 31 is formed, by repeating the steps shown in FIG. 17 (c) to FIG. 18 (g), the conductive via 32 is removed from the second main surface of the base substrate 1. It is formed on the front surface (back surface) 20 side.
[0104]
Fig. 18 (i) Process: Formation of connection terminal layer
The connection terminal layers 60 and 70 are formed from a material suitable for the selected connection method by a known film formation method such as sputtering, vacuum deposition, or plating. The material used for the connection terminal layer is selected depending on the connection method. However, when solder connection is assumed, it is preferable to use an Au / Ni / Cr multilayer film, a Ni—Cu / Cr multilayer film, or the like. Here, A / B indicates that A is stacked on B.
[0105]
Fig. 18 (j) Process: Formation of connection terminals
Unnecessary portions of the connection terminal layers 60 and 70 and the conductive thin film layer 5 other than the connection terminal region are removed by a known method such as photoetching. In this embodiment, the thin film protective layer 8 is left without being removed, but may be removed if there is no problem.
[0106]
The circuit board 500 is completed through the above steps. In the manufacturing method described here, in the processing step on the first main surface 10 side, the portion on the second main surface 20 side serves as a support, and in the processing step on the second main surface 20 side, the processing has already been performed. The part on the first main surface 10 side that has been finished serves as a support part to support the manufacturing process.
[0107]
Further, the filling depth of the first insulating layers 21 and 22 is also shallower than in the manufacturing method shown in FIGS. For this reason, the manufacturing process in this embodiment is easier and more stable than the manufacturing method shown in FIGS.
[0108]
As is clear from the above description, according to this embodiment, it is possible to avoid the problem of surface unevenness due to a dimensional change of the circuit board 500 or voids, which is seen when the ceramic substrate is used as the base substrate 1. . In addition, by using an organic insulating resin for the first insulating layers 21 and 22, there is an effect that stress relaxation can be achieved in connection with other wiring boards (not shown) and semiconductor chips (not shown). can get.
[0109]
In this embodiment, an organic insulating resin is used as the first insulating layers 21 and 22. However, inorganic insulating materials such as silicon oxide, silicon nitride, aluminum oxide, and various ceramic materials may be used. Absent.
[0110]
The circuit board 501 is obtained by forming the third insulating layer 41 and then forming the connection terminals 6 and 7 after performing the steps from FIG. 17 (a) to FIG. 18 (h). This manufacturing process is the same as the process shown in FIGS. 14 (h) to 14 (i) shown in FIG.
[0111]
It is obvious that the effect obtained by the method of manufacturing the circuit board 500 can be obtained also in the case of the circuit board 501. In the circuit board 501, by providing the third insulating layer 41, the base substrate 1 and the conductive via 3 are protected from the outside world and are connected to other circuit boards (not shown) and semiconductor chips (not shown). Thus, the stress received at the connection terminals 6 and 7 is relaxed, and the generation of electromagnetic radiation noise from the circuit board 501 is suppressed.
[0112]
In this embodiment, an organic insulating resin is used as the third insulating layer 41, but inorganic insulating materials such as silicon oxide, silicon nitride, aluminum oxide, and various ceramic materials may be used.
[0113]
<Example 6>
FIG. 6 shows a cross-sectional view of a relevant part of a circuit board according to a sixth embodiment of the present invention. In FIGS. 6 (a), 6 (b), and 6 (c), 600, 601, and 602 represent circuit boards of this embodiment, and 61 and 71 represent connection terminals.
[0114]
The circuit board 600 shown in FIG. 6 (a) is the case where the connection terminals 6 and 7 are provided with the thin film protective layer 8 exposed, and has the simplest structure.
[0115]
In addition, the circuit board 601 shown in FIG. 6 (b) has the second insulating layer 4 formed on the circuit board 600 of FIG. 6 (a), and through the through hole provided in the second insulating layer 4. Thus, the connection terminal 61 and the connection terminal 71 are provided so as to be in electrical contact with the connection terminals 6 and 7.
[0116]
Furthermore, in the circuit board 602 shown in FIG. 6C, the second insulating layer 4 is formed before the connection terminals 6 and 7 are formed in the circuit board 600 of FIG. The connection terminals 6 and 7 are provided through through holes provided in the insulating layer 4.
[0117]
In this embodiment, at least a part of the conductive via 3 is made of the same material as that of the base substrate 1, and the first insulating layers 21 and 22 having two layers for electrical insulation between the conductive via 3 and the base substrate 1 are used. It is done by. This point is different from the circuit boards 100 and 101 shown in the first embodiment.
[0118]
That is, in the case of the present embodiment, it is considered that the conductive vias 31 and 32 having two layers are integrated in the fifth embodiment shown in FIG. 5 and the conductive via 3 is formed of the same member as the base substrate 1. That's fine. The basic structure is the same for the circuit boards 600 and 601 and the circuit board 500, and the circuit board 602 and the circuit board 501 are the same. Therefore, the effect obtained in the fifth embodiment by applying the present invention can also be obtained in this embodiment.
[0119]
Although the connection terminals 6 and 7 are formed on the conductive via 3, they may be provided on the base substrate 1 so as to be the embodiment shown in FIG. 2 or FIG.
[0120]
In the circuit board 601 and the circuit board 602 shown in FIG. 6B and FIG. 6C, the second insulating layer 4 is provided on the thin film protective layer 8 to protect the base substrate 1 and the conductive via 3 from the outside. is doing. Further, the second insulating layer 4 can relieve the stress received at the connection terminals 6 and 7 by connection to another circuit board (not shown) or a semiconductor chip (not shown), Generation of electromagnetic radiation noise can be suppressed. In this case, it is desirable to use an organic insulating resin as the second insulating layer 4.
[0121]
Next, a method for manufacturing the circuit board 600 shown in FIG. 6A, which is one of the present embodiments, will be described with reference to FIG.
[0122]
Fig. 19 (a) Process: Preparation of base substrate
A conductive member having a melting point of 1000 ° C. or higher is cut into an appropriate size to form a base substrate 1. If necessary, the surface of the base substrate 1 is polished to be smooth. Next, the base substrate 1 is degreased and washed with a neutral or alkaline detergent to clean the surface.
[0123]
FIG.19 (b) process: Thin film protective layer deposition
A thin film protective layer 8 is formed on the two main surfaces (front surface 10 and back surface 20) of the base substrate 1 using a well-known method such as a physical method such as a sputtering method, a chemical vapor deposition method, a sol-gel method, or a plating method. To do. The thin film protective layer 8 is selected from ceramic materials having excellent environmental resistance, precious metals, and conductive oxides having excellent oxidation resistance. In consideration of the process conditions, the reliability of the circuit board 600, and the like, it may be omitted if not necessary.
[0124]
FIG. 19 (c) process: formation of conductive vias on the first main surface side of the base substrate
A well-known method such as a photo etching method or a laser processing method is used to leave a region that becomes a conductive via on the first main surface (for example, the surface 10) of the base substrate 1 and to have a groove of a predetermined depth ( Through-hole 91) is formed. A part of the base substrate left in the through hole 91 becomes the conductive via 31 in a later process. That is, the through hole 91 is not formed as a through hole, but is stopped in the middle of the base substrate 1 and a groove is formed so as to surround the conductive via 31.
[0125]
FIG.19 (d) process: Filling the first insulating layer
The first insulating layer 21 is formed by filling the through hole 91 provided on the surface of the base substrate 1 with an organic insulating resin by dipping and curing. If necessary, polishing or back etching is performed to flatten the surface. Although the dipping method is used here, other methods such as a printing method, spray coating, and transfer method may be used.
[0126]
FIG.19 (e) process: formation of conductive via and first insulating layer on second main surface side
By repeating the step of FIG. 19 (c) and the step of FIG. 19 (d), the conductive via 32 and the first insulating layer 22 are also formed on the second main surface (back surface) 20 side of the base substrate 1. The conductive via 3 (consisting of the conductive vias 31 and 32, which is electrically separated from the base substrate 1 by the first insulating layer 2 (consisting of the first insulating layers 21 and 22) is made of the same material. Formed).
[0127]
FIG.19 (f) process: Formation of connection terminal
A connection terminal layer is formed from a material suitable for the selected connection method by a known film formation method such as sputtering, vacuum deposition, or plating. Next, unnecessary portions of the connection terminal layer other than the connection terminal formation region are removed by a known method such as photoetching to form the connection terminals 6 and 7. The material used for the connection terminal is selected depending on the connection method. However, when solder connection is assumed, it is preferable to use an Au / Ni / Cr multilayer film, a Ni—Cu / Cr multilayer film, or the like. Here, A / B indicates that A is stacked on B.
[0128]
Thus, the circuit board 600 shown in FIG. 6A is completed. In the manufacturing method described here, in the processing step on the first main surface 10 side, the portion on the second main surface 20 side serves as a support, and in the processing step on the second main surface 20 side, the processing has already been performed. The part on the first main surface 10 side that has been finished serves as a support part to support the manufacturing process. The manufacturing method in this embodiment has the following features, and the manufacturing process is shortened and a stable process compared to the manufacturing method shown in FIGS. 13 to 15 and the manufacturing method shown in FIGS.
[0129]
(1) Since the conductive via 3 is formed so as to be separated from the base substrate 1, the through hole formation in the first insulating layer and the filling process of the conductive via 3 are not required.
(2) The filling depth of the first insulating layers 21 and 22 is shallower than that in the manufacturing method shown in FIGS. 13 to 15, and is almost the same as that in the fifth embodiment.
[0130]
As is clear from the above description, even in the case of this embodiment, the problem of surface unevenness due to the dimensional change of the circuit board 600 and voids, etc. seen when the ceramic substrate is used as the base substrate 1 is avoided. it can.
[0131]
In addition, by using an organic insulating resin for the first insulating layers 21 and 22, there is an effect that stress relaxation can be achieved in connection with other wiring boards (not shown) and semiconductor chips (not shown). can get.
[0132]
In addition, since a member having a melting point of 1000 ° C. or higher is used as the base substrate 1, there are fewer restrictions on the process conditions than when an organic resin substrate is used.
[0133]
The circuit board 601 shown in FIG. 6 (b) is formed on the circuit board 600 produced in the manufacturing process shown in FIG. 19, such as a spin coating method, a physical method such as printing and sputtering, a chemical vapor deposition method, a sol-gel method, etc. A second insulating layer 4 is formed by using a well-known method, and a through hole is formed in the second insulating layer 4 by a method such as a photo-etching method. It is obtained by forming the connection terminals 6 and 7 using the film forming method and the photo etching method.
[0134]
In addition, the circuit board 602 shown in FIG. 6 (c) is subjected to physical processes such as spin coating, printing, sputtering, etc. after the manufacturing steps shown in FIGS. 19 (a) to 19 (e) shown in FIG. The second insulating layer 4 is formed by using a known method such as a method, a chemical vapor deposition method, or a sol-gel method, and a through hole is formed in the second insulating layer 4 by a local method such as a photo-etching method. It is obtained by forming the connection terminals 6 and 7 in this through hole portion using a well-known film formation method and a photoetching method.
[0135]
It is clear that the effects obtained by the method of manufacturing the circuit board 600 in FIG. 6 (a) can be obtained also in the case of the circuit board 601 and the circuit board 602 shown in FIG. 6 (b) and FIG. 6 (c). is there. In the circuit board 601 and the circuit board 602, the second insulating layer 4 is provided to protect the base substrate 1 and the conductive via 3, and other circuit boards (not shown) and semiconductor chips (not shown) In this connection, the stress applied to the connection terminals 6 and 7 is relaxed, and generation of electromagnetic radiation noise from the circuit boards 601 and 602 is suppressed. For this purpose, it is effective to form the second insulating layer 4 from an organic insulating resin.
[0136]
In this embodiment, an organic insulating resin is used as the first insulating layers 21 and 22 and the second insulating layer 4, but inorganic materials such as silicon oxide, silicon nitride, aluminum oxide and various ceramic materials are used. Insulating materials can be used.
[0137]
<Example 7>
FIG. 7 shows a cross-sectional view of the main part of a circuit board according to a seventh embodiment of the present invention. In the figure, 700 indicates a circuit board to which the present invention is applied, 11 indicates a resistance element, and 111 and 112 indicate electrodes of the resistance element 11. Other reference numerals are the same as those in FIGS. 1 and 6.
[0138]
This embodiment is an example in which a resistance element is built in a circuit board. That is, in the circuit board 700, the resistive element 11 is formed on the first main surface 10 of the circuit board 601 shown in FIG. 6B of the sixth embodiment, and the third insulating layer 41 is formed thereon. The connection terminal 61 is formed through a through hole provided in the third insulating layer 41.
[0139]
In order to use the resistance element 11 as a termination resistance, a semiconductor chip (not shown) is mounted on the first main surface 10, and one electrode 111 of the resistance element 11 is used as a signal terminal and the other electrode 112 is grounded. Connect to terminal or power supply terminal. According to such a circuit board, since the termination resistor is arranged near the semiconductor chip, the effect of suppressing signal reflection can be increased.
[0140]
In this embodiment, the circuit board 601 and the resistance element 11 shown in FIG. 6B of the sixth embodiment are integrally formed. Therefore, it is clear that the effect obtained in Example 6 can be obtained. Further, although the circuit board 601 is used as a circuit board integrated with the resistance element 11, any circuit board shown in the first to sixth embodiments may be used.
[0141]
<Example 8>
FIG. 8 shows a cross-sectional view of a relevant part of a circuit board according to an eighth embodiment of the present invention. In FIGS. (A), (b), and (c), 800, 801, and 802 are circuit boards to which the present invention is applied, 12 is a capacitor, 120 is a dielectric layer constituting the capacitor 12, and 121. 122 denotes an electrode constituting the capacitor 12, and 42 denotes a fourth insulating layer. Other reference numerals are the same as those in FIGS. 1 and 6. The third insulating layer 42 of the circuit board 802 is formed to protect the circuit board.
[0142]
In this embodiment, a capacitor element is built in a circuit board having a conductive via having a coaxial structure. That is, the circuit boards 800, 801, and 802 shown in FIGS. (A), (b), and (c) form the capacitor 12 on the first main surface 10 of the circuit board shown in the sixth embodiment. The third insulating layer 41 or the fourth insulating layer 42 is formed thereon, and the connection terminal 61 or the connection terminal 6 is provided through through holes provided in these insulating layers 41 and 42.
[0143]
The circuit board incorporating the capacitor 12 is the circuit board 600 or the circuit board 601 shown in the sixth embodiment in the case of the circuit boards 800 and 801, and the circuit board 602 in the case of the circuit board 802. The circuit board 801 incorporates two or more capacitors 12.
[0144]
In order to use the capacitor 12 as a decoupling capacitor, the electrodes 121 and 122 of the capacitor 12 are connected to the ground terminal and the power supply terminal, respectively. According to such a circuit board, since the decoupling capacitor can be disposed near the semiconductor chip, the switching noise generated in the semiconductor chip can be efficiently removed.
[0145]
In addition, if the magnetic permeability of the conductive via 3 connected to the ground terminal and the power supply terminal is increased, the propagation of noise generated in the semiconductor chip to other semiconductor chips can be suppressed, and the capacitance of the mounted capacitor 12 can be reduced. Can be small.
[0146]
In the present embodiment, since the circuit boards 600, 601, and 602 of the sixth embodiment and the capacitor 12 are integrally formed, it is obvious that the effects obtained in the sixth embodiment can be obtained. Further, although the circuit board shown in the sixth embodiment is used as the circuit board integrated with the capacitor 12, any circuit board shown in the first to sixth embodiments may be used.
[0147]
Next, a method for manufacturing a circuit board in the present embodiment will be described. In the case of the circuit boards 800 and 801, the capacitor 12 may be formed on the first main surface 10 of the circuit boards 600 and 601 shown in the sixth embodiment by a sequential lamination method. For example, the circuit board 600 is manufactured by the manufacturing method described in the sixth embodiment, and the second insulating layer 4, the electrode 122 of the capacitor 12, the dielectric layer 120 of the capacitor 12, the electrode 121 of the capacitor 12, and the third insulating layer. 41, the connection terminal 61 may be formed.
[0148]
According to this manufacturing method, the circuit board integrated with the capacitor 12 is not limited to the circuit boards 600 and 601 shown in the sixth embodiment, and any circuit board shown in the first to seventh embodiments may be used. . However, in this case, it is difficult to use a perovskite compound such as strontium titanate having a high dielectric constant for the dielectric layer when an organic insulating resin is used as the first insulating layers 21 and 22 and the second insulating layer 4. is there. This is because a high-temperature process such as heat treatment at 400 ° C. or higher is required to improve the crystallinity of the perovskite compound and increase the dielectric constant.
[0149]
In order to solve this, the inventors propose a circuit board 802 shown in FIG. 8 (c). This circuit board 802 is basically formed by integrating the capacitor 12 with the circuit board 602 shown in the sixth embodiment. Hereinafter, a method of manufacturing the circuit board 802 will be described with reference to the process diagrams of FIGS.
[0150]
Figure 20 (a) Process: Preparation of base substrate
A conductive member having a melting point of 1000 ° C. or higher is cut out to an appropriate size and used as the base substrate 1. If necessary, the surface of the base substrate 1 is polished to be smooth. Next, the base substrate 1 is degreased and washed with a neutral detergent or an alkaline detergent to clean the surface of the base substrate 1.
[0151]
FIG.20 (b) process: Film formation of thin film protective layer
The thin film protective layer 8 is formed on the two main surfaces 10 and 20 of the base substrate 1 using a well-known method such as a physical method such as a sputtering method, a chemical vapor deposition method, a sol-gel method, or a plating method. The thin film protective layer 8 is selected from ceramic inorganic materials having excellent environmental resistance, noble metals, and conductive oxides having excellent oxidation resistance.
[0152]
FIG. 20 (c) process: formation of the second insulating layer
The second insulating layer 4 is formed on the thin film protective layer 8 using a known method such as a physical method such as a sputtering method, a chemical vapor deposition method, a sol-gel method, a printing method, or a transfer method. In this case, an opening 210 is provided in a portion of the second insulating layer 4 corresponding to a place where the conductive via 3 is formed on the capacitor formation surface (first main surface 10). The opening 210 is formed in a size including the conductive via 3 inside the outer edge of the region where the first insulating layer 2 (that is, 21 and 22) is formed. This is important for ensuring the insulation between the base substrate 1 and the conductive via 3.
[0153]
Considering the formation process of the perovskite compound to be formed later, the second insulating layer 4 is preferably a material having a heat resistance of 1000 ° C. or higher, such as a silica-based, alumina-based, or titanium-based inorganic material. However, when the circuit board 802 is manufactured by a process of 400 ° C. or lower, an organic insulating resin such as polyimide may be used.
[0154]
FIG.20 (d) process: Capacitor electrode formation
One electrode pattern 122 (lower electrode) of the capacitor 12 is formed on the second insulating layer 4. In this case, the electrode film may be present in the opening 210 provided in the second insulating layer 4, but in view of ensuring the insulating property of the base substrate 1 of the conductive via 3, it is safer not to exist. It is. As the electrode layer, a known material used for a capacitor using a perovskite dielectric such as platinum may be used.
[0155]
FIG.20 (e) process: Formation of dielectric layer
A dielectric layer 120 made of a perovskite compound such as strontium titanate is formed on the lower electrode pattern 122 by using a well-known method such as a sputtering method, a chemical vapor deposition method, a sol-gel method, and photoetching. The dielectric layer 120 is patterned using a known method such as a method.
[0156]
At this time, the dielectric layer pattern 120 is formed so as to cover at least a part of the pattern edge of the lower electrode 122. In addition, it is important that the dielectric layer 120 does not exist in the opening 210 provided in the second insulating layer 4. Next, heat treatment at 600 ° C. to 900 ° C. is performed to improve the crystallinity of the dielectric layer 120.
[0157]
FIG.20 (f) process: Capacitor electrode formation
The other electrode pattern 121 (upper electrode) of the capacitor 12 is formed on the dielectric layer 120. In this case, the electrode pattern 121 (upper electrode) is disposed inside the second insulating layer 4 in consideration of securing insulation from the base substrate 1. As the electrode layer, a known material used for a capacitor using a perovskite compound as a dielectric, such as platinum, may be used.
[0158]
FIG. 20 (g) process: through-hole formation on the first main surface side of the base substrate
Through holes 91 are formed on the first main surface 10 side of the base substrate 1 in the same manner as in FIG. 19C of the sixth embodiment by a known method such as laser processing or photo etching. In this case, the through hole 91 is stopped in the middle of the base substrate 1 without being a through hole. The through hole 91 is formed as a groove so as to surround the portion 31 on the first main surface 10 side constituting the conductive via 3. As a result, the portion 31 on the main surface side of the conductive via 3 is separated from the base substrate 1. A thin film protective layer 8 is formed on the surface of the portion 31 on the main surface side of the conductive via 3, and in some cases, electrode layers 121 and 122 of the capacitor 12 are laminated. Hereinafter, description will be given with reference to the process diagram of FIG.
[0159]
Step (h) in FIG. 21: Filling the through hole provided in the base substrate with the first insulating layer and forming the third insulating layer on the first main surface side
A through-hole 91 provided in the first main surface 10 of the base substrate 1 is filled with an organic insulating resin by a dipping method so as to surround the first main surface side portion 31 constituting the conductive via 3. One insulating layer 21 is formed. In this step, the through hole 91 is filled with an organic insulating resin, and the third insulating layer 41 is formed on the first main surface. If necessary, polishing or back etching is performed to flatten the surface.
[0160]
Although the dipping method is used here, the present invention is not limited to this, and other methods such as a printing method, a spin coating method, a spray coating method, and a transfer method may be used. Further, although the first insulating layer 21 and the third insulating layer 41 are formed at the same time, they may be formed in separate steps. Step (i) in FIG. 21: Formation of the first insulating layer and the conductive via on the second main surface side of the base substrate.The process of FIG. 20 (g) and FIG. A portion 32 on the second main surface 20 side of the via 3 and a second main surface 20 side portion 22 of the first insulating layer are formed on the second main surface 20. Thereby, the conductive via 3 and the first insulating layer 2 are formed.
[0161]
Fig. 21 (j) Process: Formation of through hole for connection terminal
Through holes 82 and 92 are formed in the third insulating layer 41 in the region where the connection terminals are to be formed by a known method such as photoetching, laser processing, or ablation.
[0162]
FIG.21 (k) process: Formation of connection terminals
A connection terminal layer is formed from a material suitable for the selected connection method by a known film formation method such as sputtering, vacuum deposition, or plating. Next, unnecessary portions of the connection terminal layer are removed by a well-known method such as photoetching to form connection terminals 6 and 7. The material used for the connection terminal is selected depending on the connection method. However, when solder connection is assumed, it is preferable to use an Au / Ni / Cr multilayer film, a Ni—Cu / Cr multilayer film, or the like. Here, A / B indicates that A is stacked on B.
[0163]
FIG. 21 (l) process: protective layer formation
A fourth insulating layer 42 is formed using an organic insulating resin by a known method such as a spin coating method, a dipping method, a spraying method, a printing method, or a transfer method to form a protective layer. Next, a terminal connection through hole 93 is formed in the terminal connection portion by a known method such as photoetching or laser processing. In this process, the process can be reduced by using a material imparted with photosensitivity as the organic insulating resin and forming in the coating, exposure, and development processes.
[0164]
Thus, the circuit board 802 having the structure shown in FIG. 8C is completed. In the manufacturing method described here, the conductive via 3 is formed after the capacitor 12 that requires a process at a temperature higher than 400 ° C. is formed. Therefore, an organic insulating resin having poor heat resistance can be used as the material of the first insulating layers 21 and 22 that electrically separate the conductive via 3 and the base substrate 1. Thereby, when a semiconductor chip (not shown) or a wiring board (not shown) is connected to the circuit board 802, stress relaxation can be achieved. As described above, according to this embodiment, it is possible to provide a circuit board having a built-in circuit element requiring a temperature process of 500 ° C. to 1000 ° C. and having a conductive via having a coaxial structure.
[0165]
In the method for manufacturing the circuit board 802 shown in FIGS. 20 and 21, a perovskite compound is used as the dielectric layer 120 of the capacitor 12. However, the present invention is not limited to this. Further, the capacitor electrodes are not limited to materials suitable for the case where a perovskite compound is used as the dielectric layer.
[0166]
<Example 9>
FIG. 9 shows a cross-sectional view of a relevant part of a circuit board according to a ninth embodiment of the present invention. In the figure, 900 indicates a circuit board to which the present invention is applied, and 13 indicates a thin film multilayer wiring portion. Other symbols are the same as those in FIG. This embodiment is an example in which a thin film multilayer wiring portion is provided on the circuit board 600 shown in FIG. Accordingly, also in this embodiment, since the circuit board 600 according to the sixth embodiment and the thin film multilayer portion 13 are integrally formed, it is obvious that the effects obtained in the sixth embodiment can be obtained.
[0167]
In addition, although the circuit board 600 shown in Example 6 is used as a circuit board integrated with the thin film multilayer part 13, it is not limited to this, Any circuit board shown in Examples 1-8 is used. It can be used.
[0168]
<Example 10>
FIG. 10 shows a cross-sectional view of a relevant part of a circuit module according to a tenth embodiment of the present invention. 10 (a) and 10 (b), reference numerals 1000 and 1001 denote circuit modules (semiconductor devices) in which a semiconductor chip is mounted on a wiring board using the circuit board (interposer) of the present invention. In the figure, 14 indicates a semiconductor chip, 15 indicates a wiring board (motherboard or module board), and 16 indicates solder. Other reference numerals are the same as those of the circuit board shown in FIG. That is, this embodiment is an example in which the semiconductor chip 14 is mounted on the wiring board 15 using the circuit board 801 with a built-in capacitor shown in the eighth embodiment.
[0169]
The semiconductor device 1000 is an example in which one semiconductor chip 14 is mounted using the circuit board 801 incorporating the capacitor shown in FIG. 8B of the eighth embodiment. The semiconductor device 1001 is a circuit board having a capacitor. In this example, two or more semiconductor chips 14 are mounted using 801. Since the capacitor 12 is used as a decoupling capacitor, the electrodes 121 and 122 of the capacitor 12 are connected to the power supply terminal and the ground terminal.
[0170]
According to such a configuration, since the decoupling capacitor can be installed directly under the semiconductor chip 14, switching noise generated in the semiconductor chip 14 can be efficiently suppressed. Further, in this example, since the semiconductor chip 14 is mounted on the wiring board 15 using the circuit board 801 shown in FIG. 8B of Example 8, the present invention obtained in Example 8 is provided. An effect can be obtained.
[0171]
In this embodiment, the circuit board 801 shown in the eighth embodiment is used to mount the semiconductor chip 14 on the wiring board 15. However, the present invention is not limited to this circuit board 801. Any of the substrates shown in Embodiment 9 can be applied, and a circuit substrate may be appropriately selected according to the purpose.
[0172]
<Example 11>
FIG. 11 shows a cross-sectional view of a relevant part of a circuit module according to an eleventh embodiment of the present invention. In the figure, 1100 is a circuit module (semiconductor device) to which the present invention is applied, 2 is a first insulating layer made of a low dielectric constant material, and 23 is a first dielectric layer made of a high dielectric constant material such as a perovskite compound. An insulating layer 33 is a conductive via surrounded by a first insulating layer 23 made of a material having a high dielectric constant. Other symbols are the same as those in FIG.
[0173]
In this embodiment, in the circuit board 602 shown in FIG. 6B of the sixth embodiment, the first insulating layer around several conductive vias among the conductive vias 3 existing in the circuit board 602. The capacitor 12 is formed between the base substrate 1 and the conductive via 3 by changing to a material having a high dielectric constant. Therefore, this embodiment is also an example in which the semiconductor chip 14 is mounted on the wiring board 15 using a circuit board with a built-in capacitor.
[0174]
In this embodiment, the capacitor 12 is decoupled by connecting the base substrate 1 to the installation terminal and the conductive via 33 surrounded by the first insulating layer 23 made of a material having a high dielectric constant to the power supply terminal. Can be used. That is, since the decoupling capacitor can be installed immediately below the semiconductor chip 14, switching noise generated in the semiconductor chip 14 can be efficiently suppressed.
[0175]
Furthermore, in the case of this embodiment, as can be seen from the figure, the structure becomes simple compared to other embodiments. In addition, since the present embodiment is based on the circuit board 602 that is the sixth embodiment, the effect of the present invention obtained in the sixth embodiment can be obtained.
[0176]
<Example 12>
FIG. 12 shows a cross-sectional view of a relevant part of a circuit board according to a twelfth embodiment of the present invention. In the figure, reference numeral 1200 denotes a circuit board to which the present invention is applied. Other reference numerals are the same as those in FIG. In this embodiment, the circuit boards 801 shown in FIG. 8B of the eighth embodiment are connected to each other by using connection terminals formed on the second main surface side.
[0177]
This embodiment is effective when the circuit board 801 includes the capacitor 12 and the capacity of the capacitor is insufficient. This is because in the circuit board 1200, two capacitors 12 are connected in parallel. Since this embodiment is based on the circuit board 801 of the eighth embodiment, the effect of the present invention obtained in the eighth embodiment can be obtained.
[0178]
In this embodiment, the two circuit boards are connected by the connection terminals provided on the second main surface, but the connection terminals provided on the first main surface and the second main surface are provided. You can connect the connection terminals. In this embodiment, the circuit boards 801 are connected to each other. However, the present invention is not limited to this combination, and any combination of the circuit boards shown in the first to ninth embodiments may be used.
[0179]
For example, by connecting the circuit board 801 of the eighth embodiment and the circuit board 700 of the seventh embodiment, a circuit board having a built-in decoupling capacitor and termination resistor can be provided. According to such a configuration, since the termination resistor and the decoupling capacitor can be disposed near the semiconductor chip, switching noise and signal reflection can be efficiently suppressed.
[0180]
In addition, the termination resistor and the decoupling capacitor are formed on separate substrates, and the non-defective products can be combined with each other, and the yield of the circuit board incorporating the decoupling capacitor and the termination resistor can be improved.
[0181]
【The invention's effect】
As described in detail above, the intended object can be achieved by the present invention. That is, the interposer according to the present invention has a highly reliable interposer capable of preventing reflection and matching impedance when used as signal wiring because the conductive via has a coaxial structure, and a circuit module using the interposer. Can be realized.
[0182]
In addition, it can solve the problems due to thermal shrinkage and surface roughness during sintering when using a ceramic base substrate, and the heat resistance problem when using an organic resin substrate, and has a conductive via with a coaxial structure. A circuit board suitable as an interposer for mounting a semiconductor chip on a wiring board can be provided.
[0183]
According to the circuit board having such a configuration, the manufacturing process of the circuit board is simplified, which can greatly contribute to shortening the manufacturing process, improving the manufacturing yield, and reducing the manufacturing cost. Further, since a manufacturing process up to 1000 ° C. is possible, for example, a capacitor using a perovskite compound that requires a heat treatment step of 600 ° C. or more as a dielectric layer can be easily built in the interposer. As a result, a decoupling capacitor having a large capacitance can be arranged immediately below the semiconductor chip, and thus a semiconductor device capable of reducing switching noise without reducing the mounting density can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part of a circuit board according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part of a circuit board according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of a circuit board according to a third embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a circuit board according to a fourth embodiment of the present invention.
FIG. 5 is a cross-sectional view of a main part of a circuit board according to a fifth embodiment of the present invention.
FIG. 6 is a cross-sectional view of main parts of a circuit board according to a sixth embodiment of the present invention.
FIG. 7 is a cross-sectional view of a main part of a circuit board according to a seventh embodiment of the present invention.
FIG. 8 is a cross-sectional view of a main part of a circuit board according to an eighth embodiment of the present invention.
FIG. 9 is a cross-sectional view of main parts of a circuit board according to a ninth embodiment of the present invention.
FIG. 10 is a cross-sectional view of main parts of a circuit board according to a tenth embodiment of the present invention.
FIG. 11 is a cross-sectional view of main parts of a circuit board according to an eleventh embodiment of the present invention.
FIG. 12 is a cross-sectional view of main parts of a circuit board according to a twelfth embodiment of the present invention.
13 is a fragmentary cross-sectional view showing a manufacturing step of the circuit board 100 of the embodiment shown in FIG. 1; FIG.
14 is a fragmentary cross-sectional view showing a manufacturing step of the circuit board 101 of the embodiment shown in FIG. 1; FIG.
15 is a fragmentary cross-sectional view showing a manufacturing step of the circuit board 300 of the embodiment shown in FIG. 3; FIG.
FIG. 16 is a cross-sectional view of an essential part showing an example of a circuit board in which the first embodiment and the second embodiment are combined.
17 is a fragmentary cross-sectional view showing an example of a manufacturing process of the circuit board 500 shown in the fifth example of FIG. 5; FIG.
18 is a cross-sectional view of the principal part showing an example of the manufacturing process of the circuit board 500 shown in the fifth example of FIG. 5 following FIG. 17. FIG.
19 is a fragmentary cross-sectional view showing an example of a manufacturing process of the circuit board 600 shown in the sixth example of FIG. 6; FIG.
20 is a fragmentary cross-sectional view showing an example of a manufacturing process of the circuit board 802 shown in the eighth example of FIG. 8; FIG.
FIG. 21 is a cross-sectional view of the principal part showing an example of the manufacturing process of the circuit board 802 shown in the eighth embodiment of FIG. 8 following FIG. 20;
[Explanation of symbols]
1 ... Base substrate,
2, 21, 22, 23 ... the first insulating layer,
3, 31, 32, 33 ... conductive vias,
4 ... the second insulating layer,
41 ... third insulating layer,
42 ... fourth insulating layer,
5 ... 1st electroconductive thin film layer,
51. Second conductive thin film layer,
52. Third conductive thin film layer,
6, 61, 7, 71 ... connection terminals,
60, 70 ... connection terminal layer,
81, 82, 83 ... through holes,
10 ... 1st main surface (surface) of a circuit board (base board),
20 ... 2nd main surface (back surface) of a circuit board (base board),
11: Resistance element,
111, 112 ... electrodes of the resistance element 11,
12: Capacitor,
121, 122 ... Electrodes of the capacitor 12,
13 ... Thin film multilayer wiring part,
14 ... Semiconductor chip,
15 ... Wiring board (motherboard, module board),
16 ... solder,
210 ... an opening provided in the second insulating layer 4;
100,101,160,200,201,300,301,400,401,500,501,600,601,602,1200… Circuit board (interposer),
1000, 1001, 1100 ... Circuit modules (semiconductor devices).

Claims (7)

  A base substrate made of a conductive member, a through hole that connects two main surfaces of the base substrate, a first insulating layer filled in the through hole, and a first insulating layer provided in the first insulating layer A circuit board having conductive vias for electrically connecting the two main surfaces of the base substrate and mounting connection terminals formed on the two main surfaces of the base substrate, The conductive via is made of the same conductive member as the base substrate, and is provided in the base substrate via a first insulating layer to form a coaxial structure.   2. The interposer according to claim 1, wherein the base substrate is made of a refractory metal material having a melting point of 1000 [deg.] C. or higher.   The refractory metal material is tungsten (W), tantalum (Ta), molybdenum (Mo), nickel (Ni), or any one of nickel (Ni), chromium (Cr), cobalt (Co), and aluminum (Al). The interposer according to claim 2, wherein the interposer is selected from a metal group of an iron (Fe) alloy including two.   A platinum group metal material: indium oxide, tin oxide, indium oxide / tin oxide mixture, zinc oxide, ruthenium oxide, rhodium oxide, rhenium oxide, as a thin film protective layer on at least one of the two main surfaces of the base substrate Forming a conductive oxide containing at least one of iridium oxide and osmium oxide; and at least one material selected from the group of inorganic insulating materials containing at least one of silicon oxide, silicon nitride, aluminum oxide, and titanium oxide The interposer according to any one of claims 1 to 3, wherein the interposer is performed.   5. The second insulating layer is formed on at least one of the two main surfaces of the front and back surfaces of the base substrate so as to be in contact with at least one of the base substrate and the thin film protective layer. The interposer as described in any one of.   6. A circuit module in which a semiconductor chip is mounted and connected to a wiring board via an interposer, wherein the interposer is constituted by the interposer according to any one of claims 1 to 5. At least (1) leaving a region for forming the core portion of the conductive via on the first main surface of the conductive base substrate, and forming a first annular groove of a predetermined depth on the outer periphery of the region;
(2) a first conductive via forming step of embedding a first insulating layer in the first annular groove;
(3) A second annular groove is formed on the second main surface of the base substrate in the same manner as the step of forming the first annular groove on the first main surface to form the first annular groove. Exposing the buried first insulating layer;
(4) forming a conductive via having a coaxial structure using the remaining region of the base substrate as a core wire, including a second conductive via forming step of burying a second insulating layer in the second annular groove. An interposer manufacturing method characterized by the above.

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