JP4040446B2 - Evaluation method of MIS type semiconductor layer device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for evaluating the lifetime of a MIS type semiconductor device, and more particularly, to a method for evaluating the time until dielectric breakdown of a gate insulating film.
[0002]
[Prior art]
With the progress of miniaturization of semiconductor integrated circuit devices, the gate insulating film of MIS type semiconductor devices is becoming thinner and thinner. As the gate insulating film becomes thinner, the gate leakage current has increased. As a result, the complete dielectric breakdown test that has been carried out conventionally does not make sense, and instead, life prediction based on soft breakdown is about to become established. Hereinafter, soft destruction will be described.
[0003]
Neutral defects are induced in the silicon oxide film by electrical stress such as constant voltage or constant current. Since a leakage current flows through this neutral defect, the gate leakage current increases when electrical stress is continuously applied. It is defined that a soft breakdown phenomenon has occurred when an increase in gate leakage current hinders the operation of a semiconductor element (for example, an increase in subthreshold current).
[0004]
The method of measuring the elapsed time from application of an actual operating voltage to the gate electrode until soft breakdown is not practical because it requires an enormous amount of time per year. In order to shorten the evaluation time, a method is adopted in which a stress voltage (test voltage) higher than the actual operating voltage is applied to the gate electrode to shorten the time until soft breakdown. In order to shorten the test time, it is preferable to increase the test voltage as much as possible. However, when the test voltage is increased, excessive stress is applied to the gate insulating film, and there is a risk of underestimating the lifetime.
[0005]
In the method of evaluating the lifetime by applying a relatively low test voltage, the concept of defect generation probability (P _G ) and critical defect density (N _SBD ) has been proposed in order to avoid a prolonged test time. The defect generation probability is obtained by differentiating the increment of the leakage current induced by applying the test voltage to the gate electrode by the accumulated charge amount injected into the gate insulating film. The defect density in the gate insulating film when the gate insulating film causes soft breakdown is defined as the critical defect density.
[0006]
The cumulative charge amount injected into the gate insulating film is Q _INJ , the gate leakage current density when a test voltage is applied to the gate electrode is J _TEST , and the elapsed time (stress application time) from the start of the test voltage application is t. Then
[0007]
[Expression 1]
It is expressed.
[0008]
From the definition of critical defect density N _SBD ,
[Expression 2]
It can be expressed as. Here, Q _SBD is the total amount of charge injected into the gate insulating film until the gate insulating film is softly broken, and T _SBD is the time until soft breakdown. It is assumed that the gate leakage current J _TEST in equation (1) is almost constant regardless of the elapsed time.
[0010]
By obtaining a defect generation probability P _G for a plurality of test voltages can be obtained the relationship between the critical defect density N _SBD and lifetime T _SBD in each test voltage. If the critical defect density _NSBD is known, the lifetime at each test voltage can be obtained. The lifetime at the operating voltage can be predicted from the lifetime at a plurality of test voltages higher than the operating voltage. By making the test voltage close to the operating voltage, the accuracy of prediction can be increased.
[0011]
[Non-Patent Document 1]
DJ Dimaria, Defect generation in ultrathin silicon dioxide films produced by anode hole injection, Applied Physics Letters, American Institute of Physics, 23 October 2000, Vol. 77, No. 17, p.2716-2718.
[Non-Patent Document 2]
Muhammand Ashraful Alam, SILC as a Measure of Trap Generation and Predictor of T _BD in Ultrathin Oxides, IEEE Transactions on Electron Devices, February 2002, Vol.49, No.2, p.226-231.
[0012]
[Problems to be solved by the invention]
In the conventional method, since the dielectric breakdown time at the operating voltage is predicted from the soft breakdown time measured by applying a stress voltage about twice as high as the actual operating voltage, the error becomes large.
[0013]
An object of the present invention is to provide a semiconductor device evaluation method capable of more accurately predicting a dielectric breakdown time at an operating voltage.
[0014]
[Means for Solving the Problems]
According to one aspect of the invention,
(A) measuring an initial value of the threshold voltage of the MIS type semiconductor device;
(B) applying a measurement voltage between the substrate of the MIS type semiconductor device and the gate electrode to measure an initial value of the gate leakage current;
(C) a step of allowing a certain time to elapse while a test voltage is applied between the substrate and the gate electrode of the MIS type semiconductor device;
(D) applying a measurement voltage between the substrate of the MIS type semiconductor device and the gate electrode to measure a gate leakage current;
(E) a step of measuring a threshold voltage of the MIS type semiconductor device and obtaining a fluctuation amount from the initial value;
(F) correcting the gate leakage current measured in the step (d) based on the variation amount of the threshold voltage obtained in the step (e) to obtain a correction value of the gate leakage current ;
(G) A step of predicting the lifetime of the MIS type semiconductor device based on the initial value of the gate leakage current measured in the step (b) and the correction value of the gate leakage current obtained in the step (f). as the life evaluation method of MIS type semiconductor device having a <br/> is provided.
[0015]
By obtaining a correction value of the gate leakage current corrected based on the amount of fluctuation of the threshold voltage, the influence of the threshold fluctuation can be eliminated and the fluctuation of the gate leakage current can be observed.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Before describing the embodiments of the present invention, the results of measuring the gate leakage current by bringing the test voltage close to the operating voltage in order to improve the prediction accuracy of the lifetime of the MIS type semiconductor device will be described.
[0017]
FIG. 1 shows a circuit configuration used for the evaluation test. A P-channel MISFET is formed on the surface of the silicon substrate 1. The MISFET includes a source 2 and a drain 3 formed on both sides of the channel of the surface layer portion of the silicon substrate 1, a gate insulating film 4 formed on the channel, and a gate electrode 5 formed thereon.
[0018]
The voltage V _SUB applied to the silicon substrate 1, the voltage V _S applied to the source 2, and the voltage V _D applied to the drain 3 are set to the ground potential, and the measurement voltage V _SENS is applied to the gate electrode 5. In this state, the gate leakage current is measured, and the measurement result is an initial value J _GO . The measurement voltage V _SENS is equal to the operating voltage of the MISFET to be measured, for example. In this evaluation test, the measurement voltage V _SENS was set to −1V.
[0019]
The gate electrode 5 is left for a predetermined time with a test voltage V _TEST higher than the operating voltage applied. After a predetermined time, applying a measurement voltage V _SENS the gate electrode 5, to measure the gate leakage current J _GM. A step of leaving the test voltage V _TEST applied for a predetermined time and a step of measuring the gate leakage current J _GM by applying the measurement voltage V _SENS are repeated. Thus, it is obtained time dependence of gate leakage current J _GM in test voltage V _TEST.
[0020]
FIG. 2 shows the measurement result of normalized stress-induced leakage current (SILC). The horizontal axis in FIG. 2 represents the stress application time in the unit of “second”, and the vertical axis represents the normalized stress application leak current. Here, the normalized stress applied leakage current is the measured gate leakage current J _GM, a value obtained by dividing the incremental .DELTA.J _G from the initial value J _GO initial value _{J GO (ΔJ G / J GO} ) . In the figure, rhombus symbols, circle symbols, and black square symbols indicate normalized stress application leak currents when the test voltages V _TEST are −1.3 V, −1.4 V, and −1.5 V, respectively.
[0021]
When a test voltage is applied to the gate electrode, a gate leakage current flows and a defect is generated in the gate insulating film. It is considered that the gate leakage current increases due to this defect. However, as shown in FIG. 2, it can be seen that the normalized stress application leakage current actually decreases with time. When the gate leakage current decreases, the apparent defect generation probability becomes negative. For this reason, the conventional life prediction method using the defect generation probability and the critical defect density cannot be applied.
[0022]
Then, also described life prediction method according to a possible embodiment apply to the case where the gate leakage current is reduced.
FIG. 3 shows the time variation of the gate leakage current I _G when the test voltage V _TEST is applied. The horizontal axis represents the stress application time in the unit “second”, and the vertical axis represents the gate leakage current in the unit “μA”. The direction of current flowing from the gate electrode to the channel was positive. It can be seen that the gate leakage current when the test voltage V _TEST is applied decreases exponentially with time.
[0023]
Considering that the fluctuation of the gate leakage current depends only on the generation of defects in the gate insulating film, the gate leakage current cannot be reduced. The decrease in the gate leakage current is thought to be due to the occurrence of other physical phenomena besides the generation of defects in the gate insulating film.
[0024]
Since the gate leakage current when the test voltage is applied decreases exponentially as shown in FIG. 3, it is considered that the carrier trap in the gate insulating film is the cause of the reduction of the gate leakage current. .
[0025]
FIG. 4 shows the relationship between the variation amount of the threshold voltage and the stress application time. The horizontal axis represents the stress application time in the unit “second”, and the vertical axis represents the amount of fluctuation of the threshold voltage in the unit “mV”. The lower white circle, asterisk, black circle, upper white circle, and cross in the figure indicate the test voltages V _TEST of −1.4V, −1.8V, −2.0V, −2.2V, and −2.4V, respectively. The threshold voltage fluctuation amount is shown.
[0026]
As time passes, the threshold voltage shifts in the negative direction. This is a phenomenon called negative bias temperature instability (NBTI). In general, NBTI is caused by generation of positive fixed charges and generation of donor-type interface states.
[0027]
The amount of change S in the gate voltage required to change the drain current by one digit in the subthreshold region depends on the interface state. The threshold voltage fluctuated with the lapse of the stress application time, but S was almost constant. From this, it can be seen that, within the range of the test voltage applied in the experiment, the cause of the fluctuation of the threshold voltage is mainly the generation of fixed charges.
[0028]
Generation of positive fixed charges suppresses a tunnel current flowing through the gate insulating film. When the test voltage is relatively low, the decrease in the tunnel current due to the generation of fixed charges is more dominant than the increase in the leakage current due to the generation of defects in the gate insulating film, as shown in FIG. It is considered that the stress-applied leakage current decreases with time.
[0029]
In order to perform a life prediction with high accuracy, it is only necessary to eliminate the decrease in the tunnel current due to the generation of the fixed charge and obtain only the increase in the leakage current due to the defect generation from the measurement result of the stress applied leak current. In the embodiment described below, it is possible to eliminate the decrease in the tunnel current due to the generation of the fixed charge, and to predict the lifetime based on the increase in the leakage current due to the defect generation.
[0030]
Next, an evaluation method according to an embodiment of the present invention will be described. First, the substrate 1, source 2 and drain 3 of the MISFET to be evaluated shown in FIG. 1 are grounded, the measurement voltage V _SENS is applied to the gate electrode 5, and the initial value J _GO of the gate leakage current is measured. Here, the measurement voltage V _SENS is selected to be equal to the operating voltage (for example, −1 V).
[0031]
Next, a drain voltage, for example, −50 mV is applied to the drain 3, and an initial value of the threshold voltage V _TH is measured.
After measuring the initial value of the gate leakage current and the initial value of the threshold voltage, the substrate 1, the source 2 and the drain 3 are grounded, and a stress voltage (test voltage) V _TEST is applied to the gate electrode 5 for a predetermined time. For example, the test voltage V _TEST is applied to the gate electrode 5 for 100 seconds at regular time intervals. A state in which the test voltage V _TEST is applied to the gate electrode 5 is referred to as a “stress application state”. In addition, it is good also as a logarithmic interval instead of a fixed time interval.
[0032]
After the stress application state is continued for a predetermined time, the characteristics of the MISFET are measured by the following procedure.
First, the substrate 1, the source 2, and the drain 3 are grounded, and the measurement voltage V _SENS applied to the gate electrode 5 is changed in the vicinity of the operating voltage to measure the gate voltage dependency of the gate leakage current.
[0033]
FIG. 5 shows an example of the measurement result of the gate voltage dependency of the gate leakage current. The horizontal axis represents the gate voltage in the unit “V”, and the vertical axis represents the gate leakage current in the unit “μA”. The white circle symbol in the figure indicates the measured value of the gate leakage current. Measurements J _GM of gate leak current when the gate voltage is -1V is about 2.52Myuei.
[0034]
Next, the substrate 1 and the source 2 are grounded, -50 mV is applied to the drain 3, and the threshold voltage is measured. The amount of variation of the measured threshold from the initial value is calculated. Normally, the threshold voltage increases in the negative direction as shown in FIG.
[0035]
In the graph showing the relationship between the gate leakage current and the gate voltage shown in FIG. 5, the gate leakage current is corrected by the variation amount of the threshold voltage. Specifically, the measured value indicated by the white circle symbol is moved by the threshold voltage variation ΔVth in the direction in which the absolute value of the gate voltage decreases. The correction value of the gate leakage current is indicated by a white square symbol.
[0036]
A correction value J _GC of the gate leakage current when the gate voltage is the measurement voltage V _SENS (−1 V in this embodiment) is obtained. In the measurement example shown in FIG. 5, the correction value J _GC is about 2.6 μA. This correction value corresponds to the gate leakage current when it is assumed that there is no change in the threshold voltage. An increase ΔJ _GC of the correction value J _GC of the gate leakage current from the initial value J _GO is calculated. ΔJ _GC is divided by the initial value J _GO to normalize. This normalized value is referred to as “normalized stress application leak current after threshold correction”.
[0037]
By repeatedly performing the stress application state for a predetermined time and measuring the characteristics of the MISFET, the time variation of the normalized stress application leak current after threshold correction is obtained.
[0038]
FIG. 6 shows an example of the measurement result of the normalized stress application leak current after threshold correction. The horizontal axis represents the stress application time (elapsed time) in the unit of “second”, and the vertical axis represents the normalized stress application leak current after threshold correction. The rhombus symbols, white circle symbols, and black square symbols in the figure are the leakage currents with normalized stress applied after threshold correction when the test voltages V _TEST are -1.3V, -1.4V, and -1.5V, respectively. Indicates.
[0039]
It can be seen that the corrected normalized stress application leakage current increases with time. Each point of the graph shown in FIG. 6 is obtained by correcting each point of the normalized stress application leak current before correction shown in FIG. In the state before the correction, the normalized stress application leak current decreased with the passage of time, but the normalization stress application leak current started to increase by performing the correction. This increment is considered to correspond to an increase in defects generated in the gate insulating film.
[0040]
Assuming that the gate leakage current in the stress application state is J _TEST and the elapsed time from the start of the evaluation test is t, the accumulated charge amount Q _INJ injected into the gate insulating film 4 is
[0041]
[Equation 3]
It is expressed.
[0042]
FIG. 7 shows the relationship between the normalized stress application leak current (ΔJ _GC / J _GO ) after the threshold correction and the accumulated charge amount Q _INJ . The abscissa represents the accumulated charge amount Q _INJ in the unit “C / cm ² ”, and the ordinate represents the normalized stress application leak current after threshold correction. In the figure, the black diamond symbol, white square symbol, white triangle symbol, black circle symbol, and white circle symbol indicate that the test voltage V _TEST is −1.2V, −1.5V, −1.8V, −2.0V, and −, respectively. The normalized stress application leak current after threshold correction in the case of 2.2V is shown.
[0043]
It can be seen that the relationship between the normalized stress application leakage current and the accumulated charge amount after threshold correction plotted on the logarithmic scale can be approximated by a straight line.
The defect generation probability P _G is
[0044]
[Expression 4]
Defined by
[0045]
FIG. 8 shows the relationship between the defect generation probability P _G obtained from FIG. 7 and Equation (4) and the test voltage V _TEST . The horizontal axis represents the test voltage V _TEST in the unit of "V" and the ordinate represents a defective generation probability P _G in the unit of "cm ² / C." The white square symbol, black circle symbol, white triangle symbol, and black rhombus symbol in the figure have cumulative charge amounts Q _INJ of 1 × 10 ⁶ C / cm ² , 1 × 10 ⁵ C / cm ² , 1 × 10 ⁴ C, respectively. / cm ^2, and shows the defect generation probability when the ^{1 × 10 3 C / cm 2} . In FIG. 7, the normalized stress application leak current in the accumulated charge amount without the measurement point was obtained by extending an approximate straight line.
[0046]
In the range where the test voltage is −1.5 V or more, the relationship between the defect generation probability P _G and the test voltage V _TEST is approximated by a straight line. However, it can be seen that the defect generation probability P _G when the test voltage is −1.2 V deviates downward from the approximate straight line.
[0047]
As shown in FIG. 7, since the relationship between the normalized stress application leak current ΔJ _GC / J _GO after threshold correction and the accumulated charge amount Q _INJ can be linearly approximated on a logarithmic scale, the defect generation probability P _G Is
[0048]
[Equation 5]
It can be expressed as. Here, a is a proportional coefficient.
[0049]
Equation (5) is obtained for each test voltage V _TEST . That is, the proportional coefficient a is obtained for each test voltage V _TEST . When the relationship between the proportionality coefficient a and the test voltage V _TEST is plotted on a logarithmic scale graph, it is found that the relationship is almost linear. For this reason, the proportionality coefficient a is
[0050]
[Formula 6]
It can be expressed as.
[0051]
From equations (5) and (6), the defect generation probability P _G is
[0052]
[Expression 7]
It can be expressed as.
[0053]
From equations (2) and (7)
[0054]
[Equation 8]
Is obtained. The total charge amount Q _SBD the gate insulating film is injected into the gate insulating film until a soft breakdown, and time T _SBD up to the soft breakdown, using the gate leakage current J _TEST during stressing,
[0055]
[Equation 9]
It can be expressed as. From equations (8) and (9),
[0056]
[Expression 10]
It can be expressed as. If the critical defect density N _SBD is known, the relationship between the test voltage V _TEST and the time T _SBD until soft breakdown is determined from the equation (10).
[0057]
The critical defect density N _SBD is obtained by applying stress until the gate insulating film actually breaks down to obtain a cumulative charge amount Q _SBD until the dielectric breakdown, and applying this cumulative charge amount Q _SBD to equation (8). Can be determined.
[0058]
FIG. 9 shows the relationship between the time T _SBD until soft breakdown and the test voltage V _TEST . The horizontal axis represents the test voltage in the unit of “V”, and the vertical axis represents the time until soft breakdown in an arbitrary scale. In FIG. 9, the critical defect density N _SBD of the formula (10) is set to 1.
[0059]
Predict the soft breakdown time at the operating voltage of -1V from the five soft breakdown times when the test voltage is -1.2V, -1.5V, -1.8V, -2.0V, and -2.2V. be able to. The soft breakdown time when the test voltage is −1.2 V deviates from the line obtained by extending the relationship between the other four soft breakdown times and the test voltage. For this reason, when the soft breakdown time at the operating voltage is predicted from four points where the test voltage is larger in the negative direction than −1.5 V, it can be seen that the error increases. For example, in the case of FIG. 9, the predicted soft breakdown time except for the test voltage of −1.2 V is about one digit shorter than the predicted soft breakdown time including the test voltage of −1.2 V. ing. For this reason, there is a possibility that an element that originally satisfies the required specification of the soft breakdown time may be determined as not satisfying the required specification.
[0060]
As described above, the soft breakdown time can be obtained for at least three test voltages higher than the operating voltage, and the soft breakdown time at the operating voltage can be predicted from these soft breakdown times. In the above-described embodiment, the influence of threshold voltage fluctuation during stress application is eliminated, and the defect generation probability is obtained using the corrected gate leakage current. For this reason, even when the gate leakage current apparently decreases with time, the soft breakdown time can be obtained from the defect generation probability.
[0061]
In order to improve the prediction accuracy of the soft breakdown time, it is preferable that at least one of the selected test voltages is higher than the operating voltage and not more than 1.2 times the operating voltage.
[0062]
In the above embodiment, the case where the lifetime of the P-channel MISFET is measured has been described. However, the lifetime of the N-channel MISFET can also be measured by the same method.
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0063]
【The invention's effect】
As described above, according to the present invention, the influence of the threshold voltage variation due to the stress application is eliminated, and the soft breakdown time of the gate insulating film at the operating voltage is predicted using the defect generation probability and the critical defect density. be able to.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a measurement circuit used in an evaluation test.
FIG. 2 is a graph showing the relationship between normalized stress application leakage current and stress application time.
FIG. 3 is a graph showing the relationship between gate leakage current during stress application and stress application time.
FIG. 4 is a graph showing the relationship between the threshold voltage fluctuation amount and the stress application time.
FIG. 5 is a graph showing the relationship between measured and corrected values of gate leakage current and gate voltage.
FIG. 6 is a graph showing the relationship between normalized stress application leakage current and stress application time after threshold correction.
FIG. 7 is a graph showing a relationship between a normalized stress application leak current and a cumulative charge amount after threshold correction.
FIG. 8 is a graph showing a relationship between a defect generation probability and a test voltage.
FIG. 9 is a graph showing the relationship between the soft breakdown time and the test voltage.
[Explanation of symbols]
1 Silicon substrate 2 Source 3 Drain 4 Gate insulating film 5 Gate electrode

Claims (5)

(A) measuring an initial value of the threshold voltage of the MIS type semiconductor device;
(B) applying a measurement voltage between the substrate of the MIS type semiconductor device and the gate electrode to measure an initial value of the gate leakage current;
(C) a step of allowing a certain time to elapse while a test voltage is applied between the substrate and the gate electrode of the MIS type semiconductor device;
(D) applying a measurement voltage between the substrate of the MIS type semiconductor device and the gate electrode to measure a gate leakage current;
(E) a step of measuring a threshold voltage of the MIS type semiconductor device and obtaining a fluctuation amount from the initial value;
(F) correcting the gate leakage current measured in the step (d) based on the variation amount of the threshold voltage obtained in the step (e) to obtain a correction value of the gate leakage current ;
(G) A step of predicting the lifetime of the MIS type semiconductor device based on the initial value of the gate leakage current measured in the step (b) and the correction value of the gate leakage current obtained in the step (f). A method for evaluating the lifetime of a MIS type semiconductor device comprising: The steps (c) to (f) are repeated a plurality of times,
Further, in the step (g), when the correction value of the gate leakage current is changed from the initial value of the gate leakage current and the test voltage is started to be applied in the first step (c). The method for evaluating the lifetime of a MIS type semiconductor device according to claim 1, further comprising a step of obtaining a first relationship with an elapsed time from the time. Further, in the step (g), the initial value of the gate leakage current of the accumulated charge amount injected into the gate insulating film of the MIS type semiconductor device and the correction value of the gate leakage current from the first relationship. The method for evaluating the lifetime of a MIS type semiconductor device according to claim 2, further comprising a step of obtaining a second relationship with the amount of fluctuation from. Further, in the step (g), the gate insulating film of the MIS type semiconductor device at the test voltage is determined from the second relationship and the critical defect density at which the gate insulating film of the MIS type semiconductor device causes dielectric breakdown. 4. The method for evaluating the lifetime of a MIS type semiconductor device according to claim 3, further comprising a step of obtaining a time until dielectric breakdown. Further, a plurality of test voltages, said running step (c) ~ (g), determined Me a delay time of the gate insulating film of the MIS type semiconductor device is breakdown,
5. The MIS type semiconductor device according to claim 4, wherein the step (g) includes a step of predicting a time until a gate dielectric film of the MIS type semiconductor device breaks down at an operating voltage of the MIS type semiconductor device. Life evaluation method.