JP4041676B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device including a capacitive element.
[0002]
[Prior art]
In recent years, a semiconductor device using silicon as a semiconductor material often includes a capacitor element for performing an analog operation. Usually, the lower electrode in the capacitive element is formed of a polycrystalline silicon film or an impurity diffusion layer having a higher concentration than the impurity diffusion layer of a MOS transistor, for example, in order to suppress the depletion thereof.
[0003]
[Problems to be solved by the invention]
As described above, since the silicon layer constituting the lower electrode of the capacitive element has a higher concentration than the impurity diffusion layer of the MOS transistor, the following various problems occur.
[0004]
The first problem is that it is difficult to reduce the thickness of the capacitive insulating film.
[0005]
Usually, the capacitor insulating film is formed simultaneously with the gate insulating film of the transistor, that is, by the same material. Furthermore, recent semiconductor devices are required to have a plurality of film thicknesses as the gate insulating film. In this case, the oxidation process is performed by the number of film thicknesses of the gate insulating film. This is an almost integrated value of the film thickness obtained for each oxidation step.
[0006]
The gate insulating film of the transistor has an impurity concentration of about 10 ¹⁷ cm ^-3 -10 ¹⁹ cm ^-3 In contrast, the capacitor insulating film of the capacitor element has an impurity concentration of about 10%. ¹⁹ cm ^-3 It is formed on the lower electrode made of the above silicon. When this high concentration lower electrode is oxidized, an accelerated oxidation phenomenon occurs, and the amount of oxidation increases by about 30% compared to the case of a low concentration, so that the thickness of the capacitive insulating film further increases.
[0007]
As described above, when the thickness of the capacitive insulating film increases, the capacitance value per unit area decreases, so that the size of the capacitive element for obtaining a desired capacitance value increases. As a result, the chip area is reduced. There is a problem that it increases.
[0008]
The second problem is that when a capacitor element is provided on a trench type element isolation region, the film thickness of the insulating film embedded in the element isolation region is increased compared to the case where a capacitor element is not provided. is there.
[0009]
In general, an impurity is introduced into an active region of a transistor by ion implantation in order to form a well or adjust a threshold voltage before forming a gate insulating film. However, since crystal defects are generated by ion implantation when the substrate surface is exposed, a thermal oxidation process is performed after ion implantation to form an oxide film over the entire active region (sacrificial oxidation process). Thus, by forming and removing the oxide film (sacrificial oxide film), the implantation damage to the well is recovered and the surface of the well is cleaned.
[0010]
At this time, a thick oxide film is formed on the lower electrode of the capacitive element as compared with the transistor formation region by accelerated oxidation. For this reason, when the oxide film is removed by etching or the like, the etching amount of the oxide film is determined by the film thickness of the upper portion of the lower electrode of the capacitive element. Accordingly, the amount of etching with respect to the oxide film is increased as compared with a semiconductor device without a capacitor element. Here, when the etching amount with respect to the oxide film increases, the etching amount of the insulating film made of normal silicon oxide embedded in the element isolation region also increases. For this reason, when a so-called film reduction occurs in which the upper surface of the insulating film is lower than the substrate surface, the reliability at the edge of the element isolation region in the gate insulating film deteriorates, and the variation in the operating characteristics of the transistor increases. There is a problem that.
[0011]
Hereinafter, an example of a method for manufacturing a semiconductor device including a conventional capacitive element will be described with reference to the drawings.
[0012]
6 (a) to 6 (d) and FIGS. 7 (a) to 7 (d) show cross-sectional structures in the order of steps of a conventional method for manufacturing a semiconductor device.
[0013]
First, as shown in FIG. 6A, an element isolation region 102 made of trench isolation or the like is selectively formed on a semiconductor substrate 101 made of silicon to form an element active region 101a.
[0014]
Next, as shown in FIG. 6B, an impurity concentration of about 1 × 10 6 is formed on the semiconductor substrate 101. ¹⁹ cm ^-3 A lower electrode forming film of a capacitor element made of n-type polycrystalline silicon is deposited to a thickness of about 300 nm. Thereafter, patterning is performed so as to leave the upper part of the element isolation region 102 in the deposited lower electrode formation film, and the lower electrode 103 of the capacitor element is formed in the element isolation region 102.
[0015]
Next, as shown in FIG. 6C, for example, impurity ions for determining the threshold voltage of the transistor are ion-implanted into the element active region 101a, and then the entire surface of the semiconductor substrate 101 including the lower electrode 103 is formed. Thermal oxidation is performed to form a first oxide film 104A on the surface of the lower electrode 103, and a second oxide film 104B is formed on the surface of the element active region 101a. At this time, accelerated oxidation due to impurities becomes significant in the first oxide film 104A covering the lower electrode 103 made of a relatively high concentration of n-type polycrystalline silicon, and the film thickness is the first oxide film on the element active region 101a. This is about 1.3 times the thickness of the second oxide film 104B.
[0016]
Next, as shown in FIG. 6D, the first oxide film 104A and the second oxide film 104B are removed by wet etching until the lower electrode 103 is exposed. At this time, since the exposed portion of the insulating film embedded in the element isolation region 102 is also etched and dug simultaneously, the upper surface of the element isolation region 102 is lower than the upper surface of the element active region 101a.
[0017]
Next, as shown in FIG. 7A, a capacitor insulating film formation film 105A and a gate oxide film formation film 105B are formed on the surfaces of the lower electrode 103 and the element active region 101a by thermal oxidation treatment. Here, the film thickness of the gate oxide film formation film 105B is set to about 10 nm, and as described above, the accelerated oxidation phenomenon due to the high concentration impurity becomes remarkable in the capacitor insulating film formation film 105A, and the gate oxidation film The film thickness is about 1.3 times that of the film forming film 105B.
[0018]
Next, as shown in FIG. 7B, an electrode formation film 106 made of n-type polycrystalline silicon having a thickness of about 200 nm is deposited on the entire surface of the semiconductor substrate 101.
[0019]
Next, as shown in FIG. 7C, the upper portion of the lower electrode 103 in the deposited electrode forming film 106 and the capacitor insulating film forming film 105A is selectively etched, so that the upper portion from the electrode forming film 106 is removed. An electrode 106a is formed, and a capacitor insulating film 105a is formed from the capacitor insulating film forming film 105A. At the same time, the upper portion of the element active region 101a in the electrode formation film 106 and the gate oxide film formation film 105B is selectively etched to form the gate electrode 106b from the electrode formation film 106 and the gate oxide film formation. Gate oxide film 105b is formed from film 105B.
[0020]
Next, as shown in FIG. 7D, ion implantation using the gate electrode 106b as a mask is performed in the element active region 101a to form the source / drain diffusion layer 108, thereby completing the semiconductor device.
[0021]
As described above, in the conventional semiconductor device, the first problem that it is difficult to reduce the thickness of the capacitor insulating film 105a and the reduction in the thickness of the insulating film embedded in the element isolation region 102 do not provide the capacitor element 107. It has the 2nd problem of increasing compared with the case.
[0022]
The first object of the present invention is to solve the above-mentioned conventional problems and to reduce the thickness of a capacitor insulating film without increasing the number of steps in a method of manufacturing a semiconductor device including a capacitor element. The second object is to prevent the area from being reduced.
[0023]
[Means for Solving the Problems]
In order to achieve the first object, a first method of manufacturing a semiconductor device according to the present invention includes a MOS type semiconductor element having a gate insulating film and a capacitive element having a capacitive insulating film on one semiconductor substrate. A method for manufacturing a semiconductor device to be formed includes a step of simultaneously forming a gate insulating film and a capacitor insulating film in a reduced-pressure water vapor atmosphere.
[0024]
According to the first method for manufacturing a semiconductor device, since the gate insulating film and the capacitor insulating film are formed simultaneously in a reduced-pressure water vapor atmosphere, the accelerated oxidation phenomenon of the insulating film is suppressed. As a result, even when the capacitor insulating film is formed on the impurity region having a higher concentration than the gate insulating film, the thickness of only the capacitor insulating film does not increase compared to the gate insulating film. Thus, it is possible to reduce the thickness of the capacitive insulating film.
[0025]
In the first method for manufacturing a semiconductor device, the step of forming an element isolation region in a semiconductor substrate prior to the step of forming a gate insulating film and a capacitor insulating film, and an impurity concentration of about 1 on the element isolation region. × 10 ¹⁹ cm ^-3 Preferably, the method further includes the step of forming the lower electrode film made of silicon, and the capacitor insulating film is formed on the lower electrode film.
[0026]
The first semiconductor device manufacturing method includes a step of forming an element active region on the semiconductor substrate before the step of forming the gate insulating film and the capacitor insulating film, and the element active region. Impurities at a concentration of about 1 × 10 ¹⁹ cm ^-3 It is preferable to further include a step of forming a lower electrode layer in the element active region by implanting in the above manner, and forming the capacitor insulating film on the lower electrode layer.
[0027]
The first method for manufacturing a semiconductor device includes a step of forming a gate electrode on the gate insulating film and forming an upper electrode on the capacitive insulating film after the step of forming the gate insulating film and the capacitive insulating film. Is preferably further provided.
[0028]
In order to achieve the second object, a second method of manufacturing a semiconductor device according to the present invention includes a MOS semiconductor element having a gate insulating film and a capacitor element having a capacitive insulating film on one semiconductor substrate. A method for selectively forming an element isolation region on a semiconductor substrate and forming an element active region partitioned by the formed element isolation region, and a method for manufacturing the semiconductor device to be formed on the element isolation region , Concentration is about 1 × 10 ¹⁹ cm ^-3 By forming the lower electrode film made of silicon containing n-type or p-type impurities as described above, and oxidizing the surface of the semiconductor substrate including the lower electrode film in a reduced-pressure water vapor atmosphere, the lower electrode film and Forming an oxide film on the surface of the semiconductor substrate; forming a gate insulating film on the device active region after removing the oxide film by etching; and forming a capacitive insulating film on the lower electrode film; Forming a gate electrode on the gate insulating film and forming an upper electrode on the capacitor insulating film.
[0029]
According to the second method for manufacturing a semiconductor device, the concentration is about 1 × 10 6 above the element isolation region. ¹⁹ cm ^-3 After forming the lower electrode film made of silicon containing the above impurities, the surface of the semiconductor substrate including the lower electrode film is oxidized in a reduced-pressure water vapor atmosphere, thereby preventing contamination of the lower electrode film and the surface of the semiconductor substrate. In order to form an oxide film (sacrificial oxide film) for this purpose, the accelerated oxidation phenomenon does not occur in the oxide film formed on the surface of the lower electrode film made of silicon containing a relatively high concentration of impurities. Therefore, only the oxide film on the lower electrode film does not become thicker than the oxide film on the element active region. Therefore, when the oxide film on the lower electrode film is removed thereafter, the element isolation is performed. It is possible to prevent the film from being reduced around the lower electrode film in the region.
[0030]
In order to achieve the second object, a third method of manufacturing a semiconductor device according to the present invention includes a MOS type semiconductor element having a gate insulating film and a capacitive element having a capacitive insulating film on one semiconductor substrate. And a step of selectively forming an element isolation region on a semiconductor substrate and forming a capacitor element formation region and an element active region partitioned by the formed element isolation region. The impurity concentration in the capacitor element formation region is about 1 × 10 ¹⁹ cm ^-3 By injecting so as to achieve the above, an oxide film is formed on the surface of the lower electrode layer and the active region of the device by oxidizing the surface of the semiconductor substrate in a reduced pressure water vapor atmosphere in the step of forming the lower electrode layer And after removing the oxide film by etching, forming a gate insulating film on the device active region and forming a capacitive insulating film on the lower electrode layer; and forming a gate electrode on the gate insulating film And forming an upper electrode on the capacitor insulating film.
[0031]
According to the third method for fabricating a semiconductor device, the impurity concentration in the capacitor element formation region is about 1 × 10. ¹⁹ cm ^-3 After the lower electrode layer is formed by implanting as described above, the surface of the semiconductor substrate is oxidized in a reduced-pressure water vapor atmosphere to prevent contamination and implantation on the surface of the lower electrode layer and the element active region. Since an oxide film (sacrificial oxide film) for recovering damage is formed, the accelerated oxidation phenomenon does not occur in the oxide film formed on the surface of the lower electrode layer made of silicon containing a relatively high concentration of impurities. For this reason, since only the oxide film on the lower electrode layer does not become thicker than the oxide film on the element active region, element isolation that occurs when the oxide film on the lower electrode layer is removed thereafter. It is possible to prevent film loss in the region.
[0032]
In the first to third semiconductor device manufacturing methods, hydrogen and oxygen are introduced into a chamber for oxidation treatment in a reduced-pressure steam atmosphere, and the introduced hydrogen and oxygen are reacted on a heated semiconductor substrate. It is preferable to produce it.
[0033]
Alternatively, in the first to third semiconductor device manufacturing methods, it is preferable to generate a water vapor atmosphere in a reduced pressure outside the chamber for oxidation treatment.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.
[0035]
FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2D show cross-sectional structures in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention. ing.
[0036]
First, as shown in FIG. 1A, an element isolation region 12 made of shallow trench isolation (STI) or the like in which silicon oxide is buried is selectively formed on a semiconductor substrate 11 made of silicon, and the formed element. An element active region 11a partitioned by the isolation region 12 is formed. Here, the semiconductor substrate 11 represents a part of the wafer.
[0037]
Next, as shown in FIG. 1B, the film thickness is about 300 nm and the impurity concentration is about 1 × 10 6 on the semiconductor substrate 11 by, for example, chemical vapor deposition (CVD). ¹⁹ cm ^-3 The lower electrode forming film for the capacitor element made of the n-type polycrystalline silicon is deposited. The introduction of impurities into the lower electrode formation film is, for example, about 1 × 10 6 during film formation. ¹⁹ cm ^-3 ~ 1x10 ^{twenty one} cm ^-3 After doping of phosphorus (P) ions or depositing non-doped polycrystalline silicon, the dose is about 1 × 10 ¹⁵ cm ^-2 ~ 1x10 ¹⁶ cm ^-2 Of phosphorus (P) ions. Thereafter, patterning is performed so as to leave the upper portion of the element isolation region 12 in the deposited lower electrode formation film, and the lower electrode 13 of the capacitive element is formed at a predetermined position on the element isolation region 12 from the lower electrode formation film.
[0038]
Next, as shown in FIG. 1C, for example, p-type impurity ions for determining the threshold voltage of the MOS transistor are added to the element active region 11a at an impurity concentration of about 1 × 10. ¹⁷ cm ^-3 Then, the entire surface of the semiconductor substrate 11 including the lower electrode 13 is subjected to thermal oxidation in a reduced-pressure water vapor atmosphere to thereby form an oxide film (on the surface of the lower electrode 13 and the surface of the element active region 11a). Sacrificial oxide films) 14A and 14B are formed. At this time, the difference between the thickness of the oxide film 14A on the lower electrode 13 and the thickness of the oxide film 14B on the device active region 11a is larger than the impurity concentration of the lower electrode 13 in the device active region 11a. Nevertheless, it will be 5% or less as will be described later. By the formation process of the oxide films 14A and 14B, the implantation damage in the element active region 11a is recovered. When impurity ions are introduced into the lower electrode 13 by implantation, the implantation damage to the lower electrode 13 is also recovered at the same time.
[0039]
Here, the steam atmosphere is generated by a so-called internal combustion system pyrogenic oxidation (ISSG) method. Specifically, in a chamber having a temperature of about 850 ° C. to about 1100 ° C. and a pressure of about 8 mTorr (1 Torr = 133.322 Pa), hydrogen (H ₂ ) And oxygen (O ₂ ) At a flow rate of about 10 L / m (provided that the standard state is 0 ° C. and 1 atm), and the introduced hydrogen and oxygen are reacted on the heated semiconductor substrate 11 to generate water vapor.
[0040]
Next, as shown in FIG. 1D, the oxide films 14A and 14B are removed by wet etching using hydrofluoric acid or the like. Thus, by removing the oxide films 14A and 14B, carbon particles and the like contained in the resist film and the like remaining on the respective surfaces of the lower electrode 13 and the element active region 11a are taken into the oxide film and removed. Therefore, contamination is prevented.
[0041]
In addition, as a feature of the first embodiment, the oxide film 14A on the lower electrode 13 and the oxide film 14B on the element active region 11a are almost equal in thickness, so that the element isolation region 12 is excessively etched. Therefore, it is possible to prevent the exposed portion of the insulating film embedded in the element isolation region 12 from being reduced.
[0042]
Next, as shown in FIG. 2A, a capacitive insulating film forming film 15A made of silicon oxide is formed on the surface of the lower electrode 13 by an ISSG oxidation method using a reduced-pressure steam atmosphere under the same conditions as described above. A gate insulating film forming film 15B made of silicon oxide is also formed on the surface of the element active region 11a. Also at this time, the difference in film thickness between the capacitor insulating film forming film 15A and the gate insulating film forming film 15B is 5% or less.
[0043]
Next, as shown in FIG. 2B, an n-type multi-layer having a film thickness of about 200 nm over the entire surface including the capacitor insulating film forming film 15A and the gate insulating film forming film 15B on the semiconductor substrate 11 by CVD or the like. An electrode forming film 16 made of crystalline silicon is deposited.
[0044]
Next, as shown in FIG. 2C, by selectively etching the upper part of the lower electrode 13 in the deposited electrode forming film 16 and the capacitor insulating film forming film 15A, the electrode forming film 16 is removed. The upper electrode 16a is formed, and the capacitive insulating film 15a is formed from the capacitive insulating film forming film 15A. As a result, the capacitive element 17 including the lower electrode 13, the capacitive insulating film 15a, and the upper electrode 16a is formed. At the same time, by selectively etching the upper portion of the element active region 11a in the electrode forming film 16 and the gate oxide film forming film 15B, the gate electrode 16b is formed from the electrode forming film 16, and the gate oxidation is performed. Gate oxide film 15b is formed from film forming film 15B.
[0045]
Next, as shown in FIG. 2D, with the gate electrode 16b as a mask in the element active region 11a, the implantation energy is about 30 keV and the dose amount is about 3 × 10. ¹⁵ cm ^-2 The n-type source / drain diffusion layer 18 is formed in the element active region 11a by ion implantation of arsenic (As) ions.
[0046]
Here, the difference between the oxide film formed by the oxidation process of the present embodiment and the film thickness of the oxide film formed by the conventional oxidation process will be described.
[0047]
FIG. 3 shows a temperature of about 900 ° C. and a dose of about 1 × 10 ¹⁴ cm ^-2 An oxidizing atmosphere having a value of a ratio between the thickness of the silicon oxide film formed on the impurity diffusion layer made of silicon formed by implanting arsenic and the thickness of the silicon oxide film formed on the bare wafer made of silicon Shows dependency.
[0048]
As can be seen from FIG. 3, the oxidation method in the water vapor atmosphere under reduced pressure according to the present invention reduces the film thickness of the silicon oxide film by about 20% compared to the conventional oxidation method in the water vapor atmosphere under normal pressure. is doing. This is because silicon is oxidized in a water vapor atmosphere under reduced pressure, thereby allowing radical oxidation and suppressing accelerated oxidation by impurity ions.
[0049]
As described above, according to the first embodiment, in the process shown in FIG. ¹⁹ cm ^-3 Since the oxide film 14A on the surface of the lower electrode 13 highly doped as described above is formed in a water vapor atmosphere in a reduced pressure state, the thickness of the oxide film 14A is almost different from the thickness of the oxide film 14B on the element active region 11a. Absent. For this reason, in the step of removing the oxide films 14A and 14B shown in FIG. 1D, it is possible to prevent the insulating film embedded in the element isolation region 12 where the lower electrode 13 is formed from being reduced, and thus the gate insulating film 15b. It is possible to suppress deterioration in reliability at the end of the element isolation region 12 and increase in variation in transistor characteristics.
[0050]
Further, since the capacitor insulating film forming film 15A and the gate insulating film forming film 15B shown in FIG. 2A are formed in a water vapor atmosphere in a reduced pressure state, the capacitance on the surface of the highly doped lower electrode 13 is increased. The insulating film forming film 15A has almost the same thickness as the gate insulating film forming film 15B because the accelerated oxidation phenomenon is suppressed. Accordingly, since the thickness of the capacitive insulating film 15a can be reduced to approximately the same as that of the gate insulating film 15b, the element size of the capacitive element 17 can be reduced.
[0051]
In the first embodiment, after the lower electrode 13 is formed, ion implantation for threshold adjustment is performed on the element active region 11a. On the contrary, the lower electrode 13 is formed. Prior to this, ion implantation may be performed on the element active region 11a.
[0052]
(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0053]
4 (a) to 4 (d) and FIGS. 5 (a) to 5 (d) show cross-sectional structures in order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention. ing.
[0054]
First, as shown in FIG. 4A, an element isolation region 12 made of STI or the like in which silicon oxide is embedded is selectively formed on a semiconductor substrate 11 made of silicon, and is partitioned by the formed element isolation region 12. An element active region 11a and a capacitor element formation region 11b to be formed are formed. Here, the semiconductor substrate 11 represents a part of the wafer.
[0055]
Next, as shown in FIG. 4B, a resist pattern 20 that opens the capacitor element formation region 11b is formed on the semiconductor substrate 11 by lithography. Subsequently, using the resist pattern 20 as a mask, for example, the dose amount is about 1 × 10 6 in the capacitive element formation region 11b. ¹⁵ cm ^-2 ~ 1x10 ¹⁶ cm ^-2 Of phosphorus (P) ions, arsenic (As) ions, or boron (B) ions, and the impurity concentration in the capacitor element formation region 11b is about 1 × 10 5. ¹⁹ cm ^-3 The lower electrode layer 21 as described above is formed.
[0056]
Next, as shown in FIG. 4 (c), for example, p-type impurity ions for determining the threshold voltage of the MOS transistor are introduced into the element active region 11a at an impurity concentration of about 1 × 10. ¹⁷ cm ^-3 After the ion implantation is performed, the entire surface of the semiconductor substrate 11 is subjected to thermal oxidation in a reduced-pressure water vapor atmosphere to thereby form an oxide film (sacrificial oxide film) on the surface of the lower electrode layer 21 and the surface of the element active region 11a. 14A and 14B are formed. At this time, the difference between the thickness of the oxide film 14A on the lower electrode layer 21 whose impurity concentration is higher than that of the element active region 11a and the thickness of the oxide film 14B on the element active region 11a is 5% or less. By the formation process of the oxide films 14A and 14B, the implantation damage of the lower electrode layer 21 and the element active region 11a is recovered.
[0057]
In the second embodiment as well, the water vapor atmosphere is generated by the ISSG oxidation method that suppresses accelerated oxidation due to high-concentration impurities, and the conditions for water vapor generation are a temperature of about 850 ° C. to about 1100 ° C., a pressure Is about 8 mTorr in a chamber with a flow ratio of 9: 1 hydrogen (H ₂ ) And oxygen (O ₂ ) Is a flow rate of about 10 L / m (however, a standard state of 0 ° C. and 1 atm).
[0058]
Next, as shown in FIG. 4D, the oxide films 14A and 14B are removed by wet etching using hydrofluoric acid or the like. In this way, by removing the oxide films 14A and 14B, carbon particles and the like contained in the resist film and the like remaining on the surfaces of the lower electrode layer 21 and the element active region 11a are taken into the oxide film and removed. Therefore, contamination is prevented.
[0059]
Further, as a feature of the second embodiment, since the film thicknesses of the oxide film 14A on the lower electrode layer 21 and the oxide film 14B on the element active region 11a are almost equal, the element isolation region 12 is etched excessively. Therefore, it is possible to prevent the exposed portion of the insulating film embedded in the element isolation region 12 from being reduced.
[0060]
Next, as shown in FIG. 5A, a capacitive insulating film forming film 15A made of silicon oxide is formed on the surface of the lower electrode layer 21 by an ISSG oxidation method in a reduced-pressure water vapor atmosphere under the same conditions as described above. At the same time, a gate insulating film forming film 15B made of silicon oxide is also formed on the surface of the element active region 11a. Also at this time, the difference in film thickness between the capacitor insulating film forming film 15A and the gate insulating film forming film 15B is 5% or less.
[0061]
Next, as shown in FIG. 5B, an n-type multi-layer having a thickness of about 200 nm over the entire surface including the capacitor insulating film forming film 15A and the gate insulating film forming film 15B on the semiconductor substrate 11 is formed by CVD or the like. An electrode forming film 16 made of crystalline silicon is deposited.
[0062]
Next, as shown in FIG. 5C, the electrode forming film 16 is selectively etched by etching the upper part of the lower electrode layer 21 in the deposited electrode forming film 16 and the capacitive insulating film forming film 15A. Then, the upper electrode 16a is formed, and the capacitor insulating film 15a is formed from the capacitor insulating film forming film 15A. As a result, the capacitive element 17 including the lower electrode layer 21, the capacitive insulating film 15a, and the upper electrode 16a is formed. At the same time, by selectively etching the upper portion of the element active region 11a in the electrode forming film 16 and the gate oxide film forming film 15B, the gate electrode 16b is formed from the electrode forming film 16, and the gate oxidation is performed. Gate oxide film 15b is formed from film forming film 15B.
[0063]
Next, as shown in FIG. 5D, with the gate electrode 16b as a mask in the element active region 11a, the implantation energy is about 30 keV and the dose is about 3 × 10. ¹⁵ cm ^-2 The n-type source / drain diffusion layer 18 is formed in the element active region 11a by ion implantation of arsenic (As) ions.
[0064]
As described above, according to the second embodiment, impurities are about 1 × 10 5 in the step shown in FIG. ¹⁹ cm ^-3 Since the oxide film 14A on the surface of the lower electrode layer 21 highly doped as described above is formed in a water vapor atmosphere under reduced pressure, the film thickness is almost the same as the film thickness of the oxide film 14B on the element active region 11a. . For this reason, in the step of removing the oxide films 14A and 14B shown in FIG. 4D, it is possible to prevent the insulating film embedded in the element isolation region 12 from being reduced, so that the end of the element isolation region 12 in the gate insulating film 15b can be prevented. It is possible to suppress deterioration in reliability and increase in variation in transistor characteristics.
[0065]
Furthermore, since the capacitor insulating film forming film 15A and the gate insulating film forming film 15B shown in FIG. 5A are formed in a water vapor atmosphere in a reduced pressure state, they are formed on the surface of the highly doped lower electrode layer 21. The capacitive insulating film forming film 15A has almost the same thickness as the gate insulating film forming film 15B because the accelerated oxidation phenomenon is suppressed. Accordingly, since the thickness of the capacitor insulating film 15a can be reduced to almost the same as that of the gate insulating film 15b, the element size of the capacitor 17 can be reduced.
[0066]
In the second embodiment, since the lower electrode layer 21 of the capacitive element 17 is formed of an impurity diffusion layer, the manufacturing process is simplified in addition to the effects of the nonvolatile semiconductor memory device according to the first embodiment. It is also possible to obtain the effect of
[0067]
In the second embodiment, after the lower electrode layer 21 is formed, ion implantation is performed on the element active region 11a. On the contrary, before the lower electrode layer 21 is formed, the ion implantation is performed. Ion implantation may be performed on the element active region 11a.
[0068]
In the first or second embodiment, the ISSG oxidation method is used as the generation method for generating the water vapor in the reduced pressure state. May be.
[0069]
Moreover, although the silicon wafer was used for the semiconductor substrate 11, it is not restricted to this, You may use the SOI substrate which has the semiconductor area | region which consists of silicon | silicone in the upper part.
[0070]
【The invention's effect】
According to the first method for manufacturing a semiconductor device of the present invention, even when the capacitive insulating film is formed on the impurity region having a higher concentration than the gate insulating film, only the capacitive insulating film is the gate insulating film. Therefore, the thickness of the capacitor insulating film can be reduced.
[0071]
According to the second or third method for manufacturing a semiconductor device of the present invention, only the oxide film on the lower electrode film or the lower electrode layer is not thicker than the oxide film on the element active region. Therefore, thereafter, when the oxide film on the lower electrode film is removed, it is possible to prevent the film from being reduced around the lower electrode film in the element isolation region.
[Brief description of the drawings]
FIGS. 1A to 1D are process cross-sectional views illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
FIGS. 2A to 2D are process cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
FIG. 3 is a graph showing the dependence of the ratio of the thickness of a silicon oxide film formed on an impurity diffusion layer and the thickness of a silicon oxide film formed on a bare wafer made of silicon on the oxidation atmosphere. .
FIGS. 4A to 4D are process cross-sectional views illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.
FIGS. 5A to 5D are process cross-sectional views illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.
FIGS. 6A to 6D are cross-sectional structural views in the order of steps showing a conventional method for manufacturing a semiconductor device. FIGS.
FIGS. 7A to 7D are cross-sectional structural views in order of steps showing a conventional method for manufacturing a semiconductor device. FIGS.
[Explanation of symbols]
11 Semiconductor substrate
11a Device active region
11b Capacitor element formation region
12 Device isolation region
13 Lower electrode (lower electrode film)
14A oxide film
14B oxide film
15A capacitive insulating film forming film
15B Gate insulating film forming film
16 Electrode forming film
16a Upper electrode
16b Gate electrode
17 Capacitance element
18 Source-drain diffusion layer
20 resist pattern
21 Lower electrode layer

Claims (7)

A semiconductor device manufacturing method for forming a MOS type semiconductor element having a gate insulating film and a capacitive element having a capacitive insulating film on one semiconductor substrate,
Forming an element isolation region in the semiconductor substrate (a) ;
Forming a lower electrode film made of silicon having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ or more on the element isolation region (b);
Forming the gate insulating film on the semiconductor substrate and forming the capacitive insulating film on the lower electrode film (c),
In the step (c), in a water vapor atmosphere at a reduced pressure state, the gate insulating layer above to form the capacitor insulating film and at the same time as, the capacitor insulating film semi-conductor device you characterized by inhibiting the enhanced oxidation of Manufacturing method. A semiconductor device manufacturing method for forming a MOS type semiconductor element having a gate insulating film and a capacitive element having a capacitive insulating film on one semiconductor substrate,
The semiconductor substrate is made of silicon,
(A) forming an element active region in the semiconductor substrate,
(B) forming a lower electrode layer in the device active region by injecting impurities into the device active region so that the concentration thereof is about 1 × 10 ¹⁹ cm ⁻³ or more ;
Forming the gate insulating film on the semiconductor substrate and forming the capacitive insulating film on the lower electrode layer (c),
In the step (c), in a water vapor atmosphere at a reduced pressure state, the gate insulating layer above to form the capacitor insulating film and at the same time as, the capacitor insulating film semi-conductor device you characterized by inhibiting the enhanced oxidation of Manufacturing method. After the step of forming the gate insulating film and the capacitor insulating film,
3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a gate electrode on the gate insulating film and forming an upper electrode on the capacitive insulating film. . A semiconductor device manufacturing method for forming a MOS type semiconductor element having a gate insulating film and a capacitive element having a capacitive insulating film on one semiconductor substrate,
Selectively forming an element isolation region in the semiconductor substrate and forming an element active region partitioned by the formed element isolation region;
Forming a lower electrode film made of silicon having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ or more on the element isolation region;
Forming an oxide film on the surface of the lower electrode film and the semiconductor substrate by oxidizing the surface of the semiconductor substrate including the lower electrode film in a reduced-pressure water vapor atmosphere;
Forming the gate insulating film on the device active region after removing the oxide film by etching, and forming the capacitive insulating film on the lower electrode film;
Forming a gate electrode on the gate insulating film and forming an upper electrode on the capacitive insulating film. A semiconductor device manufacturing method for forming a MOS type semiconductor element having a gate insulating film and a capacitive element having a capacitive insulating film on one semiconductor substrate,
Selectively forming an element isolation region on the semiconductor substrate, and forming a capacitor element formation region and an element active region partitioned by the formed element isolation region;
A step of forming a lower electrode layer by injecting impurities into the capacitor element formation region so that the concentration thereof is about 1 × 10 ¹⁹ cm ⁻³ or more;
Forming an oxide film on the surfaces of the lower electrode layer and the element active region by oxidizing the surface of the semiconductor substrate in a reduced-pressure water vapor atmosphere;
Forming the gate insulating film on the device active region after removing the oxide film by etching, and forming the capacitive insulating film on the lower electrode layer;
Forming a gate electrode on the gate insulating film and forming an upper electrode on the capacitive insulating film. The reduced-pressure steam atmosphere is generated by introducing hydrogen and oxygen into an oxidation treatment chamber and reacting the introduced hydrogen and oxygen on the heated semiconductor substrate. Item 6. The method for manufacturing a semiconductor device according to any one of Items 1 to 5 . The water vapor atmosphere of a reduced pressure state, the method of manufacturing a semiconductor device according to any one of claims 1-5, characterized in that the generated outside the chamber for oxidation.

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