JP4043872B2 - Multilayer wiring board manufacturing method and resin-encapsulated semiconductor device manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a resin-encapsulated semiconductor device, a multilayer wiring board used therefor, and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, semiconductor devices have been increasingly integrated and improved in performance, as represented by LSI ASICs, due to the trend toward higher performance, smaller size, and thinner electronic devices. In the manufacture of a conventional semiconductor device, a semiconductor element is mounted on each multilayer wiring board, and wire bonding, resin sealing, and the like are performed to assemble the semiconductor device.
A multilayer wiring board used for manufacturing a conventional resin-encapsulated semiconductor device has an internal terminal wiring on one surface of a core substrate, an external terminal wiring on the other surface, and through holes formed in the core substrate. In this way, the internal terminal wiring and the external terminal wiring are electrically connected.
[0003]
[Problems to be solved by the invention]
However, such a multilayer wiring board has a limit in reducing the thickness due to the presence of the core substrate, which hinders the reduction in thickness of the semiconductor device. In addition, the production of the multilayer wiring board requires a plurality of steps such as a through hole forming step and a conduction step for the core substrate, and the operation is extremely complicated.
The present invention has been made in view of the above situation, a multilayer wiring board capable of manufacturing a small and thin resin-encapsulated semiconductor device with high accuracy and high efficiency, and a method for manufacturing the same, and It is an object of the present invention to provide a method for manufacturing a small and thin resin-encapsulated semiconductor device.
[0004]
[Means for Solving the Problems]
  In order to achieve such an object, a manufacturing method of a multilayer wiring board according to the present invention includes a step of forming a metal conductive layer on one surface of a base substrate, and the electric conduction layer on the metal conductive layer via an electric insulating layer. A step of forming a plurality of internal terminal wirings in an arrangement corresponding to a mounting position of a semiconductor element by providing one or more wirings in which a necessary conduction is taken in a via portion formed in an insulating layer; and the base substrate And exposing the metal conductive layer, and pattern etching the metal conductive layer to form a plurality of external terminal wirings corresponding to the internal terminal wirings. .
[0005]
As a preferred aspect of the present invention, a configuration in which a concave portion is formed in advance on one surface of the base substrate so as to correspond to the external terminal of the external terminal wiring, and a metal conductive layer is formed on the surface on which the concave portion is formed. did.
As a preferred aspect of the present invention, the base substrate is configured such that the thermal expansion coefficient in the XY direction is in the range of 2 to 20 ppm.
As a preferred aspect of the present invention, the base substrate is configured to be any one of silicon, glass, and 42 alloy.
As a preferred embodiment of the present invention, the metal conductive layer is configured to be copper.
[0006]
  The manufacturing method of the resin-encapsulated semiconductor device of the present invention is as follows.A step of forming a metal conductive layer on one surface of the base substrate, and one or more layers of wiring on which the necessary electrical conduction is achieved on the metal conductive layer through the electrical insulating layer through the electrical insulating layer Forming a plurality of internal terminal wirings in an arrangement corresponding to the mounting position of the semiconductor element, removing the base substrate and exposing the metal conductive layer, and pattern etching the metal conductive layer Forming a plurality of external terminal wirings corresponding to each internal terminal wiring to form a multilayer wiring board; andA step of mounting a semiconductor element on the internal terminal wiring of the multilayer wiring board, a step of resin-sealing the semiconductor element, and cutting and separating the multilayer wiring board and the sealing resin to obtain individual resin-encapsulated semiconductor devices And having a process.
  The method for manufacturing a resin-encapsulated semiconductor device according to the present invention includes a step of forming a metal conductive layer on one surface of a base substrate, and an electric insulating layer formed on the metal conductive layer via the electric insulating layer. Forming a plurality of internal terminal wirings in an arrangement corresponding to the mounting position of the semiconductor element by providing one or more layers of wiring that have the necessary conduction in the via portion, and a semiconductor element on each internal terminal wiring And then, sealing the semiconductor element with resin, removing the base substrate and exposing the metal conductive layer, and pattern etching the metal conductive layer to correspond to each internal terminal wiring In this way, the configuration includes a step of forming a plurality of external terminal wirings and a step of cutting and separating the electrical insulating layer and the sealing resin to obtain individual resin-encapsulated semiconductor devices.
[0007]
As a preferred aspect of the present invention, a configuration in which a concave portion is formed in advance on one surface of the base substrate so as to correspond to the external terminal of the external terminal wiring, and a metal conductive layer is formed on the surface on which the concave portion is formed. did.
As a preferred aspect of the present invention, the base substrate is configured such that the thermal expansion coefficient in the XY direction is in the range of 2 to 20 ppm.
As a preferred aspect of the present invention, the base substrate is configured to be any one of silicon, glass, and 42 alloy.
As a preferred embodiment of the present invention, the metal conductive layer is configured to be copper.
In the present invention as described above, there is no core substrate in the multilayer wiring board and the thickness is thin, and in the manufacturing process of the multilayer wiring board and the manufacturing process of the resin-encapsulated semiconductor device, the formation of the through hole , The conduction step is unnecessary.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Multilayer wiring board
FIG. 1 is a partial longitudinal sectional view showing an embodiment of a multilayer wiring board according to the present invention. In FIG. 1, a multilayer wiring board 1 according to the present invention includes a plurality of internal terminal wirings 2 formed in a planar shape in an arrangement corresponding to a mounting position of a semiconductor element, and a plurality of external terminal wirings corresponding to each internal terminal wiring 2. And 5.
[0009]
The plurality of internal terminal wirings 2 constituting the multilayer wiring board 1 are multilayer wirings in the illustrated example, and predetermined external terminal wirings 5 are formed on the external terminal wirings 5 via the first electrical insulating layer 3a and via portions 4a. The first-layer wiring 2a formed so as to be electrically connected to the first-layer wiring 2a and the predetermined first-layer wiring 2a through the second-layer electric insulating layer 3b on the first-layer wiring 2a. The second-layer wiring 2b formed as described above is electrically connected to the predetermined second-layer wiring 2b at the via portion 4c via the third-layer electrical insulating layer 3c on the second-layer wiring 2b. And the third-layer wiring 2c formed as described above. An internal terminal (not shown) for mounting a semiconductor element is set on the third-layer wiring 2c. A plurality of such internal terminal wirings 2 are formed in a plane (along a plane parallel to each wiring layer constituting the internal terminal wiring) in an arrangement corresponding to the mounting position of the semiconductor element. Two sets of 2A and 2B are shown.
[0010]
The plurality of external terminal wirings 5 constituting the multilayer wiring board 1 are formed to be electrically connected to predetermined internal terminal wirings 2 (2a) through the via portions 4a through the electrical insulating layer 3a. The external terminal wiring 5 is set with an external terminal (not shown) for mounting on a printed wiring board after being assembled in a semiconductor device. A plurality of such external terminal wirings 5 are formed so as to correspond to the respective internal terminal wirings 2. In the illustrated example, two sets of 5A and 5B are shown. In the present invention, solder balls may be provided on the external terminals of the external terminal wiring 5. Further, as shown in FIG. 2, a convex external terminal 5 a may be integrally provided on the external terminal wiring 5.
[0011]
The material of the first layer wiring 2a, the second layer wiring 2b, the third layer wiring 2c, and the material of the via portions 4a, 4b, 4c constituting the internal terminal wiring 2 are copper, silver, gold Further, a conductive material such as chromium or nickel can be used. The thicknesses of the wirings 2a, 2b, 2c can be appropriately set within a range of 0.5 to 10 μm, for example. The diameter of the via portions 4a, 4b, 4c is 100 μm or less, preferably 10 to 50 μm, and the minimum formation pitch of the via portions 4a, 4b, 4c in each layer is 200 μm or less, preferably 50 to 180 μm. And If the diameter of the via portion exceeds 100 μm or the minimum formation pitch exceeds 200 μm, the effect of downsizing the semiconductor device cannot be sufficiently obtained.
[0012]
The material of the electrical insulating layers 3a, 3b, 3c is an insulating material such as an organic insulating material such as epoxy resin, benzocyclobutene resin, cardo resin, polyimide resin, or a combination of these organic materials and glass fiber. It can be. In particular, for example, when the second-layer wiring 2b is a ground and the first-layer wiring 2a and the third-layer wiring 2c are signal lines, the second-layer electrical insulation layer 3b and the third-layer electrical insulation are used. The material of the layer 3c is preferably an insulating material having a low dielectric constant and dielectric loss tangent, such as benzocyclobutene resin, cardo resin, and polyimide resin. The thickness of the electrical insulating layers 3a, 3b, 3c can be appropriately set within a range of 1 to 20 μm, for example.
The external terminal wiring 5 can be formed using a conductive material such as copper, nickel, or gold.
Such a multilayer wiring board 1 has a thickness in the range of 30 to 150 μm, preferably 30 to 100 μm. If the thickness of the multilayer wiring board 1 is less than 30 μm, the mechanical strength is insufficient, and if it exceeds 150 μm, the effect of thinning the semiconductor device cannot be obtained sufficiently.
[0013]
The multilayer wiring board 1 of the present invention as described above has a small thickness because there is no core substrate having a through hole. In addition, in the conventional multilayer wiring board, the wiring layer is formed on both surfaces of the core board to prevent warpage, and the balance maintenance function is achieved. However, in the present invention, the core board does not exist, so the wiring formation is limited. Even if not, the occurrence of warpage is prevented. Further, the formation density of the via portion can be increased, and the semiconductor device can be further reduced in thickness and size as compared with the conventional multilayer wiring board.
The multilayer wiring board of the present invention is not limited to the one shown in the above-described embodiment, and the layer structure of the internal terminal wiring can be two layers or four or more layers.
[0014]
Manufacturing method of multilayer wiring board
Next, the manufacturing method of the multilayer wiring board of this invention is demonstrated, referring drawings.
3 and 4 are process diagrams showing an embodiment of a manufacturing method using the multilayer wiring board 1 of the present invention shown in FIG. 1 as an example.
In the method for manufacturing a multilayer wiring board according to the present invention, first, a metal conductive layer 15 is formed on one surface 11a of the base substrate 11 (FIG. 3A). The base substrate 11 is a material having a thermal expansion coefficient in the XY direction (a plane parallel to the surface 11a of the base substrate 11) in the range of 2 to 20 ppm, preferably 2.5 to 17 ppm, for example, silicon, glass, 42 alloy. (Iron-nickel alloy) or the like can be used. The thickness of the base substrate 11 can be appropriately set within a range of about 100 to 1000 μm, for example. In addition, the metal conductive layer 15 is patterned in a process to be described later to become an external terminal wiring, and can be made of a material such as copper, nickel, or chromium. The metal conductive layer 15 can be formed by plating, or can be formed as a laminated film of sputtering and plating, and the thickness can be appropriately set within a range of about 0.1 to 50 μm, for example. it can.
[0015]
Next, a plurality of internal terminal wirings 2 are formed on the metal conductive layer 15 in an arrangement corresponding to the mounting position of the semiconductor element (FIG. 3B). In the illustrated example, two sets of internal terminal wirings 2A and 2B are shown. The internal terminal wiring 2 is formed by, for example, forming an electrical insulating layer 3a on the metal conductive layer 15, and using a carbon dioxide laser, UV-YAG laser, or the like so that a desired portion of the metal conductive layer 15 is exposed. Are formed at predetermined positions on the electrical insulating layer 3a. After cleaning, a conductive layer is formed by electroless plating in the hole and on the electrical insulating layer 3a. A dry film resist is laminated on the conductive layer, and a resist pattern is formed by performing desired pattern exposure and development. To do. Thereafter, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating on the exposed part including the hole part to form the via part 4a and the first layer wiring 2a, and the resist pattern and the conductive layer are removed. This operation is repeated to form a plurality of buildup layers. In the illustrated example, the second-layer wiring 2b is formed on the first-layer wiring 2a so as to be connected to the predetermined first-layer wiring 2a through the second-layer electrical insulating layer 3b at the via portion 4b. Then, the third-layer wiring 2c is formed on the second-layer wiring 2b so as to be connected to the predetermined second-layer wiring 2b through the third-layer electrical insulating layer 3c via the via portion 4c. The wiring has a three-layer structure.
[0016]
Next, the base substrate 11 is removed, and the metal conductive layer 15 is exposed (FIG. 4A). The removal of the base substrate 11 can be performed by polishing using a grinding apparatus. Next, the metal conductive layer 15 is pattern-etched to form a plurality of external terminal wirings 5 so as to correspond to the respective internal terminal wirings 2 to obtain the multilayer wiring board 1 (FIG. 4B). In the illustrated example, two sets of external terminal wirings 5A and 5B are shown so as to correspond to two sets of internal terminal wirings 2A and 2B. Pattern etching of the metal conductive layer 15 can be performed by a known method.
In the manufacturing method of the multilayer wiring board of the present invention as described above, the metal conductive layer 15 is used, and the metal conductive layer 15 is patterned after the base substrate 11 is removed to form the external terminal wiring 5. The internal terminal wiring 2 is electrically connected in the process of forming the internal terminal wiring 2 on the metal conductive layer 15. For this reason, each process of formation of the through hole and conduction in the through hole which are necessary in the conventional manufacturing method of the multilayer wiring board is unnecessary, and the process becomes simple.
[0017]
When the convex external terminal 5a is integrally provided on the external terminal wiring 5 as described above (see FIG. 2), as shown in FIG. 5, the concave portion 12 corresponds to the external terminal of the external terminal wiring. Is formed in advance on one surface 11a of the base substrate 11, and the metal conductive layer 15 is formed on this surface. Thereby, as shown by the chain line in FIG. 4B, the external terminal wiring 5 integrally including the convex external terminal 5a can be formed. Formation of the recess 12 in the base substrate 11 can be performed by wet etching, sandblasting, or the like. The size of the recess 12 to be formed can be, for example, an opening diameter of 20 to 500 μm and a depth of about 10 to 250 μm. .
The method for manufacturing a multilayer wiring board according to the present invention is not limited to the one shown in the above-described embodiment, and even when a multilayer wiring board having two or more layers of internal terminal wiring is manufactured. Can be applied.
[0018]
Manufacturing method of resin-encapsulated semiconductor device
Next, a method for manufacturing a resin-encapsulated semiconductor device of the present invention will be described with reference to the drawings.
FIG. 6 is a process diagram showing an embodiment of a method for manufacturing a resin-encapsulated semiconductor device taking as an example the case where the multilayer wiring board 1 of the present invention shown in FIG. 1 is used.
In the method for manufacturing a resin-encapsulated semiconductor device of the present invention, first, a semiconductor element 22 is mounted on each internal terminal wiring 2 of the multilayer wiring board 1 (FIG. 6A). The semiconductor element 22 can be mounted on the internal terminals of the internal terminal wiring 2 through metal bumps 23 such as solder. In the illustrated example, the semiconductor element 22 is mounted on each of the two sets of internal terminal wirings 2A and 2B.
[0019]
Next, the mounted semiconductor element 22 is covered with a sealing member 24 and sealed (FIG. 6B). As the sealing member 24, a conventionally known sealing member can be used, and examples thereof include a sealing agent in which silica powder is dispersed in an epoxy resin.
Next, dicing is performed to cut the multilayer wiring board 1 and the sealing member 24 for each semiconductor element 22 at a predetermined position, thereby obtaining individual semiconductor devices 21 (FIG. 6C).
In the method for manufacturing a resin-encapsulated semiconductor device of the present invention as described above, each step of forming a through-hole and conducting in a through-hole is unnecessary, so that the process is simple and the obtained resin encapsulation The type semiconductor device can be thinned because there is no core substrate. Moreover, since the mounting from the semiconductor element to the resin sealing is simultaneously performed on multiple surfaces on the multilayer wiring board, a highly accurate resin-encapsulated semiconductor device can be manufactured.
[0020]
7 and 8 are process diagrams showing another embodiment of the method for manufacturing a resin-encapsulated semiconductor device of the present invention.
In the method for manufacturing a resin-encapsulated semiconductor device of the present invention, first, a metal conductive layer 15 ′ is formed on one surface 31a of the base substrate 31 (FIG. 7A). The base substrate 31 is made of a material having a thermal expansion coefficient in the XY direction (a plane parallel to the surface 31a of the base substrate 31) in the range of 2 to 20 ppm, preferably 2.5 to 17 ppm, for example, silicon, glass, 42 alloy. (Iron-nickel alloy) or the like can be used. The thickness of the base substrate 31 can be appropriately set within a range of about 100 to 1000 μm, for example. The metal conductive layer 35 ′ is patterned in a process described later to become an external terminal wiring, and can be made of a material such as copper or nickel. The metal conductive layer 35 ′ can be formed by plating, or can be formed as a laminated film of sputtering and plating. The thickness of the metal conductive layer 35 ′ is appropriately within a range of about 0.1 to 50 μm, for example. Can be set.
[0021]
Next, a plurality of internal terminal wirings 32 are formed on the metal conductive layer 35 'in an arrangement corresponding to the mounting position of the semiconductor element (FIG. 7B). In the illustrated example, two sets of internal terminal wirings 32A and 32B are shown. The internal terminal wiring 32 is formed, for example, by forming an electrical insulating layer 33a on the metal conductive layer 35 'and exposing a desired portion of the metal conductive layer 35' using a carbon dioxide gas laser, a UV-YAG laser or the like. A small-diameter hole is formed at a predetermined position of the electrical insulating layer 33a. Then, after cleaning, a conductive layer is formed by electroless plating in the hole and on the electrical insulating layer 33a, and a dry film resist is laminated on the conductive layer to form a resist pattern by performing desired pattern exposure and development. To do. Thereafter, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating on the exposed portion including the hole portion to form the via portion 34a and the first wiring layer 32a, and the resist pattern and the conductive layer are removed. This operation is repeated to form a plurality of buildup layers. In the illustrated example, the second-layer wiring 32b is formed on the first-layer wiring 32a so as to be connected to the predetermined first-layer wiring 32a through the second-layer electrical insulating layer 33b via the via portion 34b. Then, a third-layer wiring 32c is formed on the second-layer wiring 32b so as to be connected to the predetermined second-layer wiring 32b through the third-layer electrical insulating layer 33c at the via portion 34c. The wiring has a three-layer structure.
[0022]
Next, the semiconductor element 42 is mounted on each internal terminal wiring 32 formed as described above (FIG. 7C). The semiconductor element 42 can be mounted on the internal terminals of the internal terminal wiring 32 via metal bumps 43 such as solder. In the illustrated example, the semiconductor element 42 is mounted on each of the two sets of internal terminal wirings 32A and 32B.
Next, the mounted semiconductor element 42 is covered with a sealing member 44 and sealed (FIG. 8A). As the sealing member 44, a conventionally known sealing member can be used, and examples thereof include a sealing agent in which silica powder is dispersed in an epoxy resin.
Next, the base substrate 31 is polished and removed to expose the metal conductive layer 35 '(FIG. 8B). The removal of the base substrate 31 can be performed by polishing using a grinding apparatus.
[0023]
Next, the metal conductive layer 35 'is pattern-etched to form a plurality of external terminal wirings 35 corresponding to the internal terminal wirings 32 (FIG. 8C). In the illustrated example, two sets of external terminal wirings 35A and 35B are formed so as to correspond to the two sets of internal terminal wirings 32A and 32B. Pattern etching of the metal conductive layer 35 'can be performed by a known method.
Next, dicing is performed to cut the electrical insulating layers 33a, 33b, 33c and the sealing member 44 at predetermined positions for each semiconductor element 42, whereby individual semiconductor devices can be obtained.
[0024]
In the method for manufacturing a resin-encapsulated semiconductor device of the present invention as described above, since the base substrate 31 is removed in a subsequent process, each process of forming a through hole and conducting in a through hole is unnecessary. In addition to being simple, the resin-encapsulated semiconductor device obtained can be thinned because there is no core substrate. Further, since the mounting from the semiconductor element to the resin sealing is performed on multiple surfaces simultaneously on the base substrate 31, a highly accurate resin-encapsulated semiconductor device can be manufactured.
The manufacturing method of the resin-encapsulated semiconductor device of the present invention is not limited to the one shown in the above embodiment, and the layer structure of the internal terminal wiring may be two layers or four layers or more. There is no limit to the number of semiconductor elements mounted on one semiconductor device.
[0025]
【Example】
Next, the present invention will be described in more detail with specific examples.
[Example 1]
As a base substrate, 42 alloys having a thickness of 300 μm were prepared, and a metal conductive layer having a thickness of 30 μm was formed on one surface of the base substrate by electrolytic copper plating. The 42 alloy used had a thermal expansion coefficient in the XY direction of 8 ppm.
Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied onto the metal conductive layer with a spin coater and dried to form an electrical insulating layer having a thickness of 10 μm.
[0026]
Next, exposure and development were performed to form small-diameter holes (inner diameter 30 μm) at predetermined positions on the electrical insulating layer in a range of 80 to 200 μm so that desired portions of the metal conductive layer were exposed. After cleaning, a conductive layer made of copper and chromium was formed by sputtering in the hole and on the electrical insulating layer, and a dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) was laminated on the conductive layer. Next, a resist pattern for wiring formation was formed by exposure and development through a photomask for wiring formation of the first layer. Using this resist pattern as a mask, electrolytic copper plating (thickness 5 μm) was performed, and then the resist pattern and the conductive layer were removed. As a result, a first-layer wiring was formed on the metal conductive layer via the electrical insulating layer. The diameter of the via part was 30 μm, and the minimum formation pitch of the via part was 80 μm.
Further, the same operation was performed to form a second-layer wiring on the first-layer wiring through the electrical insulating layer, and a third-layer wiring on the second-layer wiring through the electrical insulating layer.
As a result, a plurality of internal terminal wirings having a three-layer wiring structure were formed in an arrangement (20 mm × 20 mm grid arrangement) corresponding to the mounting position of the semiconductor element.
[0027]
Next, the 42 alloy as a base substrate was polished and removed by a grinding apparatus to expose the metal conductive layer as a copper layer. Next, a photosensitive resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the exposed metal conductive layer, and exposed and developed through a photomask for external terminal wiring to form a resist pattern. Using this resist pattern as a mask, the metal conductive layer was etched with copper chloride, and then the resist pattern was removed with acetone to form a plurality of external terminal wirings corresponding to each internal terminal wiring.
Thus, the multilayer wiring board of the present invention was obtained. The thickness of this multilayer wiring board was 30 μm, and the thickness was greatly reduced as compared with the thickness of a conventional multilayer wiring board having a core substrate (generally 300 to 1000 μm).
[0028]
Next, a resin-encapsulated semiconductor device was manufactured using the multilayer wiring board. That is, first, a semiconductor element (10 mm × 10 mm, thickness 0.2 mm) was mounted on the internal terminal of each internal terminal wiring of the multilayer wiring board via a solder bump.
Next, it sealed with the epoxy-type sealing agent so that the mounted semiconductor element might be coat | covered. The thickness of the sealing member was 0.3 mm. Next, dicing was performed to cut the multilayer wiring board and the sealing member at predetermined positions for each semiconductor element, thereby obtaining individual resin-encapsulated semiconductor devices.
The size of the resin-encapsulated semiconductor device thus manufactured was 20 mm × 20 mm and the thickness was 0.33 mm.
[0029]
[Example 2]
As a base substrate, 42 alloys having a thickness of 200 μm are prepared, a photosensitive resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied to one surface of the base substrate, and exposed and developed through a photomask of an external terminal. Thus, a resist pattern was formed. Using this resist pattern as a mask, the base substrate was etched with iron chloride to form a recess (for external terminal formation) having an opening diameter of 100 μm and a depth of 30 μm. The 42 alloy used had a thermal expansion coefficient in the XY direction of 8 ppm.
Next, a photosensitive resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the base substrate having the recesses, and a resist pattern was formed by exposure and development through a photomask for external terminal wiring. . Using this resist pattern as a mask, electrolytic nickel plating (thickness 1 μm), electrolytic gold plating (thickness 0.3 μm), electrolytic nickel plating (thickness 1 μm), and electrolytic copper plating (thickness 5 μm) were sequentially applied to form a metal conductive layer. Then, the recessed part was filled with the electrically conductive paste containing a copper particle.
[0030]
Next, in the same manner as in Example 1, the internal terminal wiring having a three-layer wiring structure is arranged on the metal conductive layer in the arrangement corresponding to the mounting position of the semiconductor element (10 mm × 10 mm grid arrangement). And it formed in multiple numbers by arrangement | positioning corresponding to the said recessed part for external terminal formation. Moreover, the diameter of the via part in this internal terminal wiring was 30 μm, and the minimum formation pitch of the via part was 90 μm.
Next, a semiconductor element (10 mm × 10 mm, thickness 0.2 mm) was mounted on the internal terminal of each internal terminal wiring formed on the metal conductive layer via a solder bump. Then, it sealed with the epoxy-type sealing agent so that the mounted semiconductor element might be coat | covered. The thickness of the sealing member was 0.3 mm.
[0031]
Next, the 42 alloy as the base substrate was removed by polishing with iron chloride to expose the metal conductive layer as the copper layer. On the surface of the metal conductive layer exposed in this manner, there was a convex portion (height 30 μm) corresponding to the concave portion for forming the external terminal, and an external terminal wiring was also formed at the same time.
Next, dicing was performed to cut the multilayer wiring board and the sealing member at predetermined positions for each semiconductor element, thereby obtaining individual resin-encapsulated semiconductor devices.
The size of the resin-encapsulated semiconductor device thus manufactured was 20 mm × 20 mm and the thickness was 0.33 mm.
[0032]
[Comparative example]
A double-sided wiring board based on a polyimide resin film having a thickness of 75 μm was prepared as a multilayer wiring board. A semiconductor element was mounted on the double-sided wiring board in the same manner as in the example, and resin-sealing and dicing were performed to obtain a resin-sealed semiconductor device.
However, in the production of the above resin-encapsulated semiconductor device, the workability of mounting the semiconductor element on the film wiring board is poor.
Moreover, the size of the manufactured semiconductor device was 40 mm × 40 mm and the thickness was 0.375 mm, and the thickness was about the same as the resin-encapsulated semiconductor device manufactured in the example. However, due to the low wiring density of the double-sided wiring board (L / S = 30 μm / 30 μm), the area of the resin-encapsulated semiconductor device is large.
[0033]
【The invention's effect】
As described above in detail, the multilayer wiring board of the present invention has a configuration in which a core substrate having a through hole does not exist. Unlike a conventional multilayer wiring board having a core substrate, warpage due to the number of wiring layers is reduced. There is no occurrence, the thickness is thin, and the formation density of the via portion can be increased, and a small and thin resin-encapsulated semiconductor device can be manufactured. Further, in the above method for manufacturing a multilayer wiring board, a metal conductive layer is used, and this metal conductive layer is patterned after removal of the base substrate to form an external terminal wiring. Is unnecessary, and the process becomes simple. Furthermore, in the method for manufacturing a resin-encapsulated semiconductor device according to the present invention, the steps of forming a through hole and conduction in the through hole are not required, so that the process is simple and a thin resin encapsulant without a core substrate is present. It is possible to manufacture a stationary semiconductor device, and since a semiconductor element can be mounted from a plurality of surfaces on a multilayer wiring board (base substrate) to resin sealing simultaneously, a highly accurate resin-encapsulated semiconductor device can be manufactured. Is possible.
[Brief description of the drawings]
FIG. 1 is a partial longitudinal sectional view showing an embodiment of a multilayer wiring board according to the present invention.
FIG. 2 is a partial longitudinal sectional view showing another embodiment of the multilayer wiring board of the present invention.
FIG. 3 is a process diagram showing an embodiment of a method for producing a multilayer wiring board according to the present invention.
FIG. 4 is a process diagram showing an embodiment of a method for producing a multilayer wiring board according to the present invention.
FIG. 5 is a drawing for explaining another embodiment of the method for producing a multilayer wiring board according to the present invention.
FIG. 6 is a process diagram showing an embodiment of a method for producing a resin-encapsulated semiconductor device of the present invention.
FIG. 7 is a process diagram showing another embodiment of a method for producing a resin-encapsulated semiconductor device of the present invention.
FIG. 8 is a process diagram showing another embodiment of a method for producing a resin-encapsulated semiconductor device of the present invention.
[Explanation of symbols]
1 ... Multilayer wiring board
2, 2A, 2B ... Internal terminal wiring
2a, 2b, 2c ... wiring
3a, 3b, 3c ... electric insulation layer
4a, 4b, 4c ... via part
5, 5A, 5B ... External terminal wiring
5a ... External terminal
11 ... Base substrate
12 ... recess
15 ... Metal conductive layer
21 ... Resin-sealed semiconductor device
22. Semiconductor element
24 ... Sealing member
31 ... Base substrate
35 '... Metal conductive layer
32, 32A, 32B ... internal terminal wiring
32a, 32b, 32c ... wiring
33a, 33b, 33c ... electric insulation layer
34a, 34b, 34c ... via part
35, 35A, 35B ... External terminal wiring
42. Semiconductor element
44 ... Sealing member

Claims (11)

Forming a metal conductive layer on one surface of the base substrate;
By providing at least one layer of wiring that is electrically connected to the via portion formed in the electrical insulating layer via the electrical insulating layer on the metal conductive layer, a plurality of wirings can be arranged corresponding to the mounting position of the semiconductor element. Forming the internal terminal wiring of
Removing the base substrate and exposing the metal conductive layer;
And a step of pattern-etching the metal conductive layer to form a plurality of external terminal wirings so as to correspond to the respective internal terminal wirings. On one surface of the base substrate, according to claim 1, formed in advance recesses so as to correspond to the relay terminal wires, and forming a metal conductive layer on the surface forming the recess A method for manufacturing a multilayer wiring board. 3. The method of manufacturing a multilayer wiring board according to claim 1 , wherein the base substrate has a coefficient of thermal expansion in the XY direction in a range of 2 to 20 ppm. 4. The method of manufacturing a multilayer wiring board according to claim 3 , wherein the base substrate is any one of silicon, glass, and 42 alloy. The method for manufacturing a multilayer wiring board according to claim 1 , wherein the metal conductive layer is copper. Forming a metal conductive layer on one surface of the base substrate;
By providing at least one layer of wiring that is electrically connected to the via portion formed in the electrical insulating layer via the electrical insulating layer on the metal conductive layer, a plurality of wirings can be arranged corresponding to the mounting position of the semiconductor element. Forming the internal terminal wiring of
Removing the base substrate and exposing the metal conductive layer;
A step of pattern etching the metal conductive layer to form a plurality of external terminal wirings corresponding to each internal terminal wiring to form a multilayer wiring board;
Mounting a semiconductor element on the multilayer wiring substrate on the internal terminal wires,
A step of resin-sealing the semiconductor element;
And a step of cutting and separating the multilayer wiring board and the sealing resin to obtain individual resin-encapsulated semiconductor devices. Forming a metal conductive layer on one surface of the base substrate;
By providing at least one layer of wiring that is electrically connected to the via portion formed in the electrical insulating layer via the electrical insulating layer on the metal conductive layer, a plurality of wirings can be arranged corresponding to the mounting position of the semiconductor element. Forming the internal terminal wiring of
Mounting a semiconductor element on each internal terminal wiring, and then sealing the semiconductor element with resin;
Removing the base substrate and exposing the metal conductive layer;
Forming a plurality of external terminal wirings so as to correspond to the respective internal terminal wirings by pattern etching the metal conductive layer;
And a step of cutting and separating the electrically insulating layer and the sealing resin to obtain individual resin-encapsulated semiconductor devices. On one surface of the base substrate, forming a pre-recess so as to correspond to the relay terminal wiring, claim 6 or claim and forming a metal conductive layer on the surface forming the recess A method for producing a resin-encapsulated semiconductor device according to claim 7 . 9. The method of manufacturing a resin-encapsulated semiconductor device according to claim 6 , wherein the base substrate has a thermal expansion coefficient in the XY direction within a range of 2 to 20 ppm. The method for manufacturing a resin-encapsulated semiconductor device according to claim 9 , wherein the base substrate is any one of silicon, glass, and 42 alloy. The method for manufacturing a resin-encapsulated semiconductor device according to claim 6 , wherein the metal conductive layer is copper.

Images