JP4044332B2 - High voltage semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
  The present invention relates to a power semiconductor device that controls a large current, and more particularly to a high-withstand-voltage power semiconductor device.
[0002]
[Prior art]
  Silicon carbide (SiC), which is a wide gap semiconductor material, has excellent characteristics such as about 10 times higher dielectric breakdown field strength than silicon (Si), and has high resistance to high reverse voltage characteristics. It attracts attention as a suitable material for voltage power semiconductor devices.
  As a conventional wide gap high withstand voltage semiconductor device using SiC, for example, a SiC pn diode having a withstand voltage of about 12 kV shown in the cross-sectional view of FIG. 9 is a preliminary collection of International Symposium on Power Semiconductor Devices & ICs of 2001. Pages 27-30. FIG. 9 shows an enlarged cross section of the right half of the SiC pn diode, and the left half is not shown because it is symmetrical with the right half. In this conventional example, an n-type drift layer 102 is formed on the upper surface of an n-type SiC cathode region 101 having a cathode electrode 107 on the lower surface, and a p-type layer 103 is formed in the central portion of the n-type drift layer 102. The p-type layer 103 is provided with an anode contact electrode 108 made of a thin metal film having a good conductor. The anode contact electrode 108 is provided with a metal film anode electrode 109 which is made thick in order to reduce electric resistance. For the anode contact electrode 108, titanium or the like having excellent adhesion to SiC is used, and for the anode electrode 109, corrosion-resistant gold or the like is used. A termination region T is provided in the end region of the p-type layer 103. The “termination region” refers to a peripheral region having a special structure in order to suppress electric field concentration in the peripheral portion of the high voltage semiconductor element. A p-type region 104 is formed at the left end of the termination region T, and an n-type channel stopper region 105 for preventing the depletion layer from spreading to the end of the n-type drift layer 102 is formed at the right end. . On the surface of the high withstand voltage diode, a passivation film 106 of a silicon dioxide film having a thickness of about 2 μm is provided for surface protection except for the anode electrode 109.
[0003]
  FIG. 10 is a cross-sectional view of a conventional SiC MOS field effect transistor (MOSFET). The chip size of this MOSFET is 4 mm (4 mm × 4 mm) both vertically and horizontally. In the figure, an n-type drift layer 2 is formed on a substrate serving as a high impurity concentration n-type drain layer 11 having a drain electrode 53 on the lower surface. An n-type source layer 7 is formed in a part of a p-type body layer 33 partially formed on the n-type drift layer 2, and a trench (groove) 60 is formed in the p-type body layer 33. A gate 54 is formed in the trench 60 via the gate insulator layer 8. A source contact electrode 155 is provided on the p-type body layer 33 and the n-type source layer 7, and all the source contact electrodes 155 are connected to the source electrode 161 at a portion where the trench 60 is not provided.
[0004]
  FIG. 11 is a sectional view of a conventional SiC gate turn-off thyristor (GTO). In the figure, a low impurity concentration n-type drift layer 2 is formed on a high impurity concentration p-type SiC substrate having an anode electrode 51 and functioning as the anode layer 21. A p-type layer 22 is formed on the n-type drift layer 2, and an n-type cathode region 23 is formed on the entire surface of the p-type layer 22. A predetermined portion of the n-type cathode region 23 is etched to a depth reaching the p-type layer 22, and a gate electrode 54 is formed in contact with the p-type layer 22 at the etched portion. All the gate electrodes 54, 54, 54... Are connected in common at positions that are not visible in the cross section of FIG. A cathode contact electrode 159 is formed on the remaining n-type cathode region 23. Cathode electrodes 150 that are in contact with the cathode contact electrodes 159 are formed on all the cathode contact electrodes 159.
[0005]
[Problems to be solved by the invention]
  SiC is suitable for increasing the withstand voltage of a semiconductor device because of its high dielectric breakdown electric field strength, but the SiC single crystal substrate has many crystal defects called micropipes with a diameter of about several μm. For this reason, when it is going to manufacture a semiconductor device with a large area, a yield will worsen. The maximum area of a practical SiC semiconductor device is 0.7 cm.²Degree. Therefore, it is necessary to ensure a high reverse withstand voltage in such a semiconductor device having a relatively small area. Since a semiconductor device using SiC has a dielectric breakdown electric field about 10 times higher than that of Si, a reverse resistance to the same degree as that of a Si semiconductor device in a termination region T having a shorter width than a semiconductor device using Si. Have voltage. Such a reverse withstand voltage in the semiconductor device is called “internal withstand voltage”. The internal withstand voltage is substantially equal to the breakdown voltage.
[0006]
  In an SiC semiconductor device, it is desirable to increase the areas of the anode contact electrode 108 and the anode electrode 109 and to reduce the area of the termination region T as much as possible in order to increase the current-carrying area as much as possible. However, when the termination region T is reduced and the area of the anode electrode 109 is increased in a semiconductor device having a small area, the distance between the end R1 of the semiconductor device and the end R2 of the anode electrode 109 is shortened. As a result, there is a problem that the “external withstand voltage”, which is the withstand voltage of the space between the end R1 close to the potential of the cathode electrode 107 and the end R2 at the anode potential, becomes low and causes air discharge. For example, in the case of the SiC high voltage diode shown in FIG. 9, since the width of the termination region T is 500 microns, the distance between the end portions R1 and R2 is also about 500 microns. When nitrogen that is generally used in a Si semiconductor device is used as the sealing gas for the diode package, the breakdown electric field of nitrogen is 3.8 kV / mm, so that the discharge start voltage is 1 at a distance of 500 microns. Air discharge occurs at .9 kV (= 3.8 kV / mm × 0.5 mm). The withstand voltage of the semiconductor device is determined by the lower of the internal withstand voltage and the external withstand voltage.
[0007]
  As a method of increasing the external withstand voltage between the end portions R1 and R2, it is conceivable to cover the right side portion of the anode electrode 109 including the end portion R2 with a passivation film 106A as indicated by a dotted line. The SiC semiconductor element is often used at a high temperature of 300 to 700 ° C., and the passivation film 106A must be a film of a heat resistant material such as silicon dioxide. It is difficult to form silicon dioxide on a wall with a high level difference like the end portion R2, and even if it can be formed, cracking and peeling may occur due to the temperature cycle during use, and long-term reliability is lacking. There's a problem.
  The above-mentioned problems are the same for the conventional MOSFET shown in FIG. 10 and the conventional GTO shown in FIG.
  An object of the present invention is to provide a semiconductor device having a high external withstand voltage in a semiconductor device having a relatively small area.
[0008]
[Means for Solving the Problems]
  The high voltage semiconductor device of the present invention is
  A high-impurity wide gap semiconductor substrate having a first electrode on one side;
  A low-impurity wide gap semiconductor drift layer formed on the other surface of the substrate;
  A termination region having at least one high impurity concentration region of the same conductivity type as the drift layer, formed in an outer peripheral region in the upper portion of the drift layer;
  Above the drift layerOn the inside of the termination area in the part, adjacent to the termination areaFormed wide gap semiconductor active region generation layer,
  in frontA second electrode formed on the active region generating layer;
  The second electrodeOn top of the, The termination areaInner peripheryKeep a certain distance fromFormed and electrically connected to the second electrode.A third electrode, and
  The termination areaWhen,The second electrodeAnd a region exposed from the third electrode inSurface protective film formed to cover
  Have
  Since the third electrode is away from the outer edge having a high potential in the termination region, the air discharge start voltage between the third electrode and the outer edge is increased.
[0009]
  A high withstand voltage semiconductor device according to another aspect of the present invention provides:
  A wide-gap semiconductor substrate of a first conductivity type having a high impurity concentration and having a first electrode on one surface;
  A drift layer of a first conductivity type wide gap semiconductor having a low impurity concentration formed on the other surface of the substrate;
  A termination region having at least one high impurity concentration region of the first conductivity type formed in an outer peripheral region in an upper portion of the drift layer;
  Above the drift layerOn the inside of the termination area in the part, adjacent to the termination areaFormedAsAn active region generating layer of a second conductivity type wide gap semiconductor in which the impurity concentration in the portion far from the drift layer is higher than the impurity concentration in the portion near the drift layer,
  in frontA second electrode formed on the active region generating layer;
  The second electrodeOn top of the, The termination areaInner peripheryKeep a certain distance fromFormed and electrically connected to the second electrode.A third electrode, and
  The termination areaWhen,The second electrodeAnd a region exposed from the third electrode inSurface protective film formed to cover
  Have
  The active region is widened by increasing the impurity concentration in the portion far from the drift layer with respect to the impurity concentration in the portion near the drift layer of the active region generation layer.
[0010]
  A high withstand voltage semiconductor device according to another aspect of the present invention provides:
  A wide-gap semiconductor substrate of a first conductivity type having a high impurity concentration and having a first electrode on one surface;
  A low impurity concentration formed on the other surface of the substrate.SaidA drift layer of a wide gap semiconductor of a first conductivity type;
  A termination region having at least one high impurity concentration region of the first conductivity type formed in an outer peripheral region in an upper portion of the drift layer;
  Above the drift layerOn the inside of the termination area in the part, adjacent to the termination areaFormedThe secondOf wide-gap semiconductorFirst semiconductorlayer,
  Provided so as to penetrate the first semiconductor layer and reach the drift layer, and the first semiconductor layer andVia an insulating film to the drift layerAs opposed toAs a gate electrodeOperateA second electrode,
  Over the first semiconductor layer.Near the second electrodeBesideFormationAnd opposed to the second electrode through the insulating filmdidSaidHigh impurity concentration of the first conductivity typeSecond semiconductorregion,
  The secondSemiconductor region and the first semiconductor layer between the second semiconductor regionProvided onAs,Electrical contact with the second semiconductor regionContact electrodes,
  Contact electrodeOn top of the, The termination areaInner peripheryKeep a certain distance fromFormed and electrically connected to the contact electrode.A third electrode, and
  The termination areaWhen,Contact electrode, A region exposed from the third electrode on the surface of the first semiconductor layer on which the second electrode and the insulating film are formed;Surface protective film formed to cover
  Have
  By thickening the contact electrode of the MOS field effect type semiconductor device and separating the third electrode from the termination region by a predetermined distance, the active region becomes wider and the withstand voltage becomes higher.
[0011]
  A high withstand voltage semiconductor device according to another aspect of the present invention provides:
  High impurity concentration with a first electrode on one sideFirstWide gap semiconductor substrate of conductive type,
  A low impurity concentration formed on the other surface of the substrate.SecondWide gap semiconductor drift layer of conductivity type,
  A termination region having at least one high impurity concentration region of the second conductivity type formed in an outer peripheral region in an upper portion of the drift layer;
  Above the drift layerOn the inside of the termination area in the part, adjacent to the termination areaFormed,FirstOf wide-gap semiconductor of conductivity typeFirst semiconductorlayer,
  Provided so as to penetrate the first semiconductor layer and reach the drift layer, and the first semiconductor layer andVia an insulating film to the drift layerAs opposed toAs a gate electrodeOperateA second electrode,
  Over the first semiconductor layer.Near the second electrodeBesideFormationAnd Opposing to the second electrode through an edge filmdidThe secondHigh impurity concentration of conductivity typeSecond semiconductorregion,
  The secondSemiconductor region and the first semiconductor layer between the second semiconductor regionProvided onAs,Electrical contact with the second semiconductor regionContact electrodes,
  Contact electrodeOn top of the, The termination areaInner peripheryKeep a certain distance fromFormed and electrically connected to the contact electrode.A third electrode, and
  The termination areaWhen,Contact electrode, A region exposed from the third electrode on the surface of the first semiconductor layer on which the second electrode and the insulating film are formed;Surface protective film formed to cover
  Have
  By thickening the contact electrode of the insulated gate bipolar semiconductor device and separating the third electrode from the termination region by a predetermined distance, the active region is expanded and the withstand voltage is increased.
[0012]
  A high withstand voltage semiconductor device according to another aspect of the present invention provides:
  High impurity concentration with anode of first electrode on one sideFirstWide gap semiconductor substrate of conductive type,
  A low impurity concentration formed on the other surface of the substrate.SecondWide gap semiconductor drift layer of conductivity type,
  A termination region having at least one high impurity concentration region of the second conductivity type formed in an outer peripheral region in an upper portion of the drift layer;
  Above the drift layerOn the inside of the termination area in the part, adjacent to the termination areaFormed,FirstOf wide-gap semiconductor of conductivity typeFirst semiconductorlayer,
  in frontRecordFirst semiconductorFormed on the layer,SecondCathode region of conductivity type,
  SaidFirst semiconductorOn the layerBetween the cathode regions inA gate electrode of the formed second electrode;
  Provided on the cathode region.As,Electrical contact with the cathode regionCathode contact electrode,
  The cathode contact electrodeOn top of the, The termination areaInner peripheryKeep a certain distance fromFormed and electrically connected to the cathode contact electrode.A cathode electrode of the third electrode; and
  The termination areaWhen,SaidCathodeContact electrode, A region exposed from the cathode electrode on a surface of the first semiconductor layer on which the cathode region and the second electrode are formed;Surface protective film formed to cover
  Have
  By increasing the contact electrode of the semiconductor device of the gate turn-off thyristor and keeping the third electrode at a predetermined distance from the termination region, the active region is widened and the withstand voltage is increased.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
  A preferred embodiment of the present invention will be described below with reference to FIGS.
<< First Example >>
  FIG. 1 is a top view of a high voltage semiconductor device using a silicon carbide (SiC) semiconductor material according to a first embodiment of the present invention. The semiconductor device of the first embodiment is a SiC pn diode having a design withstand voltage of 12 kV, and the vertical and horizontal dimensions of the specific example are both 8 mm (8 mm × 8 mm). 2 is a cross-sectional view taken along the line II-II in FIG. 1, and shows a cross section of the right half of FIG. In FIG. 2, a low impurity concentration n having a thickness of about 100 μm is formed on a substrate serving as a drain layer 1 of high impurity concentration n-type SiC having a cathode electrode 50 of the first electrode on the lower surface. A drift layer 2 of type SiC is formed. The cathode electrode 50 may be provided with a terminal 50A. The left portion of the drift layer 2 has a low impurity concentration of about 2 μm, for example, 1 × 10 10¹⁷atm / cm³The p-type layer 3 which is an active region generation layer is formed by an epitaxial growth method. The active region generation layer injects electric charges into the drift layer 2 when energized to turn on the semiconductor device. In the process of forming the p-type layer 3, the impurity concentration is controlled so that the impurity concentration of the upper layer portion 3 A of the p-type layer 3 is 1 × 10¹⁹atm / cm³Increase to a high degree. A second electrode anode contact electrode 52 of 7 mm (7 mm × 7 mm) in length and width is formed on the p-type layer 3 by a metal film such as titanium, and the anode contact electrode 52 is formed at the left end portion in the drawing. A third electrode anode 51 made of gold or the like is provided. As shown in the top view of FIG. 1, the anode contact electrode 52 and the anode electrode 51 are each substantially rectangular and are formed concentrically in the central region of the diode. The anode electrode 51 may be provided with a connection terminal 51A.
[0014]
  In FIG. 2, the drift layer 2 is etched shallowly by a kind of reactive ion etching method of the mesa etching method to form a termination region T. A p-type region 4 is formed by ion implantation of boron or aluminum from the upper surface of the termination region T. Its width (length in the left-right direction in the figure) is about 200 μm. The impurity concentration of the p-type region 4 is 10¹⁶To 10¹⁹atm / cm³It is preferable to be in the range. An n-type channel stopper region 5 having a width of about 200 μm is formed in the end region of the drift layer 2, that is, the right end portion (the outer peripheral portion in FIG. 1) of the termination region T. The distance between the p-type region 4 and the channel stopper region 5 is about 100 μm. On the surface of the termination region T, the slope of the p-type layer 3 adjacent to the termination region T, and the surface of the anode contact electrode 52, a passivation film 16 is formed as a surface protection film made of a thin film such as silicon dioxide or silicon nitride. The thickness of the passivation film 16 is in the range of 0.4 μm to 5 μm.
  In the SiC diode having both vertical and horizontal dimensions shown in the top view of FIG. 1 of 8 mm (8 mm × 8 mm), the end R3 of the anode electrode 51 is separated from the left end R4 of the termination region T by about 1 mm at the maximum. And about 1.5 mm away from the right end R1.
[0015]
  In the present embodiment, the electrical conductivity at the boundary between the anode contact electrode 52 and the p-type layer 3 is increased by increasing the impurity concentration of the upper layer portion 3A near the anode contact electrode 52 of the p-type layer 3. Therefore, although the anode electrode 51 is provided only in the central portion of the anode contact electrode 52 (see FIG. 1), all the regions of the anode contact electrode 52 become active regions where current flows. That is, an active region having a vertical and horizontal dimension of about 7 mm (7 mm × 7 mm) can be secured. The on-voltage of the pn diode of this example was 3.5V.
  In FIG. 2, when a voltage is applied in the reverse direction to the pn diode of this embodiment (hereinafter referred to as reverse bias), a cathode electrode 50 and an anode electrode are formed from the junction 34 between the p-type layer 3 and the n-type drift layer 2. A depletion layer spreads toward 51. When the reverse bias voltage increases, the depletion layer that spreads in the drift layer 2 spreads toward the channel stopper region 5 at the right end of the figure by the action of the p-type region 4. By this depletion layer, the electric field is relaxed, and a high reverse withstand voltage (internal withstand voltage) of 12 kV or higher, which is a design withstand voltage, is obtained. The internal withstand voltage is substantially equal to the breakdown voltage.
[0016]
  When the diode of this example having an internal withstand voltage of 12.3 kV was housed in a package filled with Fluorinert (trademark), which is an insulating liquid, and a reverse voltage application test was performed, the theoretical value of 12.3 kV was almost the theoretical value. The reverse withstand voltage was obtained. Since the dielectric breakdown electric field of Fluorinart (trademark) is 16 kV / mm, the reverse withstand voltage of 12.3 kV is due to the internal withstand voltage of this diode, and the external withstand voltage is found to be 12.3 kV or more. . However, since a SiC semiconductor device is used at a high temperature of several hundred degrees, it is not possible to use a fluorinate that easily evaporates at a high temperature.
  The external withstand voltage is mainly equal to the air discharge start voltage that depends on the distance between the end R1 of the channel stopper region 5 and the end R3 of the anode electrode 51. When an insulating gas is sealed in the package, the air discharge start voltage increases. For example, sulfur hexafluoride gas (SF) which is a highly insulating gas having a dielectric breakdown electric field of 9 kV / mm in the package.₆), A reverse withstand voltage of about 12 kV was obtained. Insulating gas is SF₆A mixed gas of nitrogen and nitrogen is also used. SF₆It has been found that the reverse withstand voltage is further increased when the gas pressure is higher than the atmospheric pressure.
  On the other hand, in the conventional SiC pn diode of FIG. 9, the reverse withstand voltage in Fluorinert (trademark) was 7 kV.₆The reverse withstand voltage was as low as 4 kV in the gas.
[0017]
  In the conventional SiC pn diode of FIG. 9, for example, when the width of the termination region T is increased to 1.5 mm, SF₆Although the reverse withstand voltage in the gas is 12 kV or more, the active region is reduced to 5 mm × 5 mm, which is about 50% less than that of the present example. As a result, the on-voltage of the diode increased from 3.5V to 5V.
  In the SiC pn diode of this example, an external withstand voltage higher than the high internal withstand voltage inherent in the SiC diode can be obtained while maintaining a wide active region having both vertical and horizontal dimensions of about 7 mm. When the SiC diode is used at a relatively low temperature of 150 ° C. or lower, an external withstand voltage is increased by applying a resin end protection material to the termination region T or covering the entire diode with a solid insulator such as silicon rubber. Can be high. The SiC pn diode according to the present embodiment is effective for one that is used at a high temperature of 300 ° C. or higher where an end protection agent or a solid insulator cannot be used, and one that uses a pressure contact type package that is difficult to apply the end protection agent. Since the end protection agent is not applied, the manufacturing process can be simplified. Since no resin is used, ions such as sodium do not adhere to the interface between the resin and the semiconductor, and the reliability of the semiconductor device is improved. The manufacturing process is also simplified.
[0018]
<< Second Embodiment >>
  FIG. 3 is a cross-sectional view of a SiC (silicon carbide) pn diode having a planar withstand voltage of 12 kV according to the second embodiment of the present invention. The SiC pn diode of the first embodiment has a mesa type termination region T. However, the present embodiment differs from the first embodiment in that the termination region T is a planar type. The chip size of the pn diode of this example is 6 mm (6 mm × 6 mm) in both vertical and horizontal dimensions. The end R3 of the anode electrode 51 is separated from the end R4 of the termination region T by about 1 mm. The impurity concentration of the upper layer portion 13A of the p-type layer 13 that is the active region generation layer is higher than that of the p-type layer 3. Other configurations and operations are the same as those of the first embodiment.
  The reverse withstand voltage of the pn diode of this example was 2.8 kV in nitrogen. SF₆It was 12.1 kV in highly insulating gas such as gas. Since the anode contact electrode 52 is formed from the center portion to the vicinity of the end portion R4 of the termination region T, the active region has a size of 5 mm × 5 mm (25 mm).²) And the maximum area can be secured, and the ON voltage is as low as 3.5V.
[0019]
  For example, in order to make a pn diode having the configuration of FIG. 9 with the same chip size 6 mm × 6 mm as that of this embodiment and to obtain a reverse withstand voltage of 12 kV, the width of the termination region T needs to be 1.5 mm. Yes, resulting in an active area of 3 mm x 3 mm (9 mm²) This area 9mm²Is the area of this embodiment 25 mm²It is 36% of that and becomes considerably narrow. The on-voltage was 6V, which is 70% or more higher than the on-voltage of 3.5V in this example.
  Since the pn diode of this example does not have the mesa structure in the termination region T, the reverse withstand voltage is slightly lower than that of the mesa structure, but there is no mesa formation process and the manufacturing process is simplified.
  In the present embodiment, the pn diode in which the p-type region 13 is present has been described. However, the Schottky diode in which the p-type region 13 is not formed and a metal such as Ni having rectifying properties is formed on the n-type drift layer 2. In addition, as in this embodiment, a high withstand voltage and a low on-voltage can be realized simultaneously.
[0020]
<< Third embodiment >>
  FIG. 4 is a cross-sectional view of a SiC MOS field effect transistor (MOSFET) having a design withstand voltage of 5 kV according to the third embodiment of the present invention. The chip size of this MOSFET is 4 mm (4 mm × 4 mm) both vertically and horizontally. In the figure, the thickness of the substrate serving as the high impurity concentration n-type drain layer 11 having the drain electrode 53 of the first electrode on the lower surface is about 200 μm. The n-type drift layer 2 formed on the drain layer 11 has a thickness of about 50 μm. The p-type body layer 33 partially formed on the n-type drift layer 2 has a thickness of about 4 μm, and the n-type source layer 7 formed on a part of the p-type body layer 33 has a thickness of about 0.5 μm. is there. These become the active region generation layer. The function of the active region generation layer is the same as that in the first embodiment. A trench (groove) 60 is formed in the p-type body layer 33. The depth of the trench 60 is about 6 μm and the width is about 3 μm. The thickness of the gate insulator layer 8 formed in the trench 60 is about 1 μm at the bottom of the trench 60 and about 0.1 μm at the side. A gate electrode 54 of the second electrode is provided in the trench 60 via the gate insulator layer 8. A source contact electrode 55 is provided on the p-type body layer 33 and the n-type source layer 7. The thickness of the source contact electrode 55 is about twice that of the source contact electrode 155 of the conventional MOSFET shown in FIG. 10 so as to have high conductivity. All the source contact electrodes 55 are connected in common at a portion where the trench 60 is not provided, and are connected to the source electrode 61 of the third electrode. The trench 60 and the gate electrode 54 may have a stripe shape extending in a direction perpendicular to the paper surface of the drawing, and may be, for example, a circle or a rectangle.
[0021]
  The manufacturing method of the MOSFET of this embodiment is as follows. In FIG. 4, the impurity concentration which functions as the drain layer 11 is 10¹⁸To 10²⁰atm / cm³N-type SiC substrate having an impurity concentration of 10 on the upper surface thereof.¹⁵To 10¹⁶atm / cm³The SiCn type drift layer 2 is formed by an epitaxial growth method. On the n-type drift layer 2, the impurity concentration is 10¹⁶atm / cm³A SiCp type body layer 33 having a thickness of about 30 is formed by an epitaxial growth method or the like. The p-type body layer 33 is left only in the left part of the figure, and the p-type body layer 33 in the other part is removed by mesa etching to form a termination region T. The impurity concentration is 10 by ion implantation in the termination region T.¹⁶To 10¹⁸atm / cm³P-type region 4 is formed. An n-type channel stopper region 5 is formed at the right end of the termination region T. The remaining p-type body layer 33 on the right side has an impurity concentration of 10¹⁹atm / cm³About n-type source region 7 is formed by ion implantation of nitrogen, phosphorus or the like. The impurity concentration of n-type source region 7 is 10 for the conventional MOSFET shown in FIG.¹⁸atm / cm³However, in this embodiment, the impurity concentration is 10¹⁹atm / cm³And about 10 times that of the conventional one.
[0022]
  Next, a trench 60 penetrating the p-type body layer 33 and having the bottom reaching the n-type drift layer 2 is formed by anisotropic etching. SiO on the inner wall of the trench 60₂After the gate insulating film 8 is formed, polysilicon containing high-concentration phosphorus is deposited to fill the trench 60. The polysilicon film adhered to the gate insulating film 8 on the inner wall of the trench 60 is left and other polysilicon is removed. A conductive material is filled in the recess from which the polysilicon is removed to form a gate electrode 54 including a polysilicon film. A source contact electrode 55 is formed on the surface of the n-type region 7 and the p-type body layer 33 with aluminum, nickel, or the like, and connected to the source electrode 61 in the center portion. A drain electrode 53 is formed on the drain layer 11. Finally, a passivation film 16 having a thickness of 0.5 μm or more is formed on the surface excluding the source electrode 61 to complete the MOSFET of this embodiment. The width of the termination region T in the drawing in the left-right direction is 0.5 mm. In the present embodiment, since the source electrode 61 is separated from the termination region T by 1 mm or more, the source electrode 61 is separated from the end R1 by about 1.5 mm.
  The withstand voltage was measured by setting the voltage between the source electrode 61 and the gate electrode 54 of the MOSFET thus configured to zero and applying a forward voltage between the source electrode and the drain electrode 53. When the MOSFET was placed in nitrogen gas, a withstand voltage of 4 kV or higher was obtained. SF₆When placed in the gas, the withstand voltage was 5.1 kV, and the withstand voltage almost as designed was obtained. The on-resistance is 55mΩcm²Met.
  In the MOSFET of the present embodiment, the drift layer 2 may be partially raised without forming a trench as shown in FIG. A gate electrode 54 is provided on the raised drift layer 2A via an insulating film 8A. In this configuration, the on-resistance is slightly higher than that in FIG. 4, but the withstand voltage is not changed.
[0023]
  In the MOSFET of this embodiment, the impurity concentration of the n-type source region 7 is about 10 times that of the conventional one, and the source contact electrode 55 having a thickness twice that of the conventional one is formed between the termination region T and the source electrode 61. Thus, these regions become active regions. In the MOSFET of FIG. 4, the vertical and horizontal dimensions of the active region are both 3 mm (3 mm × 3 mm), and the area is 9 mm.²It is.
[0024]
  In order to obtain a withstand voltage of 5.1 kV with the conventional MOSFET shown in FIG. 10, the width of the termination region T needs to be 1.5 mm. When a 1.5 mm wide termination region is provided in a MOSFET having a chip size of 4 mm × 4 mm, the vertical and horizontal dimensions of the active region are both 1 mm (1 mm × 1 mm), and the area is 1 mm.²It becomes. That is, the area of the active region of this example is 9 mm.²Therefore, it becomes nine times that of the conventional example. The on-resistance of the conventional MOSFET having the active region of 1 mm × 1 mm is 470 mΩcm.²It is about 8.5 times that of the present embodiment, which is inferior to that of the present embodiment.
[0025]
<< 4th Example >>
  FIG. 6 is a cross-sectional view of a SiC insulated gate bipolar transistor (IGBT) having a design withstand voltage of 5 kV according to a fourth embodiment of the present invention. The IGBT of this embodiment is obtained by changing the n-type drain layer 11 of the MOSFET of the third embodiment into a p-type drain layer 12. Other configurations are substantially the same as those of the MOSFET of the third embodiment. The chip size is 8 mm (8 mm × 8 mm) in both vertical and horizontal dimensions. In the present embodiment, the distance between the emitter electrode 57 of the third electrode and the termination region T is 1 mm or more, so that a distance of 1.5 mm or more can be secured between the emitter electrode 57 and the end portion R1. With the voltage of the gate electrode 65 of the second electrode of the IGBT set to zero, a forward voltage was applied between the emitter electrode 57 and the collector electrode 56 of the first electrode, and the withstand voltage was measured. As a result, a withstand voltage of 4 kV or higher was obtained even in a nitrogen atmosphere. Since an active region is also formed between the end R4 of the termination region T and the emitter electrode 57, the active region is as large as 76.5% (= 7 × 7 ÷ 8 ÷ 8) of the chip area. Despite being provided only at the center of the chip, the on-resistance did not increase. In this embodiment, since the collector layer 12 is p-type, holes are injected from the p-type collector layer 12 into the n-type drift layer 2 when on, and conductivity modulation occurs. As a result, the resistance of the n-type drift layer 2 decreases and the on-voltage decreases.
  In the IGBT of this embodiment, the drift layer 2 may be partially raised without forming a trench as shown in FIG. A gate electrode 65 is provided on the raised drift layer 2A via an insulating film 8A. In this configuration, the on-resistance is slightly higher than that in FIG. 6, but the withstand voltage is not changed.
[0026]
  In a conventional IGBT (not shown), the width of the termination region T needs to be 1.5 mm, so the area of the active region is 39% (= 5 × 5 ÷ 8 ÷ 8) of the chip area.
  The on-voltage of the IGBT of this embodiment was 4V, but the on-voltage of the conventional one is 6V. That is, in this embodiment, the on-voltage can be reduced by 33% compared to the conventional one. When the chip area is smaller, the effect obtained by this implementation is further increased.
[0027]
<< 5th Example >>
  FIG. 8 is a sectional view of a SiC gate turn-off thyristor (GTO) having a design withstand voltage of 20 kV according to the fifth embodiment of the present invention. In the figure, 10 functions as the anode layer 21 having the anode electrode 21 of the first electrode.¹⁸To 10²⁰atm / cm³10 p of high impurity concentration p-type SiC substrate¹⁴To 10¹⁶atm / cm³The low impurity concentration n-type drift layer 2 is formed by vapor phase epitaxy or the like. A p-type layer 22 is formed on the n-type drift layer 2. An n-type cathode region 23 is formed on the entire surface of the p-type layer 22. In the GTO of this embodiment, the impurity concentration of the n-type cathode region 23 is set to about 10 times that of the n-type cathode region 23 of the GTO shown in FIG. A predetermined portion of the n-type cathode region 23 is etched to a depth that reaches the p-type layer 22, and a gate electrode 54 of the second electrode is formed in contact with the p-type layer 22 at the etched portion. The p-type layer 22 and the n-type cathode region 23 form an active region generation layer. The function of the active region generation layer is the same as that in the first embodiment. All the gate electrodes 54, 54, 54... Are connected in common at positions that are not visible in the cross section of FIG. A cathode contact electrode 59 is formed in the remaining n-type cathode region 23. In this embodiment, the thickness of the cathode contact electrode 59 is increased to about twice the thickness of the conventional cathode contact electrode 159 shown in FIG. All the cathode electrodes 59, 59, 59... Are connected in common at positions that are not visible in the cross section of FIG. The cathode electrode 50 of the third electrode is formed on the cathode contact electrode 59 in the center of the GTO by using a gold film having a thickness of 10 μm in contact with the cathode contact electrode 59. A terminal 50 </ b> A may be provided on the cathode electrode 50. The formation method of the termination region T is the same as that of the first embodiment.
[0028]
  In the GTO of this embodiment, the width of the termination region T is 1 mm, and the distance between the termination region T and the cathode electrode 50 is 0.5 mm. The withstand voltage was measured by applying a forward voltage between the cathode electrode 50 and the anode electrode 51 while setting the voltage of the gate electrode 54 of the GTO of this embodiment to zero. SF of 1 atm GTO₆When placed in gas, the withstand voltage was 11.5 kV, and the design withstand voltage of 20 kV was not reached. So SF₆When the gas pressure was 2.5 atm, the withstand voltage was 21.5 kV, and the withstand voltage exceeding the design value could be obtained. Also in the GTO of this embodiment, almost all regions except the termination region T are active regions, so that a GTO with low on-resistance can be obtained.
[0029]
  The present invention described in each of the above embodiments includes many more scopes or derived structures. In the first to fifth embodiments, the case where the drift layer 2 is an n-type semiconductor device has been described. However, when the drift layer 2 is p-type, the n-type region of another element is changed to a p-type region. The configuration of the present invention can be applied by replacing the p-type region with the n-type region. In each of the above embodiments, the case where SiC is used as the wide gap semiconductor material has been described as an example. However, the present invention is a semiconductor device using other wide gap semiconductor materials such as diamond and gallium nitride having a high critical electric field. It can be effectively applied to.
[0030]
【The invention's effect】
  As is clear from the detailed description of the embodiments described above, the semiconductor device of the present invention is formed by forming the main electrode in the central portion of the semiconductor device away from the termination region, so that the main electrode and the end portion of the semiconductor device are formed. Can be made sufficiently large as long as it does not exceed the dielectric breakdown voltage of the gas sealed in the package of the semiconductor device. Thereby, the withstand voltage of the semiconductor device can be improved. In the region between the main electrode and the termination region, a wide active region is secured by increasing the impurity limit of the upper layer portion of the p-type body layer or increasing the thickness of the contact electrode, and the on-resistance of the semiconductor device can be kept low. it can.
  Furthermore, the semiconductor device of the present invention includes SF in its package.₆By enclosing an insulating gas containing gas as a main component, it has a high reverse withstand voltage even at a high temperature exceeding 200 ° C.
[Brief description of the drawings]
FIG. 1 is a top view of a SiC pn diode according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of the SiC pn diode according to the first embodiment of the present invention.
FIG. 3 is a sectional view of a SiC pn diode according to a second embodiment of the present invention.
FIG. 4 is a sectional view of a SiC MOSFET having a trench structure according to a third embodiment of the present invention.
FIG. 5 is a sectional view of another SiC MOSFET according to the third embodiment.
FIG. 6 is a sectional view of a SiC IGBT having a trench structure according to a fourth embodiment of the present invention.
FIG. 7 is a cross-sectional view of another SiC IGBT according to the fourth embodiment.
FIG. 8 is a sectional view of a SiC GTO according to a fifth embodiment of the present invention.
FIG. 9 is a sectional view of a conventional SiC pn diode.
FIG. 10 shows a cross section of a conventional SiC MOSFET.
FIG. 11 is a sectional view of a conventional SiC GTO.
[Explanation of symbols]
      1 Drain layer
      2 Drift layer
      3 p-type layer
      3A Upper layer
      4 p-type region
      5 Channel stopper area
      11 Drain layer
      12 Collector layer
      16 Passivation film
      21 Anode layer
      22 P-type layer
      23 Cathode region
      33 Body layer
      50 Cathode electrode
      51 Anode electrode
      52 Anode contact electrode
      53 Drain electrode
      54 Gate electrode
      55 Source contact electrode
      56 Collector electrode
      57 Emitter electrode
      58 Emitter contact electrode
      59 Cathode contact electrode
      60 trench
      61 Source electrode
      65 Gate electrode
      101 Cathode region
      102 Drift layer
      103 p-type layer
      104 p-type region
      105 Channel stopper area
      106 Passivation film
      107 Cathode electrode
      108 Anode contact electrode
      109 Anode electrode
      T termination area
      R1, R2, R3, R4 end

Claims (18)

A high-impurity wide gap semiconductor substrate having a first electrode on one side;
A low-impurity wide gap semiconductor drift layer formed on the other surface of the substrate;
A termination region having at least one high impurity concentration region of the same conductivity type as the drift layer, formed in an outer peripheral region in the upper portion of the drift layer;
The inside of the termination region, a wide-gap semiconductor active region generating layer formed adjacent to said termination region in the upper portion of the drift layer,
A second electrode formed on the front SL active region generating layer,
A third electrode formed on the second electrode at a predetermined separation distance from an inner periphery of the termination region and electrically connected to the second electrode; and the termination region ; , high withstand voltage semiconductor device having the second of said at electrode third forming surface protective film so as to cover the exposed area from the electrode.   The high withstand voltage semiconductor device according to claim 1, wherein the active region generation layer has an impurity concentration in a portion far from the drift layer higher than an impurity concentration in a portion near the drift layer. A wide-gap semiconductor substrate of a first conductivity type having a high impurity concentration and having a first electrode on one surface;
A drift layer of a first conductivity type wide gap semiconductor having a low impurity concentration formed on the other surface of the substrate;
A termination region having at least one high impurity concentration region of the first conductivity type formed in an outer peripheral region in an upper portion of the drift layer;
Inside it said termination region in the upper portion of the drift layer, is formed adjacent to the termination region Rutotomoni for impurity concentration in the portion close to the drift layer, increasing the impurity concentration of the portion far from the drift layer An active region generation layer of a wide gap semiconductor of the second conductivity type ,
A second electrode formed on the front SL active region generating layer,
A third electrode formed on the second electrode at a predetermined separation distance from an inner periphery of the termination region and electrically connected to the second electrode; and the termination region ; , high withstand voltage semiconductor device having the second of said at electrode third forming surface protective film so as to cover the exposed area from the electrode. The predetermined separation distance between the inner peripheral edge of the termination region and the third electrode is the air discharge start voltage between the outer peripheral edge of the termination region and the third electrode . electrodes and that selected breakdown voltage as from higher high withstand voltage semiconductor device according to claim 1 or 3 wherein between the second electrode. A wide-gap semiconductor substrate of a first conductivity type having a high impurity concentration and having a first electrode on one surface;
Was formed on the other surface of the substrate, a low impurity concentration said first conductivity type drift layer having a wider gap semiconductor of,
A termination region having at least one high impurity concentration region of the first conductivity type formed in an outer peripheral region in an upper portion of the drift layer;
The inside of the termination region, the formed adjacent the termination region, a first semiconductor layer of a wide-gap semiconductor of a second conductivity type in the upper portion of the drift layer,
A second electrode provided so as to penetrate the first semiconductor layer and reach the drift layer, and is opposed to the first semiconductor layer and the drift layer via an insulating film and operates as a gate electrode ,
Is formed in a near vicinity of the second electrode in an upper portion of the first semiconductor layer, a second high impurity concentration of the first conductivity type which is opposite to the second electrode through the insulating film Semiconductor region,
It said second semiconductor region and Rutotomoni provided on the first semiconductor layer between the second semiconductor region, the second semiconductor region and electrically contact electrodes making contact,
On the contact electrode, with the inner peripheral edge is formed with a predetermined separation distance of said termination region, and the contact electrode and electrically connected to the third electrode, and said termination region, the contact A MOS field effect type comprising: a surface protection film formed to cover the electrode , the second electrode, and a region exposed from the third electrode on the surface of the first semiconductor layer on which the insulating film is formed High-voltage semiconductor device.   6. The MOS field effect type high withstand voltage semiconductor device according to claim 5, wherein the first electrode is a drain electrode, and the third electrode is a source electrode. The predetermined separation distance between the inner peripheral edge of the termination region and the third electrode is the air discharge start voltage between the outer peripheral edge of the termination region and the third electrode . electrode and MOS field-effect high withstand voltage semiconductor device according to claim 5, wherein the selected was to be higher than the breakdown voltage between the third electrode. A wide-gap semiconductor substrate of a first conductivity type having a high impurity concentration and having a first electrode on one surface;
A drift layer of a low-concentration second conductivity type wide gap semiconductor formed on the other surface of the substrate;
A termination region having at least one high impurity concentration region of the second conductivity type formed in an outer peripheral region in an upper portion of the drift layer;
The inside of the termination region, the formed adjacent the termination region, a first semiconductor layer of a wide-gap semiconductor of a first conductivity type in the upper portion of the drift layer,
A second electrode provided so as to penetrate the first semiconductor layer and reach the drift layer, and is opposed to the first semiconductor layer and the drift layer via an insulating film and operates as a gate electrode ,
Is formed in a near vicinity of the second electrode in an upper portion of the first semiconductor layer, a second high impurity concentration of said second conductivity type opposed to the second electrode through the insulating film Semiconductor region,
It said second semiconductor region and Rutotomoni provided on the first semiconductor layer between the second semiconductor region, the second semiconductor region and electrically contact electrodes making contact,
On the contact electrode, with the inner peripheral edge is formed with a predetermined separation distance of said termination region, and the contact electrode and electrically connected to the third electrode, and said termination region, the contact An insulating gate bipolar type having a surface protective film formed to cover the electrode , the second electrode, and the region exposed from the third electrode on the surface of the first semiconductor layer on which the insulating film is formed High withstand voltage semiconductor device.   9. The high withstand voltage semiconductor device according to claim 8, wherein the first electrode is a collector electrode, and the third electrode is an emitter electrode. Said predetermined distance between the emitter electrode and the inner peripheral edge of said termination region, air discharge firing voltage between the outer edge and the emitter electrode of said termination region, and the emitter electrode and the collector electrode 10. The high withstand voltage semiconductor device according to claim 9 , wherein the high withstand voltage semiconductor device is selected so as to be higher than a breakdown voltage therebetween. 9. The high withstand voltage semiconductor device according to claim 5, wherein the second electrode is provided in a trench formed so as to penetrate the first semiconductor layer and reach the drift layer . A high-impurity concentration first- conductivity-type wide-gap semiconductor substrate having an anode electrode of the first electrode on one surface;
A drift layer of a low-concentration second conductivity type wide gap semiconductor formed on the other surface of the substrate;
A termination region having at least one high impurity concentration region of the second conductivity type formed in an outer peripheral region in an upper portion of the drift layer;
The inside of the termination region, the formed adjacent the termination region, a first semiconductor layer of a wide-gap semiconductor of a first conductivity type in the upper portion of the drift layer,
Formed on the front Symbol first semiconductor layer, the cathode region of the second conductivity type,
The second electrode the gate electrode of which is formed between the cathode region definitive on the first semiconductor layer,
Wherein provided on the cathode region Rutotomoni, the cathode region and electrically cathode contact electrode making contact,
A cathode electrode of a third electrode formed on the cathode contact electrode at a predetermined distance from the inner periphery of the termination region and electrically connected to the cathode contact electrode, and the termination region And a surface protection film formed so as to cover the cathode contact electrode , the cathode region, and the region exposed from the cathode electrode on the surface of the first semiconductor layer on which the second electrode is formed. Voltage semiconductor device. Said predetermined distance between the inner peripheral edge and the cathode electrode of said termination region, air discharge firing voltage between the outer peripheral edge and said third electrode of said termination region, wherein the cathode electrode and the anode that selected the to be higher than the breakdown voltage high withstand voltage semiconductor device according to claim 12, wherein between the electrodes. Claim, characterized in that the aerial discharge starting voltage is any discharge starting voltage in one atmosphere of a mixed gas of sulfur hexafluoride gas and sulfur hexafluoride gas and nitrogen gas 4,7,10 , high withstand voltage semiconductor device according to any one of 13. Wherein the semiconductor device, which houses the one of the gas of a mixed gas of sulfur hexafluoride gas及 beauty sulfur hexafluoride gas and nitrogen gas into a package which is sealed at a pressure above atmospheric pressure and a high withstand voltage semiconductor device according to any one of claims 1,3,5,8,12. High withstand voltage semiconductor device according to any one of claims 1,3,5,8,12, wherein the termination region is a mesa. High withstand voltage semiconductor device according to any one of claims 1,3,5,8,12, wherein the termination region is planar. The distance between the inner peripheral edge of the termination region and the third electrode is 0.3 times or more the width of the termination region, any one of claims 1, 3, 5, 8, and 12 high withstand voltage semiconductor device according to one.

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