JP4048711B2 - Thin film transistor panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor panel.
[0002]
[Prior art]
Some active matrix liquid crystal display devices include a thin film transistor panel and a counter substrate which are bonded together and liquid crystal is sealed therebetween. FIG. 4 shows a partial transmission plan view of an example of a thin film transistor panel in such a conventional liquid crystal display device. The thin film transistor panel includes a glass substrate 1. On the upper surface side of the glass substrate 1, scanning signal lines 2 and data signal lines 3 are provided in a matrix, and thin film transistors 4, pixel electrodes 5, and auxiliary capacitance electrodes 6 are provided in the vicinity of each intersection.
[0003]
The pixel electrodes 5 are delta arranged. That is, the three pixel electrodes 5 of R (red), G (green), and B (blue) constituting one pixel are arranged at positions corresponding to vertices of an isosceles triangle (Greek letter Δ). Therefore, the scanning signal line 2 is provided so as to extend linearly in the row direction between the upper and lower pixel electrodes 5, and the data signal line 3 meanders in the column direction between the left and right pixel electrodes 5 and between the upper and lower pixel electrodes 5. Is provided.
[0004]
The auxiliary capacitance electrode 6 includes a straight line portion 6a arranged in parallel to the scanning signal line 2 and an extending portion extending in the arrangement direction of the data signal line 3 at a position overlapping the data signal line 3 from the straight line portion 6a. 6b. In this case, the straight line portion 6 a is overlapped with the upper side portion of the pixel electrode 5. The width of the extension 6b is larger than the width of the data signal line 3, the left side of the extension 6b is overlapped with the right side of the pixel electrode 5 disposed on the left side of the data signal line 3, and the right side is the data signal. It overlaps with the left side of the pixel electrode 5 arranged on the right side of the line 3. Note that the dielectric strength improvement insulating film denoted by reference numeral 7 in FIG. 4 will be described later.
[0005]
Next, a specific structure of the thin film transistor panel will be described with reference to FIG. 5 which is a cross-sectional view taken along line XX in FIG. 4 and FIG. 6 which is a cross-sectional view taken along line YY in FIG. . In this case, for the sake of illustration, the planar size of FIG. 5 is twice the planar size of FIG. 4, and the planar size of FIG. 6 is four times the planar size of FIG. A scanning signal line 2 including a gate electrode 11 made of an aluminum-based metal or the like is provided at a predetermined position on the upper surface of the glass substrate 1, and an auxiliary capacitance electrode 6 also formed of an aluminum-based metal or the like is provided at another predetermined position. A gate insulating film 12 made of silicon nitride is provided on the entire upper surface.
[0006]
A semiconductor thin film 13 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 12 on the gate electrode 11. A channel protective film 14 made of silicon nitride is provided at a predetermined position on the upper surface of the semiconductor thin film 13. Ohmic contact layers 15 and 16 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 14 and on the upper surface of the semiconductor thin film 13 on both sides thereof.
[0007]
A data signal line 3 including a drain electrode 17 is provided at a predetermined location on the upper surface of one ohmic contact layer 15 and the upper surface of the gate insulating film 12. In this case, the data signal line 3 is provided with an n-type amorphous silicon film 3b and an intrinsic amorphous silicon film 3c under the metal film 3a made of chromium for forming the drain electrode 17, and has a substantially three-layer structure. ing. The intrinsic amorphous silicon film 3 c is formed simultaneously with the same film as the semiconductor thin film 13 when the semiconductor thin film 13 is formed. The n-type amorphous silicon film 3b is formed simultaneously with the same film as the ohmic contact layers 15 and 16 when the ohmic contact layers 15 and 16 are formed.
[0008]
In addition, the intrinsic amorphous silicon film 3c and the n-type are formed at the overlapping portion of the data signal line 3 and the extended portion 6b including the straight portion 6a of the auxiliary capacitance electrode 6 and at the intersection of the data signal line 3 and the scanning signal line 2. Between the amorphous silicon film 3b, there is provided a dielectric breakdown voltage improving insulating film 7 made of a channel protective film forming film for forming the channel protective film. That is, the dielectric breakdown voltage improving insulating film 7 is formed simultaneously with the same film as the channel protective film 14 when the channel protective film 14 is formed.
[0009]
Further, as shown in FIG. 4, the dielectric breakdown voltage improving insulating film 7 is provided with the same width over almost the entire arrangement region of the data signal lines 3 extending in the column direction, and the extended portion 6 b of the auxiliary capacitance electrode 6. It is provided so as to protrude to some extent from the three sides. Therefore, the left and right side portions of the pixel electrode 5 are overlapped with the insulating film 7 for improving dielectric strength. In FIG. 6, in order to emphasize the insulating film 7 for improving withstand voltage, hatching is written only in the insulating film 7 for improving withstand voltage.
[0010]
A source electrode 18 made of chromium is provided on the upper surface of the other ohmic contact layer 16. Here, the gate electrode 11, the gate insulating film 12, the semiconductor thin film 13, the channel protective film 14, the ohmic contact layers 15 and 16, the drain electrode 17 and the source electrode 18 constitute the thin film transistor 4. An overcoat film 19 made of silicon nitride is provided on the entire upper surface of the gate insulating film 12 including the thin film transistor 4 and the like. A pixel electrode 5 made of ITO is provided at a predetermined position on the upper surface of the overcoat film 19. The pixel electrode 5 is connected to the source electrode 18 through a contact hole 20 provided in the overcoat film 19.
[0011]
[Problems to be solved by the invention]
By the way, in the conventional thin film transistor panel, as described above, the dielectric breakdown voltage improving insulating film 7 is provided over almost the entire arrangement region of the data signal lines 3 extending in the column direction, and the extension portion 6b of the auxiliary capacitance electrode 6 is provided. It is provided to protrude to some extent from the three sides. For this reason, as shown in FIG. 6, each of the extended end portions of the extended portion 6 b of the auxiliary capacitance electrode 6, the end portion of the straight line portion 6 a on the opposite side, and both end portions in the width direction of the scanning signal line 2. At the position, a step 7 a is formed in the insulating film 7 for improving withstand voltage. On the other hand, the data signal line 3 has a three-layer structure of an intrinsic amorphous silicon film 3c, an n-type amorphous silicon film 3b, and a metal film 3a in order from the bottom, and among these, the intrinsic amorphous silicon film 3c and the n-type amorphous silicon film 3b. An insulating film 7 for improving the withstand voltage is provided between the two. However, the adhesion between the dielectric breakdown voltage improving insulating film 7 made of silicon nitride and the n-type amorphous silicon film 3b formed thereon is not so good, and therefore the portion overcoming the step 7a of the dielectric breakdown voltage improving insulating film 7 There is a problem that the n-type amorphous silicon film 3b is easily peeled off by the stress of the chromium metal film 3a, and the data signal line 3 is easily broken.
An object of the present invention is to make it difficult for a data signal line on an insulating film for improving dielectric strength to be disconnected.
[0012]
[Means for Solving the Problems]
According to the first aspect of the present invention, in the thin film transistor panel in which a thin film transistor, a pixel electrode, and an auxiliary capacitance electrode are provided in the vicinity of each intersection of the scanning signal line and the data signal line provided in a matrix, the scanning signal line and the auxiliary signal are provided. A gate insulating film is provided between the capacitor electrode and the data signal line, so that the dielectric breakdown voltage improving insulating film does not protrude from the auxiliary capacitor electrode between the overlapping portions of the data signal line and the auxiliary capacitor electrode. It is provided inside the auxiliary capacitance electrode, and the insulation breakdown voltage improving insulation film is provided on the gate insulation film .
According to a second aspect of the present invention, in the first aspect of the present invention, an insulating film for improving withstand voltage is not protruded from the scanning signal line between intersections of the scanning signal line and the data signal line. Is provided.
According to a third aspect of the present invention, in the first or second aspect of the present invention, a semiconductor thin film along the data signal line is provided on the gate insulating film, and the insulating breakdown voltage improving insulating film is formed on the semiconductor thin film. It is provided.
According to a fourth aspect of the invention, in the third aspect of the invention, an n-type semiconductor layer is provided under the data signal line, and the insulating film for improving withstand voltage is provided under the n-type semiconductor layer. is there.
The invention according to claim 5 is the invention according to any one of claims 1 to 4 , wherein the insulating film for improving the withstand voltage is the same as a film for forming a channel protective film for forming a channel protective film of the thin film transistor. It is formed of the material.
The invention according to claim 6 is the invention according to any one of claims 1 to 5 , wherein the side portion of the pixel electrode is provided between overlapping portions of the data signal line and the auxiliary capacitance electrode. It has a portion that overlaps with the insulation film for improving withstand voltage.
Then, according to the invention described in claim 1, without being stepped due to the end portion of the auxiliary capacitance electrodes on the insulating film for dielectric strength improving formation, thus the data signal lines in the dielectric strength improving insulating film is broken It can be difficult.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a transmission plan view of a main part of a thin film transistor panel according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line XX, and FIG. 3 is a sectional view taken along line YY. It is shown. In these drawings, for convenience of explanation, the same reference numerals are assigned to the same names as those of the conventional ones shown in FIGS.
[0014]
As shown in FIG. 1, the thin film transistor panel includes a glass substrate 1. On the upper surface side of the glass substrate 1, scanning signal lines 2 and data signal lines 3 are provided in a matrix, and thin film transistors 4, pixel electrodes 5, and auxiliary capacitance electrodes 6 are provided in the vicinity of each intersection.
[0015]
The pixel electrodes 5 are delta arranged. That is, the three pixel electrodes 5 of R (red), G (green), and B (blue) constituting one pixel are disposed at positions corresponding to the vertices of the isosceles triangle. Therefore, the scanning signal line 2 is provided so as to extend linearly in the row direction between the upper and lower pixel electrodes 5, and the data signal line 3 meanders in the column direction between the left and right pixel electrodes 5 and between the upper and lower pixel electrodes 5. Is provided.
[0016]
The auxiliary capacitance electrode 6 includes a straight line portion 6a arranged in parallel to the scanning signal line 2 and an extending portion extending in the arrangement direction of the data signal line 3 at a position overlapping the data signal line 3 from the straight line portion 6a. 6b. In this case, the straight line portion 6 a is overlapped with the upper side portion of the pixel electrode 5. The width of the extension 6b is larger than the width of the data signal line 3, the left side of the extension 6b is overlapped with the right side of the pixel electrode 5 disposed on the left side of the data signal line 3, and the right side is the data signal. It overlaps with the left side of the pixel electrode 5 arranged on the right side of the line 3. 1 will be described later.
[0017]
Next, a specific structure of the thin film transistor panel will be described with reference to FIGS. In this case, for the sake of illustration, the planar size of FIG. 2 is twice the planar size of FIG. 1, and the planar size of FIG. 3 is four times the planar size of FIG. A scanning signal line 2 including a gate electrode 11 made of an aluminum-based metal or the like is provided at a predetermined position on the upper surface of the glass substrate 1, and an auxiliary capacitance electrode 6 also formed of an aluminum-based metal or the like is provided at another predetermined position. A gate insulating film 12 made of silicon nitride is provided on the entire upper surface.
[0018]
A semiconductor thin film 13 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 12 on the gate electrode 11. A channel protective film 14 made of silicon nitride is provided at a predetermined position on the upper surface of the semiconductor thin film 13. Ohmic contact layers 15 and 16 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 14 and on the upper surface of the semiconductor thin film 13 on both sides thereof.
[0019]
A data signal line 3 including a drain electrode 17 is provided at a predetermined location on the upper surface of one ohmic contact layer 15 and the upper surface of the gate insulating film 12. In this case, the data signal line 3 is provided with an n-type amorphous silicon film 3b and an intrinsic amorphous silicon film 3c under the metal film 3a made of chromium for forming the drain electrode 17, and has a substantially three-layer structure. ing. The intrinsic amorphous silicon film 3 c is formed simultaneously with the same film as the semiconductor thin film 13 when the semiconductor thin film 13 is formed. The n-type amorphous silicon film 3b is formed simultaneously with the same film as the ohmic contact layers 15 and 16 when the ohmic contact layers 15 and 16 are formed.
[0020]
In addition, at the overlapping portion of the data signal line 3 and the extended portion 6b of the auxiliary capacitance electrode 6 and the intersection of the data signal line 3 and the scanning signal line 2, the intrinsic amorphous silicon film 3c and the n-type amorphous silicon film 3b Between them, there are provided a channel protective film forming film for forming the channel protective film 14 and dielectric films 7A and 7B for improving withstand voltage formed by the process. That is, the dielectric breakdown voltage improving insulating films 7A and 7B are simultaneously formed of the same material as the channel protective film 14 when the channel protective film 14 is formed.
[0021]
In addition, as shown in FIG. 1, the dielectric breakdown voltage improving insulating film 7 </ b> A is slightly inward from the four side end surfaces of the extension portion 6 b including the straight portion 6 a of the auxiliary capacitance electrode 6, that is, eroded from the four side end surfaces. It is provided not to protrude. In this case, the left and right side portions of the pixel electrode 5 are overlapped with the dielectric breakdown voltage improving insulating film 7A. The insulation breakdown voltage improving insulating film 7B is provided to some extent inside the widthwise end faces of the scanning signal line 2, that is, so as not to protrude from the both end faces. In FIG. 3, in order to emphasize the insulating films 7A and 7B for improving the withstand voltage, only the insulating films 7A and 7B for improving the withstand voltage are hatched.
[0022]
Here, when forming the dielectric breakdown voltage improving insulating films 7A and 7B and the channel protective film 14, a back exposure and an exposure mask using a photoresist as a mask for the scanning signal line 2 including the auxiliary capacitance electrode 6 and the gate electrode 11 are used. When formed by photolithography including surface exposure, the insulating films 7A and 7B for improving withstand voltage can be formed so as not to protrude from the auxiliary capacitance electrode 6 and the scanning signal line 2. That is, in the outer shape of the mask formed of the photoresist, the portion along the auxiliary capacitance electrode 6 and the scanning signal line 2 is in a region within several μm from the edge of the auxiliary capacitance electrode 6 and the scanning signal line 2 by the backside exposure. By defining the remaining portion of the outer shape of the mask by surface exposure, it is possible to accurately dispose the insulating films 7A and 7B for improving the withstand voltage inside the auxiliary capacitance electrode 6 and the scanning signal line 2. .
[0023]
A source electrode 18 made of chromium is provided on the upper surface of the other ohmic contact layer 16. Here, the gate electrode 11, the gate insulating film 12, the semiconductor thin film 13, the channel protective film 14, the ohmic contact layers 15 and 16, the drain electrode 17 and the source electrode 18 constitute the thin film transistor 4. An overcoat film 19 made of silicon nitride is provided on the entire upper surface of the gate insulating film 12 including the thin film transistor 4 and the like. A pixel electrode 5 made of ITO is provided at a predetermined position on the upper surface of the overcoat film 19. The pixel electrode 5 is connected to the source electrode 18 through a contact hole 20 provided in the overcoat film 19.
[0024]
As described above, in this thin film transistor panel, the withstand voltage improving insulating film 7A is disposed to some extent inside the four side end surfaces of the extending portion 6b including the straight portion 6a of the auxiliary capacitance electrode 6, that is, from the four side end surfaces. The insulation breakdown voltage improving insulating film 7B is provided so as not to protrude, and is provided to some extent inside the width direction both end faces of the scanning signal line 2, that is, so as not to protrude from both end faces. Steps caused by the end portions of the auxiliary capacitance electrode 6 and the scanning signal line 2 are not formed in the insulating films 7A and 7B, so that the data signal line 3 on the insulating films 7A and 7B for improving withstand voltage is not easily disconnected. can do.
[0025]
In the above embodiment, the insulation breakdown voltage improving insulating films 7A and 7B are formed on the intrinsic amorphous silicon film 3c formed on the gate insulating film 12. However, the present invention is not limited to this, and the insulating films 7A and 7B are formed on the gate insulating film 12. You may form directly.
[0026]
【The invention's effect】
As described above, according to the present invention, without being stepped due to the end portion of the auxiliary capacitance electrodes on the insulating film for dielectric strength improving formation, thus the data signal lines in the dielectric strength improving insulating film is less likely to break Can be.
[Brief description of the drawings]
FIG. 1 is a transparent plan view of a main part of a thin film transistor panel according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line XX in FIG.
3 is a cross-sectional view taken along line YY in FIG.
FIG. 4 is a partially transparent plan view of an example of a conventional thin film transistor panel.
5 is a cross-sectional view taken along line XX in FIG.
6 is a cross-sectional view taken along line YY in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Scan signal line 3 Data signal line 4 Thin-film transistor 5 Pixel electrode 6 Auxiliary capacity electrodes 7A and 7B Insulation film 14 for insulation withstand voltage improvement

Claims (6)

In a thin film transistor panel in which a thin film transistor, a pixel electrode and an auxiliary capacitance electrode are provided in the vicinity of each intersection of a scanning signal line and a data signal line provided in a matrix,
A gate insulating film is provided between the scanning signal line and the auxiliary capacitance electrode and the data signal line;
An insulation film for improving withstand voltage is provided inside the auxiliary capacitance electrode so as not to protrude from the auxiliary capacitance electrode between the overlapping portions of the data signal line and the auxiliary capacitance electrode,
The thin film transistor panel according to claim 1, wherein the insulating film for improving withstand voltage is provided on the gate insulating film .   The invention according to claim 1 is characterized in that an insulation film for improving dielectric strength is provided between the scanning signal line and the data signal line so as not to protrude from the scanning signal line. Thin film transistor panel.   3. The semiconductor thin film according to claim 1, wherein a semiconductor thin film is provided along the data signal line on the gate insulating film, and the insulating film for improving withstand voltage is provided on the semiconductor thin film. Thin film transistor panel. 4. The thin film transistor panel according to claim 3 , wherein an n-type semiconductor layer is provided under the data signal line, and the dielectric strength improvement insulating film is provided under the n-type semiconductor layer. In the invention of any one of claims 1 to 4, in that the dielectric strength improving insulating film which is formed by the same material as the channel protection film forming film for forming a channel protective film of the thin film transistor A thin film transistor panel. In the invention of any one of claims 1 to 5, the side portion of the pixel electrode is polymerized with the dielectric strength improving insulating film provided between the overlapping portion of the auxiliary capacitance electrode and the data signal lines A thin film transistor panel comprising a portion.

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