JP4049041B2 - Image processing circuit, image data processing method, electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is suitable for use in an electro-optical device that supplies each image signal to each data line at a predetermined timing that is divided into a plurality of systems and is time-axis extended and maintains a constant signal level per unit time. The present invention relates to an image processing circuit and an image data processing method, an electro-optical device using the image processing circuit, and an electronic apparatus.
[0002]
[Prior art]
A conventional electro-optical device, for example, an active matrix liquid crystal display device will be described with reference to FIGS.
[0003]
First, as shown in FIG. 15, the conventional liquid crystal display device includes a liquid crystal display panel 100, a timing circuit 200, and an image signal processing circuit 300. Among these, the timing circuit 200 outputs a timing signal (described later if necessary) used in each unit. A D / A conversion circuit 301 in the image signal processing circuit 300 converts image data Da supplied from an external device from a digital signal to an analog signal and outputs the converted signal as an image signal VID. Further, when a single image signal VID is input, the phase expansion circuit 302 expands the image signal VID into an N-phase (N = 6 in the figure) image signal and outputs the image signal. Here, the reason why the image signal is developed into the N phase is that the application time of the image signal supplied to the thin film transistor (hereinafter referred to as “TFT”) is increased in the sampling circuit described later, and the TFT panel This is to sufficiently secure the sampling time and charging / discharging time of the data signal.
[0004]
On the other hand, the amplifying / inverting circuit 303 inverts the polarity of the image signal under the following conditions and amplifies it appropriately, and then supplies it to the liquid crystal display panel 100 as the phase-developed image signals VID1 to VID6. Here, the polarity inversion means that the voltage level is alternately inverted with the amplitude center potential of the image signal as a reference potential. Whether to invert or not, whether the data signal application method is (1) polarity inversion in units of scanning lines, (2) polarity inversion in units of data signal lines, or (3) polarity in units of pixels. The inversion period is set to one horizontal scanning period or a dot clock period.
[0005]
Next, the liquid crystal display panel 100 will be described. The liquid crystal display panel 100 has a configuration in which an element substrate and a counter substrate face each other with a gap, and liquid crystal is sealed in the gap. Here, the element substrate and the counter substrate are made of a quartz substrate, hard glass, or the like.
[0006]
Among them, in the element substrate, a plurality of scanning lines 112 are arranged in parallel along the X direction in FIG. 16, and a plurality of data are paralleled along the Y direction orthogonal thereto. A line 114 is formed. Here, each data line 114 is divided into blocks of 6 units, and these are referred to as blocks B1 to Bm. Hereinafter, for the convenience of explanation, when a general data line is pointed out, the reference numeral is denoted as 114, but when a specific data line is pointed out, the reference numeral is denoted as 114a to 114f.
[0007]
At each intersection of the scanning line 112 and the data line 114, as a switching element, for example, the gate electrode of each TFT 116 is connected to the scanning line 112, while the source electrode of the TFT 116 is connected to the data line 114. The drain electrode of the TFT 116 is connected to the pixel electrode 118. Each pixel includes a pixel electrode 118, a common electrode formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes. A matrix is formed at each intersection of the scanning line 112 and the data line 114. Will be arranged in a shape. In addition, a storage capacitor (not shown) is formed in a state of being connected to each pixel electrode 118.
[0008]
Now, the scanning line driving circuit 120 is formed on the element substrate, and applies a pulse-like scanning signal to each scanning line based on the clock signal CLY from the timing circuit 200, its inverted clock signal CLYinv, the transfer start pulse DY, and the like. 112 are sequentially output. Specifically, the scanning line driving circuit 120 sequentially shifts the transfer start pulse DY supplied at the beginning of the vertical scanning period according to the clock signal CLY and its inverted clock signal CLYinv, and outputs the result as a scanning line signal. Each scanning line 112 is sequentially selected.
[0009]
On the other hand, the sampling circuit 130 includes a sampling switch 131 at each end of each data line 114 for each data line 114. The switch 131 is also composed of a TFT formed on the element substrate, and the image signals VID1 to VID6 are inputted to the source electrode of the switch 131 via the image signal supply lines L1 to L6. The gate electrodes of the six switches 131 connected to the data lines 114a to 114f of the block B1 are connected to the signal line to which the sampling signal S1 is supplied, and 6 are connected to the data lines 114a to 114f of the block B2. The gate electrodes of the switches 131 are connected to a signal line to which the sampling signal S2 is supplied. Similarly, the gate electrodes of the six switches 131 connected to the data lines 114a to 114f of the block Bm are the sampling signals. It is connected to a signal line to which Sm is supplied. Here, the sampling signals S1 to Sm are signals for sampling the image signals VID1 to VID6 for each block within the horizontal effective display period.
[0010]
The shift register circuit 140 is also formed on the element substrate, and sequentially outputs sampling signals S1 to Sm based on the clock signal CLX from the timing circuit 200, the inverted clock signal CLXinv, the transfer start pulse DX, and the like. Is. Specifically, the shift register circuit 140 sequentially shifts the transfer start pulse DX supplied at the beginning of the horizontal scanning period in accordance with the clock signal CLX and its inverted clock signal CLXinv and sequentially outputs them as sampling signals S1 to Sm. It is.
[0011]
In such a configuration, when the sampling signal S1 is output, the image signals VID1 to VID6 are sampled on the six data lines 114a to 114f belonging to the block B1, respectively. Each of the six pixels in the selected scanning line is written by the TFT 116.
[0012]
Thereafter, when the sampling signal S2 is output, the image signals VID1 to VID6 are sampled on the six data lines 114a to 114f belonging to the block B2, respectively, and these image signals VID1 to VID6 are obtained at that time. Each of the six pixels in the selected scanning line is written by the TFT 116.
[0013]
Similarly, when the sampling signals S3, S4,..., Sm are sequentially output, the image signals VID1 to VID6 are sampled on the six data lines 114a to 114f belonging to the blocks B3, B4,. Then, these image signals VID1 to VID6 are respectively written in the six pixels on the selected scanning line at that time. Thereafter, the next scanning line is selected, and similar writing is repeatedly executed in the blocks B1 to Bm.
[0014]
In this driving method, the number of stages of the shift register circuit 140 that controls the driving of the switch 131 in the sampling circuit 130 is reduced to 1/6 as compared with the method of driving each data line dot-sequentially. Further, since the frequency of the clock signal CLX to be supplied to the shift register circuit 140 and its inverted clock signal CLXinv can be reduced to 1/6, the number of stages can be reduced and the power consumption can be reduced.
[0015]
[Problems to be solved by the invention]
However, in the method of phase-developing one system of image signals into a plurality of systems and driving the liquid crystal display panel using the plurality of systems of image signals, the position is slightly shifted from the display position of the image to be originally displayed. There is a problem that an image having the same shape as the image is displayed lightly (hereinafter, this phenomenon is referred to as a ghost).
[0016]
There are various causes of ghosts, but there are two types as described below as specific ones related to phase development. The first cause is that the image signal supply lines L1 to L6 equivalently constitute a low-pass filter. That is, as shown in FIG. 15, the image signal supply lines L1 to L6 extend from the right end portion to the left end portion of the liquid crystal display panel 100 along the X direction, where distributed resistance exists and stray capacitance is present. Accompanying. Therefore, the image signal supply lines L1 to L6 equivalently constitute a low-pass filter. Therefore, the waveforms of the image signals VID1 to VID6 input to the switch 131 of the sampling circuit 130 are integrated waveforms. This point will be specifically described.
[0017]
FIG. 17 is a timing chart showing the waveforms of the image signal and sampling signal before and after phase expansion. In practice, a delay due to phase development occurs, but in this figure, the delay time is ignored for convenience of explanation. The liquid crystal display panel 100 is assumed to operate in a normally white mode.
[0018]
As shown in FIG. 6A, the image signal VID corresponds to the j−1th to j + 1th blocks, the intermediate level Vc in the period t1 to t3, the black level Vb in the period t4 to t14, and the period. If the intermediate level Vc is reached at t15 to t18, the image signals VID1 to VID6 after the phase expansion are as shown in FIGS.
[0019]
For example, paying attention to the image signal VID3 shown in FIG. 4D, the image signal VID is at the intermediate level Vc in the period t3, and is at the black level Vb in the period t9. At the start of t7, the image signal VID3 should rise steeply from the intermediate level Vc to the black level Vb as indicated by the dotted line in the figure.
[0020]
However, since the image signal supply line L3 equivalently constitutes a low-pass filter as described above, the image signal VID3 rises gently from the intermediate level Vc and reaches the black level Vb after a predetermined time has elapsed.
[0021]
Here, if the sampling signal Sj corresponding to the j-th block is active in the range from the period t7 to the period t12 as shown in FIG. 11H, the sampling signal Sj is supplied to the data line 114c of the j-th block. The image signal VID3 to be processed is affected by the image signal VID3 (VID3 in the period t1 to t6) to be supplied to the data line 114c of the (j-1) th block. As a result, when the voltage of the data line 114c is captured by the TFT 112 constituting the pixel, the voltage value is slightly lower than the black level, and the pixel becomes slightly brighter.
[0022]
Further, if the sampling signal Sj corresponding to the jth block becomes active in the range from the period t7 to the period t13 as shown in FIG. 6 (i), the sampling signal Sj is supplied to the data line 114c of the jth block. The image signal VID3 is not only the image signal VID3 (VID3 in the period t1 to t6) to be supplied to the data line 114c of the (j-1) th block but also the image to be supplied to the data line 114c of the j + 1th block. The signal VID3 (VID3 in the period t13 to t18) is affected.
[0023]
FIG. 18 is an explanatory diagram illustrating an example of a ghost attributed to the first cause described above. In this figure, the image to be originally displayed is an arrow P. On the other hand, the arrow P1 and the arrow P2 which are displayed lightly at a position about one block backward are ghosts.
[0024]
Next, the second cause of the occurrence of ghost is that each data line 114a to 114f in each block B1, B2,..., Bm is accompanied by a parasitic capacitance, and the parasitic capacitances are coupled. Is attributed. Since each data line 114a to 114f is formed on the element substrate as described above and faces the counter electrode of the counter substrate via the liquid crystal, parasitic capacitance is generated mainly between the counter electrodes. The counter electrode is grounded with a certain impedance. Therefore, if the parasitic capacitances of the data lines 114a to 114f are Ca to Cf and the impedance of the counter electrode is R, an equivalent circuit of the data lines 114a to 114f in a certain block is as shown in FIG. .
[0025]
Here, assuming that the image signal VID3 supplied to the data line 114c changes from the black level Vb to the intermediate level Vc in the block switching, the voltage Vx at the common connection point of the parasitic capacitances Ca to Cf is shown in FIG. Thus, the image signal VID3 is differentiated. Then, the voltages of the data lines 114a, 114b, and 114d to 114f change through the parasitic capacitors Ca, Cb, and Cd to Cf.
[0026]
For example, as shown in FIG. 21, it is assumed that one screen is composed of blocks B1 to B7, and a single vertical black line is displayed on a halftone background. In this case, if the image signal VID3 of the black level Vb is supplied to the data line 114c of the block B4, the image signal VID3 changes from the black level Vb to the intermediate level Vc at the time of switching from the block B4 to the block B5. . Then, the voltage of the data lines 114a, 114b, 114d to 114f of the block B4 is slightly higher than the voltage corresponding to the halftone under the influence of the differential waveform (see FIG. 20), so that the entire block B5 becomes slightly brighter.
[0027]
Thus, the method of driving the data lines 114 in a block has a problem that the quality of the display image is deteriorated by the above-described two kinds of ghosts.
[0028]
The present invention has been made in view of these problems, and an object of the present invention is to provide an image processing circuit and an image data processing method capable of displaying a high quality image by removing ghosts, and an electro-optical device using the image processing circuit. As well as providing electronic equipment.
[0035]
Next, an image processing circuit of the present invention includes a plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. Used in an electro-optical device for supplying each image signal divided into a system and expanded in time axis to each data line at a predetermined timing, and image data supplied from the outside is used as the image signal. A first delay circuit that outputs the first delayed image data after being delayed by the unit time, and a second delay circuit that outputs the first delayed image data as the second delayed image data after being delayed by the unit time of the image signal. A first difference circuit that generates a difference between the first delay image data and the second delay image data as first difference image data, and a first coefficient multiplied by a first coefficient. A first multiplication circuit for generating positive data; a second difference circuit for generating a difference between the first delayed image data and the image data as second difference image data; and a second coefficient for the second difference image data. A second multiplication circuit that generates second correction data by multiplication, a combining circuit that combines the first delay image data, the first correction data, and the second correction data to generate corrected image data; It is provided with.
[0036]
According to the present invention, each of the first delay circuit and the second delay circuit delays the image data by a unit time. Therefore, if the first delay image data is the current data, the image data is the future data and the second delay circuit. Image data corresponds to past data. Therefore, corrected image data can be generated by correcting current data based on not only past data but also future data.
[0037]
The electro-optical device includes a plurality of switch elements that sample the image signals according to a sampling signal and supply the image signals to the data lines, and image signal supply lines that supply the image signals to the switch elements. Preferably, the first coefficient and the second coefficient are determined according to characteristics of a low-pass filter equivalently configured by the image signal supply lines. Furthermore, it is preferable that the active period of the sampling signal starts from the current unit time of the image signal and ends at the next unit time.
[0038]
Since the voltage of the data line is determined at the end of the active period of the sampling signal, if the active period of the sampling signal ends in the next unit time, the voltage of the data line is affected by the image signal of the next unit time. Will receive. According to the present invention, the corrected image data is generated by correcting the current data based not only on the past but also on the future data, so that the image signal is generated by generating the image signal based on the corrected image data. Waveform deterioration that occurs in the process until the data line is supplied can be canceled. As a result, the ghost attributed to the stray capacitance of the wiring can be greatly reduced, and the quality of the display image can be dramatically improved.
[0039]
Next, in the image data processing method of the present invention, a plurality of scanning lines, a plurality of data lines, transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines, And is used in an electro-optical device that supplies each image signal to each data line at a predetermined timing that is divided into a plurality of systems and is time-axis extended and maintains a constant signal level per unit time. Then, image data supplied from the outside is set as future image data, which is sequentially delayed by the unit time to generate current image data and past image data, and the current image data and the past image data are generated. First correction data is generated based on a difference data value from image data, second correction data is generated based on a difference data value between the current image data and the future image data, It synthesizes the current image data and the first correction data and the second correction data and generates the corrected image data. According to the present invention, the corrected image data can be generated by correcting the current image data based on not only the past but also the future image data.
[0040]
Next, an image processing circuit of the present invention includes a plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. Used in an electro-optical device that is divided into a system and is time-extended to maintain each image signal at a predetermined timing to maintain a constant signal level for each unit time. A delay circuit that delays the image data supplied from the unit time and outputs the delayed image data as delayed image data; a difference circuit that generates a difference between the delayed image data and the image data as difference image data; and the difference image data An averaged circuit that averages every unit time to generate averaged image data, and corrects the corrected image by correcting the delayed image data based on the averaged image data Characterized by comprising a correction circuit for generating a chromatography data. Each data line is accompanied by a parasitic capacitance, and each adjacent data line is coupled via a parasitic capacitance, and these parasitic capacitances are equivalently grounded via a common impedance. For this reason, when the applied voltage of a certain data line changes, the potential of the other data line changes due to the influence, and a ghost corresponding to this changes. According to the above-described invention, the correction data is generated based on the averaged image data obtained by averaging the difference image data every unit time. Therefore, the correction data is a component corresponding to the ghost described above. Therefore, the corrected image image data can cancel a component by predicting a ghost in advance. As a result, if the image is displayed based on the corrected image data, the ghost can be almost eliminated, and the quality of the display image can be greatly improved.
[0041]
Here, the averaging circuit includes a cumulative addition unit that cumulatively adds the difference image data every unit time, and a division unit that divides the output data of the cumulative addition unit by the number of the plurality of systems. preferable. Furthermore, it is preferable that the correction circuit includes a coefficient unit that multiplies the averaged image data by a coefficient, and an addition unit that adds the delayed image data and the output data of the coefficient part.
[0042]
Next, in the image data processing method of the present invention, a plurality of scanning lines, a plurality of data lines, transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines, And is used in an electro-optical device that supplies each image signal to each data line at a predetermined timing that is divided into a plurality of systems and is time-axis extended and maintains a constant signal level per unit time. As a premise, the image data supplied from the outside is delayed by the unit time to generate delayed image data, the difference between the delayed image data and the image data is generated as difference image data, and the difference image data is Averaged image data is generated by averaging every unit time, and corrected image data is generated by correcting the delayed image data based on the averaged image data. To. According to the present invention, it is possible to generate correction data in which a ghost component generated due to capacitive coupling between adjacent data lines is predicted. Therefore, the corrected image image data can cancel a component by predicting a ghost in advance. As a result, if the image is displayed based on the corrected image data, the ghost can be almost eliminated, and the quality of the display image can be greatly improved.
[0043]
Next, the electro-optical device according to the present invention is divided into a plurality of systems based on the above-described image processing circuit and the corrected image data, and the time axis is extended to maintain a constant signal level for each unit time. An image signal generation circuit that generates an image signal, a data line driving circuit that sequentially generates the sampling signals, and a sampling circuit that samples the image signals based on the sampling signals and supplies the image signals to the data lines. It is characterized by having. According to the electro-optical device, the quality of the display image can be greatly improved, and the time for supplying the image signal to the data line can be extended.
[0044]
Next, an electronic apparatus according to the present invention is characterized by including the above-described electro-optical device, and includes, for example, a video projector, a notebook personal computer, a mobile phone, and the like.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0046]
<1. First Embodiment>
<1-1: Outline of Liquid Crystal Display>
First, an active matrix liquid crystal display device according to the first embodiment will be described as an example of an electro-optical device.
[0047]
FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device. The liquid crystal display device according to this embodiment is the same as the conventional liquid crystal display device shown in FIG. 15 except that the ghost removal circuit 304 is provided in the preceding stage of the D / A converter 301 in the image signal processing circuit 300A. It is configured. The image data Da in this example is an 8-bit parallel format, and is a data string whose sampling period is the period of the dot clock signal DCLK, and is supplied from an external device (not shown).
[0048]
The ghost removal circuit 304 predicts a ghost component due to the first cause described above in advance, corrects the image data Da so as to cancel it, and generates corrected image data Dout.
[0049]
The phase expansion circuit 302 performs serial / parallel conversion on the image signal VID obtained by performing DA conversion on the corrected image data Dout to generate phase expanded image signals VID1 to VID6 expanded in six phases. Specifically, the phase development circuit 302 samples and holds the image signal VID based on the six-phase sample hold pulses SP1 to SP6 and SS that become active every six cycles of the dot clock signal DCLK, and outputs the image signal VID. The time axis is expanded six times and divided into six systems to generate the phase-developed image signals VID1 to VID6.
[0050]
Since each phase development image signal VID1 to VID6 is generated based on the image signal VID obtained by DA-converting the corrected image data Dout synchronized with the dot clock signal DCLK, the value of the original corrected image data Dout is the dot clock cycle. If it changes every time, each phase expansion image signal VID1-VID6 changes for every 6 dot clock period. Accordingly, each of the phase development image signals VID1 to VID6 is a signal that changes with a unit time determined by the product of the number of phase developments (the number of systems to be divided) and one period of the dot clock signal DCLK.
[0051]
Next, the liquid crystal display panel 100 is the same as that used in the conventional liquid crystal display device shown in FIG.
[0052]
<1-2: Ghost removal circuit>
Next, the ghost removal circuit 304 will be described in detail. The ghost removal circuit 304 predicts a ghost component generated due to the image signal supply lines L1 to L6 equivalently forming a low-pass filter, and corrects the image data Da so as to cancel the ghost component. Used for.
[0053]
FIG. 2 is a circuit diagram of the ghost removal circuit 304. As shown in this figure, the ghost removal circuit 304 includes a first delay unit U 1, a first difference calculation circuit 31, a first coefficient circuit 32, and an addition circuit 33.
[0054]
First, the first delay unit U1 is configured by connecting six latch circuits LAT1 to LAT6 in series, and delays the image data Da for a predetermined time to output the image data Db. Here, each of the latch circuits LAT1 to LAT6 latches 8-bit input data based on the dot clock signal DCLK.
[0055]
The dot clock signal DCLK is a master clock of the liquid crystal display device and is generated in the timing circuit 200. The timing circuit 200 divides the dot clock signal DCLK to generate a clock signal CLX for driving the data line driving circuit of the liquid crystal display panel 100 and a clock signal CLY for driving the scanning line driving circuit. Yes. In this example, the phase expansion circuit 302 performs 6-phase expansion. Therefore, the clock signal CLX is generated by dividing the dot clock signal DCLK by 6.
[0056]
Since the first delay unit U1 is configured by serially connecting six latch circuits LAT1 to LAT6 driven by the dot clock signal DCLK, the image data Db is delayed by 6 dot cycles with respect to the image data Da. It becomes data.
[0057]
By the way, as described above, each phase development image signal VID1 to VID6 has a unit time defined by the product of the number of phase developments (the number of systems to which the image signal VID should be divided) and one period of the dot clock signal DCLK. The signal changes as follows. In this example, one unit time is a 6-dot period, which matches the delay time of the first delay unit U1. In other words, the first delay unit U1 generates the image data Db by delaying the image data Da by a time corresponding to one unit time of the phase expanded image signals VID1 to VID6 obtained by phase expansion (serial parallel conversion). To do. Here, if the image data Da is the current data, the image data Db becomes the past data for one unit time.
[0058]
Next, the first difference calculation circuit 31 calculates the difference between the image data Da and the image data Db. Specifically, the first difference data Ds1 is generated by subtracting the image data Db (past) from the image data Da (current). The first coefficient circuit 32 includes a multiplier, which multiplies the first difference data Ds1 and the coefficient K1 and outputs the multiplication result as first correction data Dh1.
[0059]
Next, the adding circuit 33 adds the first correction data Dh1 and the image data Da, and outputs the addition result as corrected image data Dout.
[0060]
Since the signal levels of the phase development image signals VID1 to VID6 are switched every unit time and become a constant level, when the signal level is changed, the signal waveform changes sharply at the input of the image signal supply lines L1 to L6. On the other hand, since the image signal supply lines L1 to L6 equivalently constitute a low-pass filter, the signal waveforms of the phase development image signals VID1 to VID6 supplied to the switches of the sampling circuit are integrated. That is, when transitioning from the previous unit time to the current unit time, the signal waveform gradually changes from the previous unit time level to the current unit time level. Therefore, the signal level of the phase development image signal in the current unit time is affected by the signal level of the immediately preceding unit time. The degree is determined according to the difference level between the signal level of the current unit time and the signal level of the immediately preceding unit time, and the characteristics of the low-pass filter.
[0061]
On the other hand, since the image data Db is data that is one unit time past with respect to the image data Da, if the image data Da corresponds to the phase-expanded image signal of the current unit time, the image data Db Corresponding to a phase-expanded image signal of unit time. Accordingly, the first difference data Ds1 corresponds to the difference level between the signal level of the current unit time and the signal level of the previous unit time. Here, the coefficient K1 described above is determined in advance according to the characteristics of the low-pass filter. Therefore, the first correction data Dh1 corresponds to a waveform component lost by being integrated by the low-pass filters of the image signal supply lines L1 to L6. In other words, the first correction data Dh1 is generated by predicting in advance the waveform components lost in the process of being transmitted through the image signal supply lines L1 to L6.
[0062]
Since the corrected image data Dout is generated by synthesizing the first correction data Dh1 and the image data Da, the corrected image data Dout is obtained by preliminarily emphasizing the waveform component lost by the integration. When phase-developed image signals VID1 to VID6 generated by performing phase expansion on the corrected image data Dout are supplied to the switches of the sampling circuit via the image signal supply lines L1 to L6, the signal waveforms are integrated and blunted. It will be. However, since the phase development image signals VID1 to VID6 are emphasized by the first correction data Dh1, the influence of the signal level in the immediately preceding unit time is canceled, and the phase development image signals VID1 to VID6 that are not affected by the influence are canceled by the sampling circuit. Is supplied to the data line 114. As a result, it is possible to eliminate ghosts generated by the image signal supply lines L1 to L6 equivalently forming a low-pass filter.
[0063]
<1-3: Phase expansion circuit>
Next, the phase expansion circuit 302 will be described. FIG. 3 is a block diagram showing the main configuration of the phase expansion circuit. As shown in this figure, the phase expansion circuit 302 includes a first sample hold unit USa including sample hold circuits SHa1 to SHa6 and a second sample hold unit USb including sample hold circuits SHb1 to SHb6. Yes.
[0064]
First, the sample hold circuits SHa1 to SHa6 of the first sample hold unit USa sample and hold the image signal VID based on the sample hold pulses SP1 to SP6 supplied from the timing circuit 200 to generate signals vid1 to vid6. It is like that. Here, one cycle of each of the sample hold pulses SP1 to SP6 corresponds to a cycle that is six times the dot clock signal DCLK, and the phase of each pulse is shifted by one cycle of the dot clock signal DCLK. Therefore, the signals vid1 to vid6 are signals whose time axis is expanded six times with respect to the image signal VID and whose phases are sequentially shifted by the dot clock signal period.
[0065]
Next, the sample hold circuits SHb1 to SHb6 of the second sample hold unit USb sample and hold the signals vid1 to vid6 based on the sample hold pulse SS supplied from the timing circuit 200, and the result is a buffer (not shown). The phase development image signals VID1 to VID6 are output via a circuit. The sample hold pulse SS is a pulse having a unit time period. Therefore, the phases of the signals vid1 to vid6 are aligned at the timing when the sample hold pulse SS becomes active, and phase expanded image signals VID1 to VID6 having the same phase are generated.
[0066]
<1-4: Operation of liquid crystal display device>
Next, the operation of the liquid crystal display device will be described in order. First, the operation from when the image data Da is input until the corrected image data Dout is generated by the ghost removal circuit 304 will be described. FIG. 4 is a timing chart for explaining the operation of the ghost removal circuit 304. In this figure, the subscript X in the case of DX, Y represents the number of the data line 114 corresponding to one block counted in the scanning direction in the block, while the subscript Y represents what. Let it be the th block. For example, D1, n + 1 corresponds to the first data line 114a in the block and represents that the block is the (n + 1) th data line.
[0067]
First, when the image data Da is supplied to the ghost removal circuit 304, the first delay unit U1 delays the image data Da by one unit time (6-dot period) and outputs it as the image data Db.
[0068]
Thereby, the image data Db one unit time before is obtained with respect to the image data Da. For example, paying attention to the period Tx shown in FIG. 4, the image data Da is D2, n, which corresponds to the data line 114b of the block Bn. On the other hand, the image data Db is D2, n-1 and corresponds to the data line 114b of the block Bn-1. The image signal VID2 is supplied to the data line 114b of each block via the image signal supply line L2. That is, both the image data Da and the image data Db in the period correspond to the image signal VID2 supplied via the image signal supply line L2. Further, since the image data Da and the image data Db correspond to adjacent blocks, they are data corresponding to before and after the signal level of the image signal VID2 is switched.
[0069]
Thereafter, when the first difference circuit 31 subtracts the second image data Db from the first image data Da to generate the first difference data Ds1, the first coefficient circuit 32 multiplies the first difference data Ds1 by the coefficient K1. The first correction data Dh1 is generated. Therefore, in the period Tx, the first difference data Ds1 is “D2, n−D2, n−1”, and the first correction data Dh1 is “K1 (D2, n−D2, n−1)”. . Furthermore, since the corrected image data Dout is obtained by adding the first correction data Dh1 and the image data Da, it becomes “D2, n + K1 (D2, n−D2, n−1)”.
[0070]
The corrected image data Dout obtained in this way is converted into an analog signal via the AD converter 301 and supplied to the phase development circuit 302 as an image signal VID. Next, an operation until the phase development image signals VID1 to VID6 are generated based on the image signal VID will be described. FIG. 5 is a timing chart showing the operation of the phase expansion circuit.
When the image signal VID is supplied to the phase expansion circuit 302, the sample hold circuits SHa1 to Sha6 are synchronized with the sample hold pulses SP1 to SP6 to extend the image signal VID by 6 times and divide it into 6 systems. Then, the signals VID1 to VID6 shown in the figure are generated. Further, the sample hold circuits SHa1 to SHa6 sample and hold the signals vid1 to vid6 in synchronization with the sample hold pulses SS to generate image signals VID1 to VID6.
[0071]
Now, an operation for canceling a ghost will be specifically described. FIG. 6 is a timing chart showing an operation from when the image data Da is supplied to when the phase development image signal VID3 is supplied to the data line 114c. In FIG. 6, in order to facilitate understanding, each data value is converted into an analog signal level and the delay time associated with the phase expansion is ignored. In this example, it is assumed that the image data Da has a data value corresponding to the intermediate level Vc in the periods t1 to t3, the black level Vb in the periods t4 to t14, and the intermediate level Vc in the periods t15 to t18.
The image data Da shown in FIG. 6A rises from the intermediate level Vc to the black level Vb at the start of the period t4, but is delayed by 6 dot clock cycles to become the image data Db, so that FIG. As shown, the image data Db rises from the intermediate level Vc to the black level Vb at the start of the period t10.
[0072]
As shown in FIG. 6C, the first difference data Ds1 becomes “0” in the period t1 to t3, becomes “Vb−Vc” in the period t4 to t9, becomes “0” in the period t10 to t14, and becomes the period t15. It is “− (Vb−Vc)” at t18. Further, since the first correction data Dh1 is obtained by multiplying the first difference data Ds1 by the coefficient K1, the data value changes as shown in FIG. In addition, since the corrected image data Dout is generated by adding the first correction data Dh1 to the image data Da, the data value becomes “Vc” in the period t1 to t3 as shown in FIG. In the period t4 to t9, “Vb + K1 (Vb−Vc)”, in the period t10 to t14 “Vb”, and in the period t15 to t18 “Vc−K1 (Vb−Vc)”.
[0073]
Next, since the phase development image signal VID3 is a signal obtained by sampling and holding the corrected image data Dout in the periods t3, t9, and t15, if the delay time required for the phase development is ignored (f) The phase development image signal VID3a shown in FIG. “VID3a” is a phase development image signal input to the image signal supply line L3, and “VID3b” is a phase development image signal supplied to the data line 114c via the sampling circuit.
[0074]
As shown in the figure, the phase development image signal VID3a in the period t7 to t12 corresponds to the image data Da in the period t9, but the signal level is larger by “K1 (Vb−Vc)” than the data value of the image data Da. It has become. The phase development image signal VID3c in the period t13 to t18 corresponds to the image data Da in the period t15, but the signal level is smaller by “K1 (Vb−Vc)” than the data value of the image data Da. Yes.
[0075]
When the phase development image signal VID3a is transmitted to the switch of the sampling circuit via the image signal supply line L3, the high frequency component is lost in the process, so the signal waveform of the phase development image signal VID3b is shown in FIG. As shown, the rising waveform and falling waveform are dull.
[0076]
Here, if the sampling signal SR shown in FIG. 11H is supplied to the gate electrode of the TFT constituting the switch, the switch is turned on during the period t7 to t12, and the phase development image signal VID3b is applied to the data line 114c. Is supplied, and the switch is turned off at the end time Tz1 of the period t12. Therefore, the voltage applied to data line 114c is determined by the signal level of phase development image signal VID3b at time Tz1.
[0077]
In this example, the signal level of the phase development image signal VID3a in the period t7 to t12 is “Vb + K1 (Vb−Vc)”. The signal level of the phase development image signal VID3b is “Vb”. In other words, at the end time Tz1 of the active period of the sampling signal SR, the value of the coefficient K1 is determined so as to obtain the voltage that should be originally applied. In this example, the case where the active period of the sampling signal SR starts from the start of the period t7 and ends at the end of the period t12 has been described as an example. However, the end time Tz1 may be any as long as it is within the range of the periods t7 to t12. The coefficient K1 may be determined according to the relative phase relationship between the active period of the sampling signal SR and the phase development image signals VID1 to VID6.
[0078]
As described above, in the present embodiment, since the ghost component is predicted based on the image data corresponding to the preceding and succeeding blocks and the image data corresponding to the block is corrected, it is possible to cancel the ghost. And the quality of the display image can be greatly improved.
[0079]
<2. Second Embodiment>
<2-1: Outline of liquid crystal display device>
In the liquid crystal display device of the first embodiment described above, the image signal supply is performed based on the image data Db (past) one unit time ago and the current image data Da before phase expansion in the ghost removal circuit 304. The waveform degradation due to the lines L1 to L6 is predicted, and the corrected image data Dout is generated by correcting the image data Da so that the original signal level is obtained at the end time Tz1 of the active period of the sampling signal SR. However, depending on the method of generating the sampling signal SR, the end time Tz1 may occur within the next unit time exceeding the current unit time. In such a case, the voltage applied to the data line 114 is affected by the future image data value. The second embodiment provides a liquid crystal display device that can predict and cancel a ghost component even in such a case.
[0080]
In the liquid crystal display device according to the second embodiment, a ghost removal circuit 305 is used instead of the ghost removal circuit 304, and the active period of the sampling signal SR is in the next unit time as well as the current unit time. Is the same as the liquid crystal display device of the first embodiment shown in FIG.
[0081]
<2-2: Ghost removal circuit>
FIG. 7 is a block diagram showing a main configuration of a ghost removal circuit used in the liquid crystal display device of the second embodiment. The ghost removal circuit 305 is provided with a second delay unit U2, a second difference calculation circuit 34, and a second coefficient circuit 35 in the previous stage of the ghost removal circuit 304 of the first embodiment.
[0082]
First, similarly to the first delay unit U1, the second delay unit U2 includes six latch circuits LAT1 to LAT6. The second delay unit U2 delays the image data Dc by one unit time (6 dot clock cycles) to generate the image data Da. Is generated. Here, if the image data Da is current, the image data Dc corresponds to data after one unit time, that is, future data.
[0083]
Next, the second difference calculation circuit 34 includes a subtracter, and subtracts the image data Db from the image data Da to generate second difference data Ds2. Further, the second coefficient circuit 35 includes a multiplier, and generates the second correction data Dh2 by multiplying the second coefficient K2 and the second difference data Ds2. In addition, the addition circuit 33 adds the image data Da, the first correction data Dh1, and the second correction data Dh2, and generates corrected image data Dout.
[0084]
According to the ghost removal circuit 305, the current image data Da is corrected using not only the past image data Db but also the future image data Dc.
[0085]
<2-3: Operation of liquid crystal display device>
Next, the operation of the liquid crystal display device will be described in order. First, the operation from when the image data Dc is input until the corrected image data Dout is generated by the ghost removal circuit 305 will be described. FIG. 8 is a timing chart for explaining the operation of the ghost removal circuit 305.
[0086]
First, when the image data Dc is supplied to the ghost removal circuit 305, the second delay unit U2 and the first delay unit U1 delay the image data Dc by one unit time (6-dot period) as image data Da and Db. Is output.
[0087]
As a result, image data Db and Dc of about one unit time are obtained for the image data Da. For example, paying attention to the period Tx shown in FIG. 8, the image data Da is “D2, n”, which corresponds to the data line 114b of the block Bn. On the other hand, the image data Dc is “D2, n + 1” and corresponds to the data line 114b of the block Bn + 1.
[0088]
Thereafter, when the second difference circuit 34 subtracts the image data Dc from the image data Da to generate the second difference data Ds2, the second coefficient circuit 32 multiplies the second difference data Ds2 by the coefficient K2 to perform the second correction. Data Dh2 is generated. Therefore, in the period Tx, the second correction data Dh2 is “K2 (D2, n−D2, n + 1)”. On the other hand, the first correction data Dh1 is “K1 (D2, n−D2, n−1)” as described in the first embodiment.
[0089]
Further, since the corrected image data Dout is obtained by adding the first correction data Dh1, the second correction data Dh2, and the image data Da, “D2, n + K1 (D2, n−D2, n−1) + K2 (D2 , n−D2, n + 1) ”. The operation of phase-developing the image signal VID obtained by AD converting the corrected image data Dout is the same as that in the first embodiment shown in FIG.
[0090]
Now, an operation for canceling a ghost will be specifically described. FIG. 9 is a timing chart showing an operation from when the image data Dc is supplied until the phase development image signal VID3 is output to the data line 114c.
[0091]
The image data Dc shown in FIG. 9A is delayed by 6 dot clock cycles (one unit time) to become the image data Da shown in FIG. 9B, and further delayed by 6 dot clock cycles (c) in FIG. The image data Db shown in FIG.
[0092]
Here, since the second difference data Ds2 is obtained by subtracting the image data Dc from the image data Da, as shown in FIG. 5E, it becomes “− (Vb−Vc)” during the period t1 to t3. It becomes “0” from t4 to t8, becomes “Vb−Vc” during the period t9 to t14, and becomes “0” during the period t15 to t18. Further, since the second correction data Dh2 is obtained by multiplying the second difference data Ds2 by the coefficient K2, the data value changes as shown in FIG. Since the first difference data Ds1 and the first correction data Dh1 shown in FIGS. 4D and 4F are the same as those in the first embodiment, no particular explanation is required.
[0093]
In addition, since the corrected image data Dout is generated by adding the first correction data Dh1 and the second correction data to the image data Da, the data value thereof is a period t1 as shown in FIG. “Vc−K2 (Vb−Vc)” at time t3, “Vb + K1 (Vb−Vc)” at time t4 to t8, “Vb + K1 (Vb−Vc) + K2 (Vb−Vc)” at time t9, It becomes “Vb + K2 (Vb−Vc)” from t10 to t14, and “Vc−K1 (Vb−Vc)” from time t15 to t18.
[0094]
Next, since the phase development image signal VID3 is obtained by sampling and holding the corrected image data Dout in the periods t3, t9, and t15, if the delay time required for the phase development is ignored, A phase development image signal VID3a shown in i) is obtained.
[0095]
When this phase development image signal VID3a is transmitted to the switch of the sampling circuit via the image signal supply line L3, the high frequency component is lost in the process, so the signal waveform of the phase development image signal VID3b is shown in FIG. As shown, the rising waveform and falling waveform are dull.
[0096]
Here, if the sampling signal SR shown in FIG. 5K is supplied to the gate electrode of the TFT constituting the switch, the switch is turned on during the period t7 to t13, and the phase development image signal VID3b is applied to the data line 114c. Is supplied, and the switch is turned off at the end time Tz2 of the period t13. Therefore, the voltage applied to data line 114c is determined by the signal level of phase development image signal VID3b at time Tz2.
[0097]
In this example, the signal level of the phase development image signal VID3a in the period t7 to t12 is “Vb + K1 (Vb−Vc) + K2 (Vb−Vc)”. That is, the signal level is increased by “K2 (Vb−Vc)” compared to the first embodiment described above. This is because the end time Tz2 of the active period of the sampling signal SR occurs after the period t7 to t12, so that it is necessary to consider the data value of the future image data Dc.
[0098]
As in the first embodiment, the phase development image signal VID3a has a signal level “Vb + K1 (Vb−Vc)” and is supplied to the data line 114c by the integration effect of the image signal supply line L3. If the signal level of VID3b becomes “Vb” at the end time Tz1 of the period t12 as shown in FIG. 6G, the signal level falls below “Vb” at the end time Tz2 of the period t13. Therefore, it deviates from a desired signal level.
[0099]
However, in the present embodiment, the current image data Da is corrected by the second correction data Dh2 that reflects the influence of the future image data Dc. Therefore, at the time Tz2 as shown in FIG. The signal level of the phase development image signal VID3b becomes “Vb”. In other words, the coefficient K2 is determined so as to compensate for the change in the signal waveform from the start of the period t13 to the time Tz.
[0100]
Thus, in the present embodiment, since the ghost component is predicted and the current image data Da is corrected based on the current, past, and future image data Da, Db, and Dc, the image signal supply line is corrected. Ghosts resulting from L1 to L6 equivalently constituting a low-pass filter can be canceled, and the quality of the display image can be greatly improved.
[0101]
<3. Third Embodiment>
<3-1: Outline of liquid crystal display device>
Next, a liquid crystal display device according to a third embodiment will be described. This liquid crystal display device is configured similarly to the liquid crystal display device of the first embodiment shown in FIG. 1 except that a ghost removal circuit 306 is used instead of the ghost removal circuit 304.
[0102]
The ghost removal circuit 306 of the third embodiment is used to remove ghosts generated due to the coupling of the parasitic capacitances of the data lines 114a to 114f. FIG. 10 is a block diagram showing a configuration of a ghost removal circuit according to the second embodiment.
[0103]
As shown in the figure, the ghost elimination circuit 306 includes a first delay unit U1, a subtraction circuit 41, an averaging circuit 42, a coefficient circuit 43, a latch circuit 44, and an addition circuit 45.
[0104]
First, the first delay unit U1 is used to generate image data Db delayed by one block period with respect to the image data Da. If the image data Da is current data, the image data Db corresponds to past data one unit time ago.
Next, the subtraction circuit 41 subtracts the current image data Da from the past image data Db to generate difference image data Ds.
[0105]
Next, the averaging circuit 42 is configured to average the difference image data Ds for each block and generate the averaged image data Dw. The averaging circuit 42 includes an adding circuit 421 and a latch circuit 422. The latch circuit 422 latches the output signal of the adder circuit 421 based on the dot clock signal DCLK. On the other hand, the difference image data Ds is supplied to one input terminal of the adder circuit 421, and the output data of the latch circuit 422 is fed back to the other input terminal. Therefore, the adder circuit 421 and the latch circuit 422 function as a cumulative adder circuit. Further, a reset signal RS having a 6-dot clock cycle is supplied to the reset terminal R of the latch circuit 422. Therefore, the difference image data Ds is cumulatively added every unit time.
[0106]
The averaging circuit 42 further includes a division circuit 423 and a latch circuit 424. The division circuit 423 divides the data obtained by accumulating the difference image data Ds in units of blocks by “6” (number of phase expansions), and the latch circuit 424 activates the output data of the division circuit 423 every unit time. Is latched by the block clock signal BCLK and output as averaged image data Dw. The block clock signal BCLK is generated by the timing circuit 200 shown in FIG.
[0107]
Next, the coefficient circuit 43 has a multiplier and multiplies the averaged image data Dw by a coefficient K and outputs the result.
[0108]
Next, the latch circuit 44 is used for time adjustment, latches the output data of the coefficient circuit 43, and outputs it as correction data Dh.
[0109]
Next, the addition circuit 45 adds the image data Dc and the correction data Dh and outputs the result as corrected image data Dout.
[0110]
The other configuration is the same as that of the conventional liquid crystal display device, and therefore no further description is required.
[0111]
<2-2: Operation of Second Embodiment>
Next, the operation of the above ghost removal circuit 306 will be described. FIG. 11 is a timing chart for explaining the operation of the ghost removal circuit 306. In this figure, the subscript X in the case of DX, Y represents the number of the data line 114 corresponding to one block counted in the scanning direction in the block, while the subscript Y represents what. Let it be the th block. For example, D1, n + 1 corresponds to the first data line 114a in the block and represents that the block is the (n + 1) th data line.
[0112]
As shown in this figure, the image data Db is obtained by delaying the image data Da by one unit time (6 dot clock cycles). When these image data Da and Db are supplied to the subtracting circuit 41, the subtracting circuit 41 subtracts the image data Da (present) from the image data Db (previous: one block before) to generate difference image data Ds. To do. For example, in the period Ty shown in the figure, the image data Db is “D2, n”, and the image data Da is “D2, n−1”, so that the difference image data Ds is “D2, n−D2, n−”. 1 ”.
[0113]
As shown in FIG. 16, since the data lines 114a to 114f in one block are capacitively coupled, when the image signal VID applied to any one of the data lines 114 changes, the voltage Vx is changed. Change. As a result, the potentials of the other data lines 114 change, affecting the entire block. As shown in FIG. 14, when the image signal VID3 supplied to the data line 114c changes from the black level to the intermediate level, the voltage Vx is given as a differentiation of the image signal VID3. Here, the amount of change in the voltage Vx is proportional to the voltage value obtained by subtracting the image signal VID one block before (past) from the current image signal VID.
[0114]
In the present embodiment, the image data is corrected so as to cancel the change in the voltage Vx. For this purpose, the following conditions are required. First, it is necessary to generate the image signal VID so that a voltage in the direction opposite to the direction of change of the voltage Vx can be applied to the data line 114. For this reason, it is necessary to correct the current image data based on the data value obtained by subtracting the current image data value from the image data value one block before (past). If the image data Da is current image data, the image data Db is image data one block before (past). Therefore, it is necessary to correct based on the above-described difference image data Ds.
[0115]
Second, since a change in the image signal VID applied to a certain data line 114 in one block affects the potential of another data line 114, the difference image data Ds is averaged in the block, and as a result. It is necessary to correct based on The averaging circuit 42 is used to satisfy the second condition.
[0116]
Since the difference image data Ds is cumulatively added by the addition circuit 421 and the latch circuit 422 in the averaging circuit 42, the output data of the latch circuit 422 corresponding to the data line 114f selected last in each block is The difference image data Ds is accumulated in the block. For example, in the period from time t10 to time t12, the output data of the latch circuit 422 is Ds1, n-1 + Ds2, n-1 + ... Ds6, n-1.
[0117]
The output data of the latch circuit 422 is divided by the division circuit 423, and the latch circuit 424 latches the division result based on the block clock signal BCLK. Therefore, before the output data of the latch circuit 422 is reset, 424 generates averaged image data Dw. In the example shown in the figure, when the block clock signal BCLK rises from low level to high level at time t11, the latch circuit 424 generates averaged image data Dwn-1 in synchronization with the rising edge. . After this, when the time t12 is reached, the reset signal RS becomes active (high level), so that the output data of the latch circuit 422 is reset and prepared for accumulation of the difference image data Ds of the next block.
[0118]
Then, when the averaged image data Dw is supplied to the coefficient circuit 43, the averaged image data Dw is multiplied by a coefficient K to generate correction data Dh. However, the correction data Dh is out of phase with the image data Db. Therefore, the latch circuit 44 latches the correction data Dh output from the coefficient circuit 43 with the dot clock signal DCLK, and matches the phase of the correction data Dh with the phase of the image data Db. Thereafter, the adder circuit 45 generates corrected image data Dout by adding the image data Db and the correction data Dh.
[0119]
As described above, according to the present embodiment, the second ghost component generated due to the coupling of the parasitic capacitances Ca to Cf of the data lines 114a to 114f of one block is predicted in advance for each block. Since the corrected data Dh is generated and the image data Db is corrected based on the corrected data Dh, the second ghost can be canceled. As a result, the quality of the display image can be greatly improved.
[0120]
<4. Modification>
Next, modified examples of the above-described embodiments will be described.
(1) In each of the embodiments described above, the D / A converter 301 is provided between the ghost elimination circuits 304 to 306 and the phase expansion circuit 302. However, the phase expansion circuit 302 and the amplification / inversion circuit 303 One of them may be constituted by a digital circuit, and a D / A converter 301 may be provided at the output thereof.
[0121]
(2) In each of the embodiments described above, the phase expansion circuit 302 includes the first sample hold unit USa and the second sample hold unit USb shown in FIG. 3, and the phase of the signals vid1 to vid6 by the second sample hold unit USb. However, the second sample hold unit USb may be omitted. In this case, the signals vid1 to vid6 (see FIG. 5) whose phases are shifted every dot clock cycle may be output as the phase developed image signals VID1 to VID6.
[0122]
<5. Application example>
Next, some examples in which the liquid crystal display device described in each embodiment described above is used in an electronic device will be described.
[0123]
<5-1: Projector>
First, a projector using this liquid crystal display device as a light valve will be described. FIG. 12 is a plan view showing a configuration example of the projector.
[0124]
As shown in the figure, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.
[0125]
The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal display panel 100 described above, and are driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). Now, the light modulated by these liquid crystal panels is incident on the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.
Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter on the counter substrate.
[0126]
As described above, since the ghost removal circuit 304 or 305 is used in the image processing circuit 300 of the liquid crystal display device, the first or second ghost can be canceled and the quality of the display image can be greatly improved. Can do.
[0127]
<5-2: Mobile computer>
Next, an example in which this liquid crystal display device is applied to a mobile computer will be described. FIG. 13 is a front view showing the configuration of the computer. In the figure, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display 1206. The liquid crystal display 1206 is configured by adding a backlight to the back surface of the liquid crystal display panel 100 described above.
[0128]
<5-3: Mobile phone>
Further, an example in which the liquid crystal display device is applied to a mobile phone will be described. FIG. 14 is a perspective view showing the configuration of this mobile phone. In the figure, a cellular phone 1300 includes a reflective liquid crystal panel 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal panel 1005, a front light is provided on the front surface thereof as necessary.
[0129]
In addition to the electronic devices described with reference to FIGS. 12 to 14, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Stations, videophones, POS terminals, devices with touch panels, etc. Needless to say, the present invention can be applied to these various electronic devices.
[0130]
【The invention's effect】
As described above, according to the present invention, each image signal that is divided into a plurality of systems and is time-axis extended and maintains a constant signal level per unit time is supplied to each data line at a predetermined timing. In this case, since the ghost appearing in the display image is predicted in advance and the image data is corrected so as to cancel it, the quality of the display image can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a ghost removal circuit in the liquid crystal display device.
FIG. 3 is a block diagram showing a configuration of a phase expansion circuit in the liquid crystal display device.
FIG. 4 is a timing chart showing the operation of the ghost removal circuit.
FIG. 5 is a timing chart showing the operation of the phase expansion circuit in the liquid crystal display device.
FIG. 6 is a timing chart showing an operation from when the image data Da is supplied to when the phase development image signal VID3 is supplied to the data line in the ghost removal circuit.
FIG. 7 is a block diagram showing a main configuration of a ghost removal circuit used in a liquid crystal display device according to a second embodiment of the present invention.
FIG. 8 is a timing chart showing the operation of the ghost removal circuit.
FIG. 9 is a timing chart showing an operation from when image data Da is supplied to when a phase development image signal VID3 is supplied to a data line in the ghost removal circuit.
FIG. 10 is a block diagram showing a main configuration of a ghost removal circuit used in a liquid crystal display device according to a third embodiment of the present invention.
FIG. 11 is a timing chart showing the operation of the ghost removal circuit.
FIG. 12 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which a liquid crystal display device is applied.
FIG. 13 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which a liquid crystal display device is applied.
FIG. 14 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.
FIG. 15 is a block diagram showing an overall configuration of a conventional liquid crystal display device.
FIG. 16 is a block diagram showing an electrical configuration of a liquid crystal display panel in a conventional liquid crystal display device.
FIG. 17 is a timing chart showing the operation of a conventional liquid crystal display device.
FIG. 18 is an explanatory diagram showing an example of a ghost.
FIG. 19 is a circuit diagram showing an equivalent circuit of each data line in a certain block.
FIG. 20 is a waveform diagram showing a relationship between an image signal and a voltage at a common connection point of each parasitic capacitance.
FIG. 21 is an explanatory diagram showing an example of a ghost.
[Explanation of symbols]
31, 34... First difference calculation circuit, second difference calculation circuit
32, 35... First coefficient circuit, second coefficient circuit
33 …… Adder circuit
41 …… Subtraction circuit (difference circuit)
42 …… Averaging circuit
43 …… Coefficient circuit (coefficient part)
45 …… Adder circuit (adder)
100 …… LCD panel
112 ... Scanning line
114a to 114f ...... data line
116 …… TFT
118 …… Pixel electrode
300 …… Image processing circuit
304 to 306 ... Ghost removal circuit
302 …… Phase expansion circuit
Ds, Ds1, Ds2... Difference image data, first difference image data, second difference image data
Dh, Dh1, Dh2: Correction data, first correction data, second correction data
Dw: Averaged image data
Dout …… corrected image data
Da, Db, Dc: Image data
U1, U2... First and second delay units (delay circuits)
K1, K2 ... 1st coefficient, 2nd coefficient

Claims (7)

A plurality of scanning lines, a plurality of data lines, wherein a transistor and a pixel electrode provided corresponding to intersections of the data lines and the scan lines, the extension time axis while being divided into a plurality of systems units An image processing circuit used in an electro-optical device that supplies each image signal that maintains a constant signal level every time to each data line at a predetermined timing,
A first delay circuit that delays image data supplied from outside by a unit time of the image signal and outputs the delayed image data as first delayed image data;
A second delay circuit that delays the first delayed image data by a unit time of the image signal and outputs the delayed image data as second delayed image data;
A first difference circuit that generates a difference between the first delay image data and the second delay image data as first difference image data;
A first multiplier for generating first correction data by multiplying the first difference image data by a first coefficient;
A second difference circuit that generates a difference between the first delayed image data and the image data as second difference image data;
A second multiplication circuit for generating second correction data by multiplying the second difference image data by a second coefficient;
An image processing circuit comprising: a combining circuit that combines the first delayed image data, the first correction data, and the second correction data to generate corrected image data. The electro-optical device includes a plurality of switch elements that sample the image signals according to a sampling signal and supply the image signals to the data lines, and image signal supply lines that supply the image signals to the plurality of switch elements. And
The image processing circuit according to claim 1, wherein the first coefficient and the second coefficient are determined according to characteristics of a low-pass filter equivalently configured by the image signal supply lines. The electro-optical device includes a plurality of switch elements that sample the image signals according to a sampling signal and supply the image signals to the data lines, and image signal supply lines that supply the image signals to the plurality of switch elements. And
The first coefficient and the second coefficient are respectively set so that a signal level corresponding to a predetermined image signal supplied to the data line reaches a predetermined value at the end of the active period of the sampling signal. A coefficient multiplied by the correction data and the second correction data,
The first multiplication circuit is formed by multiplying the first difference image data by the constant first coefficient,
The image processing circuit according to claim 1, wherein the second multiplication circuit is obtained by multiplying the second difference image data by the constant second coefficient. The image processing circuit according to claim 3 , wherein an active period of the sampling signal starts from a current unit time of the image signal and ends within a next unit time. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines are divided into a plurality of systems and extended in time axis. An image data processing method used in an electro-optical device that supplies each image signal that maintains a constant signal level every time to each data line at a predetermined timing,
Image data supplied from the outside is set as future image data, which is sequentially delayed by the unit time to generate current image data and past image data,
Generating first correction data based on a difference data value between the current image data and the past image data;
Generating second correction data based on a difference data value between the current image data and the future image data;
An image data processing method, wherein corrected image data is generated by combining the current image data, the first correction data, and the second correction data.   An electro-optical device comprising the image processing circuit according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 6.

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