JP4050163B2 - Manufacturing method of substrate with through electrode - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a substrate with a through electrode used for a high-density three-dimensional mounting type semiconductor device or the like.
[0002]
[Prior art]
In order to stack semiconductor devices such as IC chips three-dimensionally and perform high-density wiring, it is indispensable to form elements on both the front and back surfaces of a substrate such as silicon and wire them. A through electrode connecting the back surface is required.
[0003]
As a method for forming a through electrode on a substrate, conventionally, a resist is applied to the surface of the substrate, a desired electrode pattern is transferred onto the resist by a lithography technique, and then a non-through fine hole is formed in an electrode portion of the substrate by selective etching. In general, an insulating layer is formed on the inner wall of the non-penetrating fine hole, a metal is filled in the non-penetrating fine hole, and the back surface of the substrate is polished to form a through electrode.
[0004]
Below, the manufacturing method of the board | substrate with a penetration electrode performed conventionally by FIG. 2 is demonstrated. FIG. 2A is a plan view of a substrate with a through electrode. Reference numeral 9 denotes a substrate, and reference numeral 10 denotes a through electrode. FIG. 2B shows the manufacturing procedure of the through electrode in the cross section in the AA direction of FIG.
[0005]
In FIG. 2B, reference numeral 11 is a substrate, reference numeral 11 a is a front surface of the substrate 11, and reference numeral 11 b is a back surface of the substrate 11. There is no distinction between the front and back surfaces of the substrate before the surface processing, and in this specification, the first surface to be drilled to form the micropores is the front surface, and the opposite surface is the back surface. Reference numeral 13 is a resist, reference numeral 12 is a front surface insulating layer, reference numeral 14 is a rear surface insulating layer, reference numeral 15 is a blind via hole (fine hole for a non-through electrode), reference numeral 16 is an inner wall insulating layer, and reference numeral 17 is The conductive layer, 18 is a contact hole.
[0006]
In step 11, the front surface 11a and the back surface 11b of the substrate are mirror-polished, then a surface insulating layer 12 is formed on the substrate surface 11a with an oxide film or the like, a resist is applied to the surface of the surface insulating layer 12, and an electrode pattern is formed. After the transfer by lithography, the surface insulating layer 12 and the resist 13 at portions to be through electrodes are removed by etching to partially expose the substrate surface 11a.
[0007]
Although the surface insulating layer 12 is formed by a thermal oxidation method or the like, the back surface insulating layer 14 may be formed at the same time. The front surface insulating layer 12 and the back surface insulating layer 14 have both a function as a substrate surface protection and a function of the insulating layer after electrode formation. The back insulating layer 14 is a flat layer that is not patterned in the process 11.
[0008]
In step 12, a blind via hole 15 that is a non-penetrating fine hole is formed on the substrate surface 11a, which is an electrode portion exposed by electrode pattern formation, using an etching technique. The shape, area, and number of blind via holes can be arbitrarily set by electrode patterns. The depth of the blind via hole 15 is usually 70 to 90% of the thickness of the substrate 11.
[0009]
In step 13, a wall insulating layer 16 such as an oxide film is formed on the inner wall of the formed blind via hole 15. Next, in step 14, the blind via hole 15 in which the wall surface insulating layer 16 is formed is filled with a metal for the through electrode, and the conductive layer 17 is formed.
[0010]
In step 15, a part of the substrate 11 is removed by a technique such as polishing on the substrate back surface 11b to expose a metal portion to be an electrode. In this case, as will be described later, the depth of the plurality of blind via holes on the substrate 11 varies in the radial direction of the substrate 11 in the drilling by etching.
[0011]
Therefore, in order to form through-holes all over the entire back surface 11b of the substrate by polishing after the formation of the blind via hole 15, the shallowest depth of the blind via hole 15 is set as the polishing reference position. It is necessary to polish to the polishing reference position. Further, if the back insulating layer 14 is formed, it is removed in this polishing step.
[0012]
In step 16, a back surface insulating layer 14 is formed on the entire back surface for protection and insulation of the substrate back surface 11b, and the metal portion is exposed by selectively removing the back surface insulating layer 14 at the electrode site using lithography and etching techniques. Thus, a contact hole (conductive fine hole) 18 is produced.
[0013]
The reason for producing the through electrode by forming the blind via hole without filling the through electrode first, filling the electrode metal, and exposing the electrode on the back surface by etching or polishing is as follows. In order to fix the substrate to the pedestal when etching or other processing is usually performed by vacuum suction, if there are through-holes, it is inconvenient for fixing the substrate, and etching, cleaning, etc. are performed on the substrate. When performing the above, gas, solution, etc. leaked from the through micropores to the back surface, and the substrate surface and pedestal were contaminated and eroded.
[0014]
[Problems to be solved by the invention]
The conventional manufacturing method has the following problems. That is, when an etching method is used when forming a blind via hole, a phenomenon occurs in which the etching depth, that is, the depth of the blind via hole varies depending on the drilling position in the radial direction of the substrate. This is reflected in the variation in the finished thickness of the substrate with electrodes.
[0015]
In RIE (Reactive Ion Etching), the etching depth is controlled by etching time, RF power, and etching gas flow rate, and in PAECE (Photo Assisted E1 Electrochemical 1 etching), it is controlled by etching time, etchant concentration, applied voltage, irradiation light amount, etc. Is done. When these parameters vary, the polishing reference position varies for each substrate to be etched, and as a result, the finished thickness of the substrate after polishing varies.
[0016]
Even when the same substrate is used, when a commercially available RIE apparatus is used, the etching rate at the central portion of the substrate is slower than that at the outer peripheral portion. As a result, the blind via hole at the outer peripheral portion is at the center. It is etched deeper than the part.
[0017]
In a commercially available RIE apparatus, a reaction gas is introduced into the reaction vessel from above the substrate fixed to the pedestal in the reaction vessel, and the gas that has become a reactive species such as radicals and ions by applying a high-frequency electric field is the substrate surface. In general, the structure is such that the substrate surface is etched from the exhaust port installed below the pedestal after being etched along the substrate surface while flowing along the substrate surface from the center of the substrate toward the outer periphery. Is.
[0018]
In such an apparatus structure, it is considered that the etching progresses quickly at the outer peripheral portion of the substrate because there are more gases, radicals, and ions that contribute to the etching around the outer peripheral portion of the substrate while the etching is in progress. .
[0019]
The difference in etching depth between the central portion and the outer peripheral portion reaches 5 to 10% of the etching depth, and is several tens of μm or more. For example, if the substrate thickness is 600 μm and the average depth of the blind via hole is 480 μm, which is 80% of the substrate thickness, the depth of the blind via hole at the center and the outer periphery of the substrate The difference is 24 to 48 μm.
[0020]
By the way, in order to expose all the brand beer holes collectively by polishing, the depth of the polishing reference position, that is, the depth of the shallowest blind via hole is accurately measured, from the back of the substrate to the polishing reference position, It is necessary to remove an amount of several tens of μm.
[0021]
However, in the depth measurement function of a laser microscope usually used for measuring such micropores, when the hole diameter is 30 μm or less, the measurement becomes difficult when the depth is 200 μm or more, and the blind is usually 250 μm or more. In the measurement of the via hole depth, sufficient accuracy has not been obtained.
[0022]
Therefore, there may be excess or deficiency of the polishing amount in backside polishing, and if there are unpenetrated fine holes remaining after polishing, repolishing is performed, and the polishing amount is too large, deviating from the allowable range of the substrate thickness. Some cases occurred. As described above, in the conventional method, the finished thickness after forming the through electrode may vary from substrate to substrate by about several tens of μm. For LSI substrates that require high accuracy and reproducibility in the substrate thickness. It was not desirable.
[0023]
Also, as shown in steps 15 and 16 of FIG. 2B, the back insulating layer 14 formed on the substrate back surface 11b in the step 11 is removed by the back surface polishing in the step 15, so It was necessary to newly form the back surface insulating layer 14 after fabrication.
[0024]
For example, Japanese Patent Application No. 2002-270563 filed earlier by the present applicant is known as a prior art document relating to a method of manufacturing such a substrate with a through electrode. (Filed on September 17, 2002)
[0025]
[Means for Solving the Problems]
The invention according to claim 1 is a method for manufacturing a substrate with a through electrode , wherein through holes are formed in an electrode portion on a silicon substrate by a method selected from ICP-RIE, PAECE, laser method, or micro drill method. After forming, a bonding substrate is bonded to the back surface side of the silicon substrate via a back insulating layer, and then the inner wall of the through microhole is selected from a thermal oxidation method, a PE-CVD method, or an anodic oxidation method Then, after forming an insulating layer, filling the fine holes with a metal to form a conductive layer, the bonding substrate is removed.
[0026]
The invention according to claim 2 is a method of manufacturing a substrate with a through electrode , wherein through holes are formed in an electrode portion on a silicon substrate by a method selected from ICP-RIE, PAECE, laser method, or micro drill method. After forming, a bonding substrate, which is a glass substrate, is bonded to the silicon substrate, and then an insulating layer is formed on the inner wall of the through fine hole by a method selected from a thermal oxidation method, a PE-CVD method, or an anodic oxidation method. Forming a conductive layer by filling the fine holes with metal, and then removing the bonding substrate so that a part of the substrate remains on the silicon substrate. Is the method.
[0027]
According to a third aspect of the present invention, in the first aspect, the bonding substrate is a silicon substrate or a glass substrate, and is bonded to the silicon substrate by thermal bonding or resin. A method for manufacturing a substrate.
The invention according to claim 4 is the method for manufacturing a substrate with a through electrode according to claim 1, wherein the back surface insulating layer is an insulating layer formed in advance on the silicon substrate before bonding.
The invention according to claim 5 is the method for manufacturing a substrate with a through electrode according to claim 1, wherein the back surface insulating layer is an insulating layer formed on the bonding substrate before bonding.
The invention according to claim 6 is the method according to claim 2, wherein the bonding substrate is a glass substrate and bonded to the silicon substrate by anodic bonding or resin. It is.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
The present invention solves the problems of the conventional method for manufacturing a substrate with a through electrode, and after forming a through microhole, a new silicon substrate or a glass substrate is joined, and then the electrode conductor is made into a microhole. A through electrode manufacturing method characterized by performing a filling process. The manufacturing method of the board | substrate with a penetration electrode concerning this invention is demonstrated using FIG.
[0029]
FIG. 1 is a view showing a cross section of a substrate. In FIG. 1, reference numeral 1 is a substrate, reference numeral 1 a is a front surface of the substrate 1, and reference numeral 1 b is a back surface of the substrate 1. The front surface and the back surface are as described in the conventional method. Reference numeral 2 is a front surface insulating layer, reference numeral 3 is a resist, reference numeral 4 is a back surface insulating layer, reference numeral 5 is a through hole, reference numeral 6 is a bonding substrate, reference numeral 7 is a wall insulating layer, reference numeral 8 is a conductive layer, reference numeral 9 is a contact Hall.
[0030]
A method for manufacturing a substrate with through electrodes according to the present invention will be described below with reference to FIG. In the following description, the substrate 1 will be described using a silicon substrate as an example, but the material is not limited to silicon. In step 1, after the surface insulating layer 2 is formed on the surface 1a of the substrate 1, a resist 3 is applied to the surface insulating layer 2, and the electrode pattern is transferred onto the resist by lithography.
[0031]
The thickness of the substrate is, for example, about 300 to 600 μm. The surface insulating layer 2, the oxide film formed by thermal oxidation (Si0 ₂₎ or the like is used. The diameter of the through electrode is usually smaller than the substrate thickness, for example, about 5 to 200 μm. Further, the opening shape, arrangement, and number of through electrodes can be arbitrarily designed according to the electrode pattern to be formed.
[0032]
Next, the surface insulating layer 2 and the resist 3 at the electrode site are removed by wet etching or the like to partially expose the substrate surface 1a. When the connection substrate 6 is silicon, the back surface insulating layer 4 may be formed on the substrate back surface 1b.
[0033]
In step 2, the electrode portion of the substrate surface 1 a is drilled by an etching technique to form the through minute hole 5. As a method of forming blind via holes and through-holes having a high aspect ratio (ratio of the hole diameter and depth of fine holes) having a hole diameter of several tens of μm and a depth of several hundreds of μm or more, ICP -RIE (Inductively Coupled Plasma-Reactive Ion Etching), PAECE, laser method, micro drill method, etc., but the micro drill method is inefficient in order to drill many blind via holes at once, Since laser drilling devices are expensive, ICP-RIE is often used to form microholes for electrodes on substrates such as silicon.
[0034]
Further, in the drilling of the substrate, since the etching depth reaches several hundred μm, it is necessary to increase the selection ratio (etching ratio) between silicon and the etching mask and use a thick etching mask. Therefore, the two layers of the resist 3 and the surface insulating layer 2 used for patterning the surface insulating layer 2 in step 1 are often used as an etching mask for forming the through hole 5 in step 2.
[0035]
Of course, the structure of the etching mask used for forming the through hole is not limited to that illustrated in FIG. 1, and a resist such as a photoresist, an oxide film, a nitride film, or the like can be used alone as an etching mask. is there.
[0036]
In etching, the surface insulating layer 2 is Si0 _2, when the substrate 1 is silicon, silicon and Si0 ₂ selection ratio in ICP-RIE (etching rate - DOO ratio) is 1: 100 to 200, The selection ratio between silicon and photoresist is about 1: 50-100.
[0037]
In order to form through-holes in a silicon substrate having a thickness of several hundred μm or more, the thicknesses of the resist 3 and the surface insulating layer 2 may be appropriately determined from the thickness of the substrate 1 and the value of the selection ratio. .
[0038]
Further, as already described, since there is a difference in the etching rate between the central part and the peripheral part of the substrate 1, the etching mask corresponding to the etching time required for the central part having a slow etching rate to penetrate therethrough is used. It is necessary to design the thickness.
[0039]
In order to function oxide film such as Si0 ₂ as the insulating layer, it is necessary thickness of about 0.5 to 3 [mu] m, when the through micropores produced finished, Si0 ₂ film is etched the thickness Even if it does not reach this limit, it is possible to form an insulating layer on the fine hole wall surface and the substrate surface at the same time if the substrate surface 1a is exposed so as to be subjected to the film forming action at the same time in the next step of forming the inner wall edge layer. it can.
[0040]
By forming the through-holes 5 in this manner, it is possible to confirm that all the fine holes on the substrate have been visually etched and penetrated, so that the thickness of the substrate 1 varies due to excessive etching. There is nothing.
[0041]
Next, in step 3, the bonding substrate 6 is bonded to the substrate 1 in which the through micro holes 5 have been formed. As the bonding substrate 6, a silicon substrate or a glass substrate is used. If the resist 3 remains before joining, it is desirable to remove it. The bonding method of the bonding substrate 6 and the removal method after bonding and filling with the electrode metal differ depending on the material of the bonding substrate 6.
[0042]
First, the case where the bonding substrate 6 is a silicon substrate will be described. The silicon substrate preferably has a thickness of about 100 to 300 μm, for example. In Step 1, when the back surface insulating layer 4 is not formed, an insulating layer such as an oxide film may be formed on the bonding surface of the bonding substrate 6. As a method for bonding the substrates, thermal bonding or bonding with a resin such as a photoresist is used. These joining methods will be described below.
[0043]
In thermal bonding, the substrate 1 and the bonding substrate 5 on which the through electrode is formed are washed with a mixed aqueous solution of ammonia and hydrogen peroxide to perform a hydrophilic treatment, and then the two are bonded together. Thereafter, the bonding is completed by heat treatment in an oxygen atmosphere, a nitrogen atmosphere, or a mixed atmosphere of nitrogen and oxygen. The temperature in the heat treatment is desirably 800 to 1200 ° C., and the time is preferably 30 minutes to 12 hours. In this case, during the heat treatment, an oxide film is formed on the surface of the silicon substrate 1 and the inner wall of the through microhole 5 by a thermal oxidation reaction, so that it is not necessary to form the wall surface insulating layer 7 in step 4 described later.
[0044]
Moreover, in joining by resin, a photoresist is uniformly apply | coated to the single side | surface of the board | substrate 5 for joining with the thickness of about 0.5-50 micrometers, for example, and it is affixed on the board | substrate 1. FIG. Thereafter, the bonding of both substrates is completed by heat treatment. The temperature is preferably 80 to 200 ° C. and the time is preferably 30 minutes to 2 hours.
[0045]
Next, joining in the field where the joining substrate 6 is a glass substrate will be described. In this case, the thickness of the bonding substrate 6 is preferably 100 to 500 μm. As a bonding method, anodic bonding or resin bonding is performed. The joining method will be described below.
[0046]
In the case of the anodic bonding method, after the through-hole 5 is formed, the substrate 1 and the bonding substrate 6 made of glass are bonded together, the substrate 1 is connected to the anode side, the bonding substrate 6 is connected to the cathode side, and a voltage is applied. Bonding is performed by performing heat treatment. The applied voltage is preferably 600 V, the heating temperature is 400 to 500 ° C., and the heating time is preferably 1 to 2 hours. The bonding method using resin is the same when the bonding substrate 6 is silicon.
[0047]
In step 4, the wall surface insulating layer 7 is formed on the inner wall of the through-hole 5. The wall insulating layer 7 is an oxide film such as SiO ₂ , and the formation method is a thermal oxidation method, a PE-CVD method, an anodization method, or the like. This step is not necessary when thermal bonding is performed in the substrate bonding.
[0048]
In step 5, the through-hole 5 in which the wall surface insulating layer 7 is formed is filled with a metal for the through-electrode to form the conductive layer 7. As a filling method, a molten metal suction method, a printing method, a CVD method, or the like is used.
[0049]
The molten metal suction method is a method used when a high-aspect-ratio fine hole is filled with a metal. First, a substrate in which a fine hole is formed is inserted into a heat-melted metal in a vacuum-tight airtight container. Next, by pressurizing the inside of the container, the molten metal is filled into the inside of the fine hole by utilizing the pressure difference between the inside of the fine hole and the inside of the airtight container, and then the substrate is taken out of the molten metal and cooled, so that the metal is formed in the fine hole. Fill.
[0050]
In step 6, the bonding substrate 4 is removed by polishing or etching. As the etching, either dry etching or wet etching can be applied. In the case of dry etching, SF6 gas, CF4 gas, oxygen gas, or a mixed gas thereof is used. In the case of wet etching, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, or an aqueous potassium hydroxide solution is used.
[0051]
The thickness of the bonded substrate that is removed by etching or polishing varies depending on the material of the bonded substrate 6. When the bonding substrate 6 is silicon, the back surface insulating layer 4 is already formed between the substrate 1 and the bonding substrate 6, so that the thickness equal to the thickness of the bonding substrate 6 is removed by polishing or etching. Then, the back surface insulating layer 4 is exposed.
[0052]
On the other hand, when the bonding substrate 6 is a glass substrate, since the back surface insulating layer 4 is not provided between the substrate 1 and the bonding substrate 6, the bonding substrate 5 made of glass is removed at a thickness of about several μm. And the remaining glass layer is used as the back insulating layer 4 for insulation and surface protection.
[0053]
In any bonding substrate removing method, the thickness of the substrate 1 does not change, so the depth of the through microhole is constant and equal to the thickness of the substrate 1. Therefore, the thickness of the substrate 1 after the through electrode is formed is constant with high accuracy, and a substrate with a through electrode with high thickness reproducibility can be manufactured.
[0054]
In step 7, the back surface insulating layer 4 at the through electrode portion is patterned by a lithography technique and then selectively removed by etching or polishing to form a conduction hole 9 (contact hole).
[0055]
Next, examples of the present invention will be described. Diameter is 2 inches, providing a silicon substrate thickness of 400 [mu] m, after forming a Si0 ₂ film by thermal oxidation on the surface of the silicon substrate, a photoresist is coated on the oxide film, by photolithography electrode patterns - transferring the down on the resist, removing the photoresist and Si0 ₂ film on a silicon substrate serving as an electrode portion by wet etching.
[0056]
The transferred electrode pattern is a pattern in which 2000 circular holes having a hole diameter of 60 μm are arranged. Further, the SiO ₂ film thickness after wet etching was 1 μm and the photoresist thickness was 2 μm, and these two layers were used as a mask for forming the next through microhole.
[0057]
The through micropores were formed by ICP-RIE. Next, substrate bonding was performed. The substrate to be bonded is a silicon substrate having a diameter of 2 inches and a thickness of 200 μm. Both substrates were subjected to a hydrophilic treatment by washing with a mixed aqueous solution of ammonia and hydrogen peroxide, and then bonded together.
[0058]
The bonded substrates were subjected to heat treatment at 1100 ° C. for 3 hours in an oxygen atmosphere. In this example, since a thermal bonding method was used, a wall surface insulating layer was formed in the bonding step, and it was not necessary to newly form a wall surface insulating layer.
[0059]
Next, a metal to be an electrode was injected into the fine holes by a molten metal method, and the bonded substrate was removed by polishing. The polishing amount is 200 μm, which is equal to the thickness of the bonded substrates. Then, the substrate rear surface SiO ₂ insulating layer is formed, the SiO ₂ film in the electrode region selectively etched and removed by using a photolithography technique, an etching technique, contact holes - the formation of the Le .
[0060]
In this way, a substrate with a through electrode having substantially the same thickness as that of the starting substrate could be obtained.
[0061]
【The invention's effect】
As described above, in the present invention, when forming the through electrode on the substrate, the through hole is formed in the substrate, the bonding substrate is bonded to the substrate, and the through hole is filled with the electrode metal. Thereafter, the bonding substrate is removed, and a contact hole is formed at the electrode portion. Therefore, the depth of the through microhole is constant and equal to the thickness of the substrate before drilling. Therefore, the substrate thickness after forming the through electrode does not vary from one production to another, and a substrate with a through electrode having the same thickness as the starting substrate can be efficiently manufactured with good reproducibility. In addition, since the insulating layer is formed in the step of bonding the bonding substrate to the substrate, it is not necessary to form the back surface insulating layer after removing the bonding substrate.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a through electrode manufacturing process according to the present invention.
FIG. 2 is a diagram illustrating an example of a through electrode manufacturing process according to a conventional example.
[Explanation of symbols]
1 .... Substrate, 1a ... Substrate surface, 1b ... Back side of substrate, 2 .... Surface insulation layer, 3 .... Resist, 4 ....・ Back insulating layer, 5... Fine through-hole, 6 .. Bonding substrate, 7 .. Insulating wall surface, 8... Conductive layer, 9. Contact hole

Claims (6)

A method of manufacturing a substrate with a through electrode, wherein through holes are formed in an electrode portion on a silicon substrate by a method selected from ICP-RIE, PAECE, laser method, or micro drill method, and then the silicon substrate A bonding substrate is bonded to the back surface via a back surface insulating layer, and then an insulating layer is formed on the inner wall of the through-hole by a method selected from a thermal oxidation method, a PE-CVD method, or an anodization method , A method for manufacturing a substrate with a through electrode, wherein the bonding substrate is removed after a conductive layer is formed by filling the fine holes with metal. A method of manufacturing a substrate with a through electrode, wherein through holes are formed in an electrode portion on a silicon substrate by a method selected from ICP-RIE, PAECE, laser method, or micro drill method, and then the silicon substrate is formed. Then, a bonding substrate that is a glass substrate is bonded, and then an insulating layer is formed on the inner wall of the through-hole by a method selected from a thermal oxidation method, a PE-CVD method, or an anodization method , A method for manufacturing a substrate with a through electrode, comprising: forming a conductive layer by filling a metal; and removing the bonding substrate so that a part of the bonding substrate remains on the silicon substrate. 2. The method for manufacturing a substrate with a through electrode according to claim 1, wherein the bonding substrate is a silicon substrate or a glass substrate, and is bonded to the silicon substrate by thermal bonding or resin. 2. The method for manufacturing a substrate with a through electrode according to claim 1, wherein the back surface insulating layer is an insulating layer formed on the silicon substrate in advance before bonding.   The method for manufacturing a substrate with a through electrode according to claim 1, wherein the back surface insulating layer is an insulating layer formed on the bonding substrate before bonding. 3. The method of manufacturing a substrate with a through electrode according to claim 2, wherein the bonding substrate is a glass substrate and bonded to the silicon substrate by anodic bonding or resin.

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