JP4050671B2 - Constant voltage circuit - Google Patents

Description

  The present invention relates to a constant voltage circuit including an overcurrent protection circuit, and more particularly to a constant voltage circuit including an overcurrent protection circuit having a U-shaped characteristic.

FIG. 9 is a circuit diagram showing an example of a conventional constant voltage circuit including an overcurrent protection circuit having a U-shaped characteristic. The description of the constant voltage generation operation in the constant voltage circuit is omitted, and the operation of the overcurrent protection circuit having the U-shaped characteristic will be described below.
In FIG. 9, a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) M42 has a source and a gate connected to correspond to the source and gate of a PMOS transistor M41 that forms a driver transistor that controls the output current iout. . Therefore, a current proportional to the drain current of the PMOS transistor M41 is output from the drain of the PMOS transistor M42.

  The drain current of the PMOS transistor M42 is input to a current dividing circuit composed of PMOS transistors M44 and M45. In the PMOS transistors M44 and M45, the sources are connected to each other and the gates are connected to each other. Therefore, the drain current of the PMOS transistor M42 is divided into current values proportional to the transistor size ratio of the PMOS transistors M44 and M45, and output as drain currents of the PMOS transistors M44 and M45, respectively.

  The drain current of the PMOS transistor M44 flows to the resistor R53, and a voltage is generated across the resistor R53. When the voltage reaches the threshold voltage of an N-channel MOS transistor (hereinafter referred to as NMOS transistor) M49, the NMOS transistor M49 is turned on and the PMOS transistor M43 is turned on. Since the drain of the PMOS transistor M43 is connected to the gate of the PMOS transistor M41, when the PMOS transistor M43 is turned on, the PMOS transistor M43 operates to raise the gate voltage of the PMOS transistor M41, and the current iout output from the PMOS transistor M41 is increased. The increase is suppressed, and the output voltage Vout of the constant voltage circuit 100, which is the voltage at the output terminal from which the output current iout is output, decreases.

  A connection portion between the resistor R51 and the resistor R52 for detecting the output voltage Vout is a gate of the PMOS transistor M54 forming one input terminal of the differential amplifier circuit configured by the PMOS transistors M53 to M57, the resistor R54, and the capacitor C51. It is connected to the. A resistor R55 is connected between the gate of the PMOS transistor M55 forming the other input terminal of the differential amplifier circuit and the negative power supply voltage Vss. Since the resistor R55 is supplied with current from the positive power supply voltage Vdd via the PMOS transistors M58 and M59, a predetermined voltage is applied to the gate of the PMOS transistor M55.

  When the output voltage Vout is a predetermined voltage, the gate voltage of the PMOS transistor M54 is set to be higher than the gate voltage of the PMOS transistor M55 in the differential amplifier circuit. When the output current iout becomes an overcurrent and the output voltage Vout decreases, the voltage at the connection between the resistor R51 and the resistor R52 that detects the output voltage Vout also decreases, and the gate voltage of the PMOS transistor M54 decreases. When the gate voltage of the PMOS transistor M54 falls below the gate voltage of the PMOS transistor M55, the drain current of the PMOS transistor M54 increases and the drain voltage of the PMOS transistor M54 increases. Since the gate of the NMOS transistor M51 is connected to the drain of the PMOS transistor M54, the NMOS transistor M51 is turned on.

  When the NMOS transistor M51 is turned on, the PMOS transistor M50 connected to the drain of the NMOS transistor M51 is turned on. The PMOS transistor M50 forms a current mirror circuit with the PMOS transistor M52, and the PMOS transistor M52 is also turned on. Since the drain of the PMOS transistor M52 is connected to the gate of the PMOS transistor M41, when the PMOS transistor M52 is turned on, the gate voltage of the PMOS transistor M41 is increased and the drain current of the PMOS transistor M41, that is, the output current iout is decreased. . The characteristic indicating the relationship between the output voltage Vout and the output current iout is a U-shaped characteristic as shown in FIG.

Also, when the output voltage drops due to load short circuit or half short circuit, this is detected by the voltage detection circuit, and the operation signal is supplied from the protection circuit to the current limit circuit based on this detection signal, and the current limit circuit controls it Some switching elements that supply a current to a load are kept in a non-conductive state by outputting a stop signal to the unit (see, for example, Patent Document 1).
Japanese Patent Publication No. 7-46291

On the other hand, in recent years, there has been a demand for power saving of electronic devices, and there is a strong demand for low current consumption even in a power supply circuit forming a constant voltage circuit, and it is also required to reduce current consumption of a protection circuit provided in the constant voltage circuit. It has been.
However, as shown in FIG. 9, since the conventional overcurrent protection circuit uses a differential amplifier circuit, the PMOS transistor M53 is set to reduce the current consumption of the differential amplifier circuit. If the bias current to be applied is reduced, the response speed of the differential amplifier circuit becomes slow, and phase compensation becomes difficult.

  If the phase compensation is not appropriate, there is a problem that the operation of the differential amplifier circuit becomes unstable and oscillation occurs in the region where the output current iout decreases while the output voltage Vout of FIG. 10 decreases. Phase compensation of the differential amplifier circuit is possible to some extent by changing the time constants of the resistor R54 and the capacitor C51 in FIG. 9, but the bias current could not be reduced to near zero.

  The present invention has been made in order to solve the above-described problems, and has an overcurrent protection circuit capable of reducing current consumption while having characteristics close to those of a conventional U-shaped characteristic. The purpose is to obtain a constant voltage circuit.

The constant voltage circuit according to the present invention includes an output control transistor that controls a current output from the output terminal so that an output voltage output from the predetermined output terminal is constant at a predetermined value. In a constant voltage circuit including an overcurrent protection circuit that controls the operation of the output control transistor so that the current output from the control transistor does not exceed a predetermined value,
The overcurrent protection circuit is
A proportional current generation circuit unit that generates a current proportional to the current output from the output control transistor;
A current dividing circuit unit that divides the current output from the proportional current generation circuit unit by a predetermined ratio;
A division ratio control circuit unit for controlling a ratio divided by the current dividing circuit unit;
A current-voltage conversion circuit unit that converts a predetermined one of the currents divided by the current dividing circuit unit into a voltage and outputs the voltage;
An output current control circuit unit that performs output current control on the output control transistor in accordance with the voltage converted by the current-voltage conversion circuit unit;
With
When the output voltage of the current-voltage conversion circuit unit reaches a predetermined voltage, the output current control circuit unit suppresses an increase in output current to the output control transistor and is output from the output terminal. When the output voltage drops to a predetermined first limit voltage, the division ratio control circuit unit increases the current supplied to the current-voltage conversion circuit unit and is output from the output control transistor. The ratio divided by the current dividing circuit unit is changed so that the current decreases.

  The overcurrent protection circuit includes a conversion ratio change circuit unit that changes a current-voltage conversion ratio of the current-voltage conversion circuit unit according to an output voltage output from the output terminal, and the conversion ratio change circuit unit When the output voltage output from the output terminal decreases to a predetermined second limit voltage, the output voltage of the current-voltage conversion circuit unit increases and the current output from the output control transistor decreases. The current-voltage conversion ratio of the current-voltage conversion circuit unit is changed.

  Specifically, the first limit voltage may be set to be larger than the second limit voltage.

  Specifically, the current-voltage conversion circuit unit is configured by a plurality of resistors that convert current into voltage.

  In this case, the conversion ratio changing circuit unit includes a switch element that short-circuits a predetermined resistance of the current-voltage conversion circuit unit, and the switch element performs switching according to the output voltage output from the output terminal, The combined resistance value of the current-voltage conversion circuit unit is changed by the switching to change the current-voltage conversion ratio of the current-voltage conversion circuit unit.

  Specifically, the resistance value of at least one resistor of the current-voltage conversion circuit unit may be set by trimming.

  On the other hand, the proportional current generation circuit unit is configured by a first transistor which is a transistor having a transistor size of the output control transistor reduced, and the first transistor is a current proportional to the current output from the output control transistor. May be output.

  The current dividing circuit unit includes a plurality of transistors each receiving a voltage corresponding to an output voltage output from the output terminal at a control signal input terminal, and each of the transistors includes the proportional current generation circuit unit. Alternatively, the current output from each of the transistors may be input to output a current corresponding to the transistor size ratio.

  In this case, the current dividing circuit unit is configured such that a predetermined transistor of the transistors is connected to the current-voltage conversion circuit unit, and a switch element is connected to the predetermined transistor of the other transistors. The division ratio control circuit unit may control the ratio divided by the current division circuit unit by controlling the switching of the switch element in accordance with the voltage output from the output terminal.

Specifically, a reference voltage generation circuit that generates and outputs a predetermined reference voltage;
An output voltage detection circuit that detects an output voltage output from a predetermined output terminal and generates and outputs a voltage proportional to the detected output voltage; and
An error amplifier for controlling the operation of the output control transistor with a voltage output by amplifying a voltage difference between the reference voltage and the voltage output from the output voltage detection circuit;
With
The reference voltage generation circuit includes:
A second transistor comprising a depletion type NMOS transistor in which the gate and the source are short-circuited;
A third transistor comprising an enhancement type NMOS transistor in which the gate and drain are short-circuited;
Have
The second transistor and the third transistor are connected in series, the drain of the second transistor is connected to the positive power supply voltage side of the DC power supply, and the source of the third transistor is connected to the negative power supply voltage side of the DC power supply. The reference voltage is output from the connection part of the second transistor and the third transistor.

  In this case, the division ratio control circuit unit is turned on when the output voltage output from the output terminal exceeds the first limit voltage, and is the same type as the third transistor and has a transistor size larger than that of the third transistor. The current dividing circuit unit includes four transistors, and when the fourth transistor is turned off, the current supplied to the current-voltage conversion circuit unit is increased and the current output from the output control transistor is decreased. The ratio of division may be changed.

  The conversion ratio changing circuit unit is turned on when the output voltage output from the output terminal exceeds the second limit voltage, and is the same type as the fourth transistor and has a transistor size larger than the fourth transistor, or A fifth transistor having a small threshold voltage, and when the output voltage output from the output terminal decreases to the second limit voltage and the fifth transistor is turned off, the output voltage of the current-voltage conversion circuit section increases. Then, the current-voltage conversion ratio of the current-voltage conversion circuit unit may be changed so that the current output from the output control transistor decreases.

  The fourth transistor and the fifth transistor are each composed of a plurality of MOS transistors and at least one fuse connected in series to a predetermined MOS transistor of each MOS transistor, and the fuses are selectively cut off. Thus, the transistor size may be set.

  Further, a current mirror circuit unit for supplying currents corresponding to the currents flowing through the second transistor and the third transistor to the fourth transistor and the fifth transistor, respectively, and threshold values of the fourth transistor and the fifth transistor are provided. The transistor sizes of the second transistor, the fourth transistor, and the fifth transistor may be set so as to cancel the temperature characteristics of the value voltage and each β value.

  On the other hand, a conversion ratio changing circuit unit that changes a current-voltage conversion ratio of the current-voltage conversion circuit unit according to an output voltage output from the output terminal is provided, and the conversion ratio changing circuit unit outputs from the output terminal. The current-voltage conversion ratio of the current-voltage conversion circuit unit is changed so that the current output from the output control transistor decreases according to the decrease in the output voltage.

  In this case, the conversion ratio changing circuit unit is divided by the current dividing circuit unit so that the current output from the output control transistor decreases when the output voltage decreases to a predetermined third limit voltage. Changed.

  Further, the conversion ratio changing circuit unit is configured to divide the current dividing circuit unit so that the current output from the output control transistor further decreases when the output voltage decreases to a predetermined fourth limit voltage. May be changed.

  Specifically, the first limit voltage is set to be higher than the second limit voltage, the second limit voltage is set to be higher than the third limit voltage, and the third limit voltage is set to be higher than the fourth limit voltage. It was to so.

  According to the constant voltage circuit of the present invention, the overcurrent protection circuit having the output voltage and output current limiting characteristics approximate to the U-shaped characteristics, which has low current consumption and does not have unstable operation such as oscillation, is provided. it can.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a circuit diagram showing an example of a constant voltage circuit according to the first embodiment of the present invention.
In FIG. 1, the constant voltage circuit 1 controls the output current io output from the output terminal OUT so that the output voltage Vo output from the output terminal OUT becomes constant at a predetermined voltage. An overcurrent protection circuit 2 for the output current io is provided. The overcurrent protection circuit 2 operates so that the relationship between the output voltage Vo and the output current io has a characteristic that approximates the U-shaped characteristic.

  The constant voltage circuit 1 includes an overcurrent protection circuit 2, a reference voltage generation circuit 3 that generates and outputs a predetermined reference voltage Vr, and an output voltage detection circuit 4 that divides and outputs the output voltage Vo by resistors R1 and R2. An error amplifier 5 that amplifies and outputs the difference voltage between the divided voltage VFB output from the output voltage detection circuit 4 and the reference voltage Vr, and the output current io according to the output signal from the error amplifier 5 It includes a PMOS transistor M1 that forms a driver transistor that performs control to control the output voltage Vo to be a constant voltage. The overcurrent protection circuit 2 includes PMOS transistors M2 to M15, NMOS transistors M16 to M27, and resistors R3 to R5.

  The PMOS transistor M1 is an output control transistor, the resistors R1 and R2 are output voltage detection circuits, the PMOS transistor M2 is a proportional current generation circuit unit and a first transistor, and the PMOS transistors M4 and M5 are current division circuit units. The PMOS transistors M10 and M12 and the NMOS transistors M16, M24, and M25 form a division ratio control circuit unit, respectively. The resistors R3 and R4 are current-voltage conversion circuit units, the PMOS transistor M3, the NMOS transistor M20 and the resistor R5 are output current control circuit units, and the PMOS transistors M7 and M9 and the NMOS transistors M21 to M23 are conversion ratio changing circuit units. Make each. The NMOS transistor M22 forms a fifth transistor, and the NMOS transistor M24 forms a fourth transistor.

  A PMOS transistor M1 is connected between the positive power supply voltage Vdd and the output terminal OUT, and a series circuit of resistors R1 and R2 is connected between the output terminal OUT and the negative power supply voltage Vss. The connection between the resistor R1 and the resistor R2 is connected to the non-inverting input terminal of the error amplifier 5, and the reference voltage Vr is input to the inverting input terminal of the error amplifier 5. The output terminal of the error amplifier 5 is connected to the gate of the PMOS transistor M1. The error amplifier 5 controls the operation of the PMOS transistor M1 so that the divided voltage VFB becomes the reference voltage Vr, controls the output current io, and controls the output voltage Vo to be a constant voltage.

  Since the source of the PMOS transistor M2 is connected to the source of the PMOS transistor M1, and the gate of the PMOS transistor M2 is connected to the gate of the PMOS transistor M1, a current proportional to the drain current of the PMOS transistor M1 flows from the drain of the PMOS transistor M2. . The drain current of the PMOS transistor M2 is supplied to the sources of the PMOS transistors M4 and M5 in the current mirror circuit composed of the PMOS transistors M4 to M6, and is divided into currents proportional to the transistor sizes of the PMOS transistors M4 and M5. Output as drain currents of the transistors M4 and M5, respectively.

  The drain current of the PMOS transistor M4, which is one of the divided currents, is supplied to the resistors R3 and R4 connected in series. Note that an NMOS transistor M21, which is normally turned on, is connected in parallel to both ends of the resistor R4 and is short-circuited. A connection portion between the resistor R3 and the drain of the PMOS transistor M4 is connected to the gate of the NMOS transistor M20. When the voltage across the series circuit of the resistors R3 and R4 reaches the threshold voltage of the NMOS transistor M20, the NMOS transistor M20 is turned on.

  Since the gate of the PMOS transistor M3 is connected to the drain of the NMOS transistor M20, the PMOS transistor M3 is also turned on when the NMOS transistor M20 is turned on. Since the source of the PMOS transistor M3 is connected to the source of the PMOS transistor M1, and the drain of the PMOS transistor M3 is connected to the gate of the PMOS transistor M1, respectively, when the PMOS transistor M3 is turned on, the gate voltage of the PMOS transistor M1 is controlled, An increase in the output current io is suppressed and the output voltage Vo is lowered.

  This shows the state at point (a) in FIG. 2 showing the relationship between the output voltage Vo and the output current io. That is, when the output current io becomes the first limit current value ia, the NMOS transistor M20 is turned on, and the PMOS transistor M3 limits the output current io to the first limit current value ia so that the overcurrent protection circuit 2 can operate the PMOS transistor. The operation control of M1 is performed, and the output voltage Vo decreases.

  On the other hand, the divided voltage VFB is inputted to the gate of the NMOS transistor M24, and the NMOS transistor M24 having a larger transistor size is used. While the constant voltage circuit 1 is operating normally, the divided voltage VFB and the reference voltage Vr are controlled to be the same voltage. Therefore, in this state, the NMOS transistor M24 is on. As the output voltage Vo decreases, the divided voltage VFB decreases. When the output voltage Vo decreases to the voltage Vb at the point (b) in FIG. 2, the NMOS transistor M24 is turned off. That is, the NMOS transistor M24 serves as a transistor for detecting the first limit voltage Vb.

  Since the drain of the NMOS transistor M24 is connected to the gate of the NMOS transistor M25, when the NMOS transistor M24 is turned off, the NMOS transistor M25 is turned on to lower the drain voltage of the NMOS transistor M25. Since the drain of the NMOS transistor M25 is connected to the gates of the NMOS transistors M16 and M17, the NMOS transistors M16 and M17 are turned off.

  When the NMOS transistor M16 is turned off, the current path of the drain current of the PMOS transistor M5 that divides the drain current of the PMOS transistor M2 proportional to the output current io is cut off, so that the drain current of the PMOS transistor M2 is all PMOS transistor It flows to M4. As a result, the voltage across the resistor R3 increases, the drain current of the NMOS transistor M20 increases, the gate voltage of the PMOS transistor M3 decreases, the gate voltage of the PMOS transistor M1 increases, and the output current io decreases. This shows the state at point (c) in FIG. That is, when the output current io reaches the current value ic, the NMOS transistor M16 is turned off, and the overcurrent protection circuit 2 operates the PMOS transistor M1 so that the output current io is limited to the second limit current value ic by the PMOS transistor M3. Control is performed and the output voltage Vo decreases.

  The divided voltage VFB is input to the gate of the NMOS transistor M22. As the NMOS transistor M22, a transistor having a larger transistor size or a smaller threshold voltage than the NMOS transistor M24 is used. While the constant voltage circuit 1 is operating normally, the NMOS transistor M22 is on, as is the NMOS transistor M24. As the output voltage Vo decreases, the divided voltage VFB decreases, and when the output voltage Vo decreases to the voltage Vd at the point (d) in FIG. 2, the NMOS transistor M22 is turned off. In other words, the NMOS transistor M22 forms a transistor for detecting the second limit voltage Vd.

  Since the drain of the NMOS transistor M22 is connected to the gate of the NMOS transistor M23, when the NMOS transistor M22 is turned off, the NMOS transistor M23 is turned on to lower the drain voltage of the NMOS transistor M23. Since the drain of the NMOS transistor M23 is connected to the gate of the NMOS transistor M21, the NMOS transistor M21 is turned off.

  When the NMOS transistor M21 is turned off, the drain current of the PMOS transistor M2 that has flowed only through the resistor R3 also flows into the resistor R4. For this reason, the gate voltage of the NMOS transistor M20 rises, and the gate voltage of the PMOS transistor M1 is raised through the NMOS transistor M20 and the PMOS transistor M3 to reduce the output current io. This shows the state at point (e) in FIG. That is, when the output current io reaches the current value ie, the NMOS transistor M21 is turned off, and the overcurrent protection circuit 2 operates the PMOS transistor M1 so that the output current io is limited to the third limited current value ie by the PMOS transistor M3. Control is performed and the output voltage Vo decreases. As described above, when the output current io of the constant voltage circuit 1 increases to the first limit current ia, the output voltage Vo and the output current io are lowered stepwise so as to be substantially U-shaped.

Next, the start of operation of the overcurrent protection circuit 2 will be described.
The NMOS transistor M26 is a depletion type MOS transistor, and has a gate connected to the ground voltage, so that a predetermined drain current flows. The drain of the NMOS transistor M26 is connected to the gate of the NMOS transistor M27 and the drain of the PMOS transistor M14. The drain of the PMOS transistor M13 is connected to the source of the PMOS transistor M14.

  Since the source of the PMOS transistor M13 is connected to the source of the PMOS transistor M1, and the gate of the PMOS transistor M13 is connected to the gate of the PMOS transistor M1, the drain current of the PMOS transistor M13 becomes a current proportional to the output current io. The drain current of the PMOS transistor M13 becomes the drain current of the NMOS transistor M26 via the bias voltage setting PMOS transistor M14.

  When the output current io of the constant voltage circuit 1 reaches a predetermined current value ia, the drain voltage of the NMOS transistor M26 exceeds the threshold voltage of the NMOS transistor M27, and the NMOS transistor M27 is turned on. When the NMOS transistor M27 is turned on, the PMOS transistors M8 and M11 whose gates are respectively connected to the drain of the NMOS transistor M27 are turned on, and the drains of the NMOS transistor M22 and the NMOS transistor M24 are PMOS transistors M7 and M10 which are current sources. The NMOS transistor M22 and the NMOS transistor M24 function respectively. The PMOS transistors M7, M9, M10, M12, and M15 each constitute a constant current source, and a predetermined bias voltage Vbias from the reference voltage generation circuit 3 is input to each gate.

Next, FIG. 3 is a diagram illustrating a circuit example of the reference voltage generation circuit 3.
In FIG. 3, the reference voltage generation circuit 3 includes a PMOS transistor M31, a depletion type NMOS transistor M32, and an enhancement type NMOS transistor M33. The NMOS transistor M32 forms a second transistor, and the NMOS transistor M33 forms a third transistor. A PMOS transistor M31, an NMOS transistor M32, and an NMOS transistor M33 are connected in series between the positive power supply voltage Vdd and the negative power supply voltage Vss, in the case of FIG. 1, the ground voltage.

  The gate of the PMOS transistor M31 is connected to the drain, the gate of the NMOS transistor M32 is connected to the source, and the gate of the NMOS transistor M33 is connected to the drain. A bias voltage Vbias is output from a connection portion between the PMOS transistor M31 and the NMOS transistor M32, and a reference voltage Vr is output from a connection portion between the NMOS transistor M32 and the NMOS transistor M33. The PMOS transistor M31 forms a current mirror circuit with the PMOS transistors M7, M9, M10, M12, and M15, respectively, and the PMOS transistors M31, M7, and M10 form a current mirror circuit unit.

  The NMOS transistor M22 and the NMOS transistor M24, which are the same type as the enhancement type NMOS transistor M33 and have a large transistor size, have a smaller gate-source voltage than the NMOS transistor M33, which is necessary for flowing the same drain current as that of the enhancement type NMOS transistor M33. It's okay. Therefore, each detection circuit for detecting the first limit voltage Vb and the second limit voltage Vd described above can be configured.

  In the above description, a plurality of MOS transistors having different transistor sizes are used in the voltage detection circuit for detecting the first limit voltage Vb and the second limit voltage Vd to detect a decrease in the output voltage Vo in multiple stages, and the PMOS transistor If the voltage at the connection portion between M4 and the resistor R3 is converted in multiple stages, the output current io can be limited to a characteristic closer to a U-shaped characteristic.

  In the above description, the case where each of the resistors R3 and R4 is configured by one resistor has been described as an example. However, the resistor R3 and the resistor R4 are connected to a plurality of resistors in series and each of the resistors is connected. You may make it the structure which connects a fuse in parallel to all or one part, respectively. In this way, the fuses can be selectively cut by laser trimming to set the resistances R3 and R4 to desired resistance values.

  For example, as shown in FIG. 4, the resistor R3 includes two resistors R31 and R32 connected in series, and a fuse F3 connected in parallel to the resistor R31, and the resistor R3 depends on whether or not the fuse F3 is cut. The resistance value of R3 can be changed. Similarly, for example, as shown in FIG. 5, the resistor R4 is composed of two resistors R41 and R42 connected in series and a fuse F4 connected in parallel to the resistor R41, and whether or not the fuse F4 is connected. Thus, the resistance value of the resistor R4 can be changed.

  In addition, the NMOS transistor M22 and the NMOS transistor M24 are described as an example in which each of the NMOS transistors M22 and M24 is configured by one NMOS transistor. However, the NMOS transistors M22 and M24 are each composed of a plurality of NMOS transistors and all or each of the NMOS transistors. You may make it comprise with each fuse connected in series in part. When there is a series circuit of a fuse and an NMOS transistor and an NMOS transistor to which no fuse is connected, the NMOS transistor is connected in parallel. By doing so, each of the fuses can be selectively cut by laser trimming to set the NMOS transistors M22 and M24 to a desired current driving capability. This is the same as changing the transistor sizes of the NMOS transistors M22 and M24.

  For example, as shown in FIG. 6, the NMOS transistor M22 includes NMOS transistors M221 to M224 and fuses F221 to F223 connected in series corresponding to the NMOS transistors M222 to M224. The NMOS transistor M22 can change the current driving capability, that is, the transistor size, depending on whether or not the fuses F221 to F223 are to be cut and which of the fuses F221 to F223 is to be cut. Further, for example, as shown in FIG. 7, the NMOS transistor M24 includes NMOS transistors M241 and M242 and a fuse F241 connected in series to the NMOS transistor M242. The NMOS transistor M24 can change the current driving capability, that is, the transistor size, depending on whether or not the fuse F241 is cut.

  On the other hand, since the threshold voltages of the NMOS transistors M22 and M24 vary depending on the temperature, the first limit voltage Vb and the second limit voltage Vd vary. For example, at the high temperature, the first limit voltage Vb and the second limit voltage Vd decrease, the amount of heat generated by the PMOS transistor M1 at the points (b) and (d) in FIG. 1 limit voltage Vb and 2nd limit voltage Vd fall. Therefore, the temperature dependence of the current flowing through the PMOS transistor M31 and the NMOS transistors M32 and M33 of the reference voltage generation circuit 3 is canceled by the change of the threshold voltages and the β values depending on the temperatures of the NMOS transistors M22 and M24. By adjusting the circuit constant, the first limit voltage Vb and the second limit voltage Vd can be prevented from changing with temperature.

  For example, when the drain-source current ids of the PMOS transistor M31 flows, the drain-source current ids (constant current) corresponding to the transistor size ratio of the PMOS transistors M31 and M10 forming the current mirror circuit is supplied to the PMOS transistor M10. Flowing. At the same time, a drain-source current ids (constant current) corresponding to the transistor size ratio of the PMOS transistors M31 and M7 forming the current mirror circuit flows to the PMOS transistor M7.

  When the threshold voltage and β value of the NMOS transistor M32 change due to the temperature change and the drain-source current ids of the NMOS transistor M32 changes, the drain-source current ids of the PMOS transistor M31 also changes. Accordingly, the drain-source currents ids of the PMOS transistors M10 and M7 also vary in accordance with the transistor size ratio with the PMOS transistor M31.

  From this, the NMOS transistor M25 is obtained by canceling the change in the drain-source currents of the PMOS transistors M10 and M7 by the respective changes in the respective threshold voltages and the respective β values due to the temperature variation of the NMOS transistors M24 and M22. The voltage level of the divided voltage VFB for turning on / off M23 is made independent of temperature. Thus, the first limit voltage Vb and the second limit voltage Vd can be made independent of temperature, and this can be realized by adjusting the transistor sizes of the NMOS transistors M32, M24, and M22.

  In the above description, the divided voltage VFB is input to the gates of the NMOS transistors M22 and M24. However, as shown in FIG. 8, the output voltage Vo is applied to the gates of the NMOS transistors M22 and M24. Each may be input.

  As described above, the constant voltage circuit according to the first embodiment suppresses an increase in the current output from the PMOS transistor M1 when the output current io reaches the first limit current ia by the overcurrent protection circuit 2. The PMOS transistor M1 is controlled so as to lower the output voltage Vo, and when the output voltage Vo drops to the predetermined first limit voltage Vb, the NMOS transistor M24 is turned off, the NMOS transistor M16 is turned off, and the gate of the NMOS transistor M20 When the voltage rises, the gate voltage of the PMOS transistor M1 is raised, the output current io is limited by the second limit current value ic to lower the output voltage Vo, and the output voltage Vo falls to the predetermined second limit voltage Vd. The NMOS transistor M22 is turned off, the NMOS transistor M21 is turned off, and the NMOS transistor Further increases the gate voltage of the register M20, further raising the gate voltage of the PMOS transistor M1 and the output current io further reduce the limited output voltage Vo at the third limit current value ie.

  For this reason, the limit current value for the output current io can be changed stepwise, and the combination of the limit current value and the output voltage Vo can be changed stepwise to prevent oscillation and the like. Reduction can be achieved.

  In FIG. 2, the voltage difference between the predetermined voltage value Vx of the normal output voltage Vo and the first limit voltage value Vb is preferably small, that is, the first limit voltage value Vb is preferably large. The reason for this is that a great amount of heat is generated when the output voltage Vo decreases while maintaining the first limit current value ia. Therefore, by setting the first limit voltage value Vb to be large, the effect of reducing the heat generation is obtained. There is. In FIG. 2, in order to reduce heat generation, the second limit voltage value Vd is preferably set to be small enough that the minimum value including the ambient temperature and process variations does not become 0V. Therefore, FIG. 2 may have characteristics as shown in FIG.

As shown in FIG. 11, in order to increase the first limit voltage value Vb and decrease the second limit voltage value Vd, either one of the following three conditions (I) to (III) is satisfied: Alternatively, the conditions (I) and (II) may be satisfied.
(I) The threshold voltage of the NMOS transistor M24 is made larger than the threshold voltage of the NMOS transistor M22.
(II) The transistor size of the NMOS transistor M24 is made smaller than the transistor size of the NMOS transistor M22.
(III) The NMOS transistors M22 and M24 have the same threshold voltage and the same transistor size, and the divided voltage VFB is input to the gate of the NMOS transistor M24 and the output voltage Vo is input to the gate of the NMOS transistor M22. To.

Here, in FIG. 11, the characteristic indicated by the broken line indicates that the intersection of the maximum value of the output current io on the specifications of the constant voltage circuit 1 and the set value Vx of the output voltage Vo, the output voltage Vo is 0V, and the output current io is This is a line connecting points that are 0A, and this is called a load meridian L1.
The third limit current value ie is preferably reduced to reduce heat generation when the output is short-circuited. However, the rise time when the power is turned on is delayed when the third limit current value ie is reduced. For this reason, the third limited current value ie including the allowable loss of the package is set to an optimum value.

  Here, the intersection P between the second limit voltage value Vd and the third limit current value ie must be prevented from entering the hatched portion in FIG. This is because, when the maximum value of the output current io of the specification is used with a resistive load, the output when the power is turned on rises on the load meridian L1, and therefore the overcurrent protection circuit 2 when the intersection P is in the hatched portion in FIG. This is because the output does not rise. Therefore, as shown in FIG. 12, the intersection P between the load meridian L1 and the third limit current value ie is set to a minimum value including variations in the second limit voltage value Vd including variations in ambient temperature and process. If the second limit voltage value Vd is set, heat generation can be minimized.

  By setting the second limit voltage value Vd in this way, the third limit current value ie is preferably small in order to reduce the heat generation at the time of short circuit when the output voltage Vo becomes 0 V, but the second limit voltage value By setting Vd to be small, the third limited current value ie can be made smaller within the range where the intersection P does not enter the shaded portion shown in FIG. Also, when the output current io has a steep fluctuation, the output voltage fluctuates temporarily to be below the second limit voltage value Vd, and the output current io at that time must be larger than the third limit current value ie. For example, the output voltage Vo does not return to the set output voltage of the product. For this reason, if the second limit voltage value Vd can be set small, such a state is unlikely to occur, and even when the output current io fluctuates more steeply, it can be used and the output voltage Vo can be stabilized. The capacity of the external capacitor can be reduced, and the size and weight can be reduced.

Second embodiment.
FIG. 13 is a circuit diagram showing an example of a constant voltage circuit according to the second embodiment of the present invention.
In FIG. 13, the constant voltage circuit 1a controls the output current io output from the output terminal OUT so that the output voltage Vo output from the output terminal OUT becomes constant at a predetermined voltage. An overcurrent protection circuit 2a for the output current io is provided. The overcurrent protection circuit 2a operates so that the relationship between the output voltage Vo and the output current io approximates the U-shaped characteristic.

  The constant voltage circuit 1a includes an overcurrent protection circuit 2a, a reference voltage generation circuit 3a that generates and outputs a predetermined reference voltage Vr, and an output voltage detection circuit 4a that divides and outputs the output voltage Vo by resistors R71 and R72. An error amplifier 5a that amplifies and outputs a difference voltage between the divided voltage VFB output from the output voltage detection circuit 4a and the reference voltage Vr, and an output current io according to an output signal from the error amplifier 5a. And a PMOS transistor M71 as a driver transistor that controls the output voltage Vo to be a constant voltage. The overcurrent protection circuit 2a includes PMOS transistors M72 to M76, NMOS transistors M77 to M81, and resistors R73 to R76.

  The PMOS transistor M71 is an output control transistor, the resistors R71 and R72 are each an output voltage detection circuit, the PMOS transistor M72 is a proportional current generation circuit unit and a first transistor, and the PMOS transistors M74 and M75 are current division circuit units. Make each. The resistors R73 to R75 form a current-voltage conversion circuit unit, the PMOS transistor M73, the NMOS transistor M79, and the resistor R76 form an output current control circuit unit, and the NMOS transistors M80 and M81 form a conversion ratio changing circuit unit and a switch element, respectively. .

  A PMOS transistor M71 is connected between the positive power supply voltage Vdd and the output terminal OUT, and a series circuit of resistors R71 and R72 is connected between the output terminal OUT and the negative power supply voltage Vss. The connection portion between the resistor R71 and the resistor R72 is connected to the non-inverting input terminal of the error amplifier 5a, and the reference voltage Vr is input to the inverting input terminal of the error amplifier 5a. The output terminal of the error amplifier 5a is connected to the gate of the PMOS transistor M71. The error amplifier 5a controls the operation of the PMOS transistor M71 so that the divided voltage VFB obtained by dividing the output voltage Vo by the resistors R71 and R72 becomes the reference voltage Vr, and controls the output current io to output the output voltage Vo. Is controlled to a constant voltage.

  Since the source of the PMOS transistor M72 is connected to the source of the PMOS transistor M71 and the gate of the PMOS transistor M72 is connected to the gate of the PMOS transistor M71, a current proportional to the drain current of the PMOS transistor M71 flows from the drain of the PMOS transistor M72. . The drain current of the PMOS transistor M72 is supplied to the sources of the PMOS transistors M74 and M75 in the current mirror circuit configured by the PMOS transistors M74 to M76, and is divided into currents proportional to the transistor sizes of the PMOS transistors M74 and M75. The drain currents of the transistors M74 and M75 are output.

  An NMOS transistor M77 is connected between the drain of the PMOS transistor M75 and the negative power supply voltage Vss, and an NMOS transistor M78 is connected between the drain of the PMOS transistor M76 and the negative power supply voltage Vss. The gates of the NMOS transistors M77 and M78 are connected, and the connection is connected to the drain of the NMOS transistor M77. NMOS transistors M77 and M78 form a current mirror circuit.

  The drain current of the PMOS transistor M74, which is one of the divided currents, is supplied to the resistors R73 to R75 connected in series. A connection portion between the resistor R73 and the drain of the PMOS transistor M74 is connected to the gate of the NMOS transistor M79. When the voltage at the connection between the resistor R73 and the PMOS transistor M74 reaches the threshold voltage of the NMOS transistor M79, the NMOS transistor M79 is turned on.

  The gate of the PMOS transistor M73 is connected to the positive power supply voltage Vdd via the resistor R76, and the gate of the PMOS transistor M73 is connected to the drain of the NMOS transistor M79. Therefore, when the NMOS transistor M79 is turned on, the PMOS transistor M73 is turned on. Also turn on. Since the source of the PMOS transistor M73 is connected to the source of the PMOS transistor M71 and the drain of the PMOS transistor M73 is connected to the gate of the PMOS transistor M71, when the PMOS transistor M73 is turned on, the gate voltage of the PMOS transistor M71 is controlled. An increase in the output current io is suppressed and the output voltage Vo is lowered.

  This shows the state at point (a) in FIG. 2 showing the relationship between the output voltage Vo and the output current io. That is, when the output current io reaches the first limit current value ia, the NMOS transistor M79 is turned on, and the PMOS transistor M73 causes the PMOS transistor M73 to limit the output current io to the first limit current value ia. The operation control of M71 is performed, and the output voltage Vo decreases.

  On the other hand, an NMOS transistor M81 is connected in parallel to a series circuit of resistors R74 and R75, and a divided voltage VFB is input to the gate of the NMOS transistor M81. An NMOS transistor M80 is connected in parallel with the resistor R75, and the divided voltage VFB is input to the gate of the NMOS transistor M80. While the constant voltage circuit 1a is operating normally, the divided voltage VFB and the reference voltage Vr are controlled to be the same voltage, and therefore, in this state, the NMOS transistors M80 and M81 are on. . As the output voltage Vo decreases, the divided voltage VFB decreases. When the output voltage Vo decreases to the voltage Vb at the point (b) in FIG. 2, the NMOS transistor M81 is turned off. That is, the NMOS transistor M81 forms a transistor for detecting the first limit voltage Vb.

  When the NMOS transistor M81 is turned off, the resistors R73 and R74 are connected in series between the gate of the NMOS transistor M79 and the ground voltage, the gate voltage of the NMOS transistor M79 rises, the drain current of the NMOS transistor M79 increases, and the PMOS The gate voltage of the transistor M73 decreases, the gate voltage of the PMOS transistor M71 is increased, and the output current io is decreased. This shows the state at point (c) in FIG. That is, when the output current io reaches the current value ic, the NMOS transistor M81 is turned off, and the overcurrent protection circuit 2a operates the PMOS transistor M71 so that the output current io is limited to the second limit current value ic by the PMOS transistor M73. Control is performed and the output voltage Vo decreases.

  The NMOS transistor M80 is larger in transistor size or smaller in threshold voltage than the NMOS transistor M81. While the constant voltage circuit 1a is operating normally, the NMOS transistor M80 is on, as is the NMOS transistor M81. As the output voltage Vo decreases, the divided voltage VFB decreases, and when the output voltage Vo decreases to the voltage Vd at the point (d) in FIG. 2, the NMOS transistor M80 is turned off. That is, the NMOS transistor M80 forms a transistor for detecting the second limit voltage Vd.

  When the NMOS transistor M80 is turned off, resistors R73 to R75 are connected in series between the gate of the NMOS transistor M79 and the ground voltage, the gate voltage of the NMOS transistor M79 rises, the drain current of the NMOS transistor M79 increases, and the PMOS The gate voltage of the transistor M73 decreases, the gate voltage of the PMOS transistor M71 is increased, and the output current io is decreased. This shows the state at point (e) in FIG.

  That is, when the output current io reaches the current value ie, the NMOS transistor M80 is turned off, and the overcurrent protection circuit 2a operates the PMOS transistor M71 so that the output current io is limited to the second limited current value ie by the PMOS transistor M73. Control is performed and the output voltage Vo decreases. As described above, when the output current io of the constant voltage circuit 1a increases to the first limit current ia, the output voltage Vo and the output current io are lowered stepwise so as to be substantially U-shaped.

  In the above description, the divided voltage VFB is input to the gates of the NMOS transistors M80 and M81. However, as shown in FIG. 14, the output voltage Vo is applied to the gates of the NMOS transistors M80 and M81. Each may be input. As shown in FIG. 15, the output voltage Vo may be input to the gate of the NMOS transistor M80, and the divided voltage VFB may be input to the gate of the NMOS transistor M81.

  In the above description, the case where each of the resistors R73 to R75 is configured by one resistor has been described as an example. However, the resistors R73 to R75 are the same as the resistors R3 and R4 illustrated in FIGS. In addition, a plurality of resistors may be connected in series and a fuse may be connected in parallel to all or a part of each resistor. By doing so, the respective fuses can be selectively cut by laser trimming to set the resistors R73 to R75 to desired resistance values.

  As described above, the constant voltage circuit according to the second embodiment suppresses an increase in the current output from the PMOS transistor M71 when the output current io reaches the first limit current value ia by the overcurrent protection circuit 2a. Then, the PMOS transistor M71 is controlled to decrease the output voltage Vo. When the output voltage Vo decreases to the predetermined first limit voltage value Vb, the NMOS transistor M81 is turned off, and the gate voltage of the NMOS transistor M79 increases, When the gate voltage of the PMOS transistor M71 is increased and the output current io is limited by the second limit current value ic to decrease the output voltage Vo, and the output voltage Vo is decreased to the predetermined second limit voltage value Vd, the NMOS transistor M80. Turns off, the gate voltage of the NMOS transistor M79 further rises, and the PMOS transistor Further increasing the gate voltage of M71 and the output current io further reduce the limited output voltage Vo at the third limit current value ie. For this reason, the same effects as those of the first embodiment can be obtained, the number of transistors constituting the circuit can be reduced, and the cost can be reduced.

Third embodiment.
The first embodiment and the second embodiment may be combined into one, and such a configuration is referred to as a third embodiment of the present invention.
FIG. 16 is a partial circuit diagram showing an example of a constant voltage circuit according to the third embodiment of the present invention. In FIG. 16, the same or similar parts as those in FIG. 1 or FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted here, and only differences from FIG. 1 will be described. Further, FIG. 16 shows only a circuit portion different from FIG.

  16 differs from FIG. 1 in that the resistor R3 in FIG. 1 is replaced with a series circuit of resistors R73 to R75, and the PMOS transistor M3, NMOS transistor M20, and resistor R5 in FIG. The NMOS transistor M79 and the resistor R76 are replaced. Accordingly, the overcurrent protection circuit 2 in FIG. 1 is changed to the overcurrent protection circuit 2b and the constant voltage circuit 1 in FIG. 1 is changed to the constant voltage circuit 1b.

In FIG. 16, the overcurrent protection circuit 2b includes PMOS transistors M2, M4 to M15, M73, NMOS transistors M16 to M19, M21 to M27, M79 to M81, and resistors R4, R73 to R76. The operations of the PMOS transistor M73, the NMOS transistors M79 to M81 and the resistors R73 to R76 are the same as those in FIG. 13, and the other operations are the same as those in FIG.
In such a configuration, the threshold voltages of the NMOS transistors M22, M24, M80, and M81 are Vth22, Vth24, Vth80, and Vth81, and the NMOS transistors M22, M24, and M80 are such that Vth24>Vth81>Vth80> Vth22. , M81.

FIG. 17 is a diagram showing the relationship between the output voltage Vo and the output current io in FIG.
In FIG. 17, when the output current io reaches the first limit current value iA, the NMOS transistor M79 is turned on, and the overcurrent protection circuit 2b limits the output current io to the first limit current value iA by the PMOS transistor M73. The operation control of the PMOS transistor M1 is performed, and the output voltage Vo decreases. This state shows the state at point (A) in FIG.
As the output voltage Vo decreases, the divided voltage VFB decreases. When the output voltage Vo decreases to the voltage VB at the point (B) in FIG. 17, the NMOS transistor M24 is turned off. That is, the NMOS transistor M24 serves as a transistor for detecting the first limit voltage VB.

  When the NMOS transistor M24 is turned off, the NMOS transistor M25 is turned on, the drain voltage of the NMOS transistor M25 is lowered, and the NMOS transistors M16 and M17 are turned off. When the NMOS transistor M16 is turned off, the current path of the drain current of the PMOS transistor M5 that divides the drain current of the PMOS transistor M2 proportional to the output current io is cut off, so that the drain current of the PMOS transistor M2 is all PMOS transistor It flows to M4. As a result, the gate voltage of the NMOS transistor M79 increases, the drain current of the NMOS transistor M79 increases, the gate voltage of the PMOS transistor M73 decreases, the gate voltage of the PMOS transistor M1 increases, and the output current io decreases. This shows the state at point (C) in FIG.

That is, when the output current io reaches the current value iC, the NMOS transistor M16 is turned off, and the overcurrent protection circuit 2b operates the PMOS transistor M1 so that the output current io is limited to the second limited current value iC by the PMOS transistor M73. Control is performed and the output voltage Vo decreases. In this state, the NMOS transistors M80 and M81 are each turned on.
As the output voltage Vo decreases, the divided voltage VFB decreases. When the output voltage Vo decreases to the voltage VD at the point (D) in FIG. 17, the NMOS transistor M81 is turned off. In other words, the NMOS transistor M81 forms a transistor for detecting the second limit voltage VD.

  When the NMOS transistor M81 is turned off, the resistors R73 and R74 are connected in series between the gate of the NMOS transistor M79 and the ground voltage because the NMOS transistor M21 is turned on. For this reason, the gate voltage of the NMOS transistor M79 increases, the drain current of the NMOS transistor M79 increases, the gate voltage of the PMOS transistor M73 decreases, the gate voltage of the PMOS transistor M1 increases, and the output current io decreases. This shows the state at point (E) in FIG. That is, when the output current io reaches the current value iE, the NMOS transistor M81 is turned off, and the overcurrent protection circuit 2b operates the PMOS transistor M1 so that the PMOS transistor M73 limits the output current io to the second limit current value iE. Control is performed and the output voltage Vo decreases.

As the output voltage Vo decreases, the divided voltage VFB decreases, and when the output voltage Vo decreases to the voltage VF at the point (F) in FIG. 17, the NMOS transistor M80 is turned off. In other words, the NMOS transistor M80 forms a transistor for detecting the third limit voltage VF.
When the NMOS transistor M80 is turned off, the resistors R73 to R75 are connected in series between the gate of the NMOS transistor M79 and the ground voltage because the NMOS transistor M21 is turned on. For this reason, the gate voltage of the NMOS transistor M79 increases, the drain current of the NMOS transistor M79 increases, the gate voltage of the PMOS transistor M73 decreases, the gate voltage of the PMOS transistor M1 increases, and the output current io decreases. This shows the state at point (G) in FIG.

That is, when the output current io reaches the current value iG, the NMOS transistor M80 is turned off, and the overcurrent protection circuit 2b operates the PMOS transistor M1 so that the output current io is limited to the fourth limit current value iG by the PMOS transistor M73. Control is performed and the output voltage Vo decreases.
As the output voltage Vo decreases, the divided voltage VFB decreases, and when the output voltage Vo decreases to the voltage VH at the point (H) in FIG. 17, the NMOS transistor M22 is turned off. In other words, the NMOS transistor M22 forms a transistor for detecting the fourth limit voltage VH.

  When the NMOS transistor M22 is turned off, the NMOS transistor M23 is turned on, the drain voltage of the NMOS transistor M23 is lowered, and the NMOS transistor M21 is turned off. When the NMOS transistor M21 is turned off, the drain current of the PMOS transistor M2 that has flowed through the resistors R73 to R75 also flows into the resistor R4. For this reason, the gate voltage of the NMOS transistor M79 rises, and the gate voltage of the PMOS transistor M1 is raised via the NMOS transistor M79 and the PMOS transistor M73 to reduce the output current io. This shows the state at point (J) in FIG.

  That is, when the output current io reaches the current value iJ, the NMOS transistor M21 is turned off, and the overcurrent protection circuit 2b operates the PMOS transistor M1 so that the output current io is limited to the fifth limited current value iJ by the PMOS transistor M73. Control is performed and the output voltage Vo decreases. As described above, when the output current io of the constant voltage circuit 1b increases to the first limit current iA, the output voltage Vo and the output current io are lowered stepwise so as to be substantially U-shaped.

  In the above description, the divided voltage VFB is input to the gates of the NMOS transistors M80 and M81. However, the output voltage Vo is input to the gates of the NMOS transistors M80 and M81. Also good. The output voltage Vo may be input to the gate of the NMOS transistor M80, and the divided voltage VFB may be input to the gate of the NMOS transistor M81. FIG. 16 shows an example in which three resistors are connected in series between the PMOS transistor M4 and the resistor R4. However, this is only an example, and between the PMOS transistor M4 and the resistor R4. A plurality of resistors may be connected in series, and a transistor may be provided that controls connection between the connection portions of the resistors and the ground voltage in accordance with the number of the resistors.

  As described above, the constant voltage circuit according to the third embodiment replaces the resistor R3 of the first embodiment with the series circuit of the resistors R73 to R75 as in the second embodiment, and outputs the output voltage. An NMOS transistor M80 that short-circuits the series circuit of the resistors R75 and R4 according to Vo and an NMOS transistor M81 that short-circuits the series circuit of the resistors R74, R75, and R4 according to the output voltage Vo are provided. As a result, the same effects as those of the first embodiment can be obtained, and the output voltage and output current can be reduced in multiple stages as compared with FIG. Characteristics can be obtained.

FIG. 3 is a circuit diagram showing an example of a constant voltage circuit in the first exemplary embodiment of the present invention. It is the figure which showed the relationship between the output voltage and output current in the constant voltage circuit of FIG. FIG. 2 is a diagram illustrating a circuit example of a reference voltage generation circuit 3 in FIG. 1. It is the figure which showed the other example of resistance R3 in FIG. It is the figure which showed the other example of resistance R4 in FIG. It is the figure which showed the other example of NMOS transistor M22 in FIG. It is the figure which showed the other example of NMOS transistor M24 in FIG. It is the circuit diagram which showed the other example of the constant voltage circuit in the 1st Embodiment of this invention. It is the circuit diagram which showed the example of the conventional constant voltage circuit provided with the overcurrent protection circuit which has a U-shaped characteristic. It is the figure which showed the relationship between the output voltage and output current in the constant voltage circuit of FIG. It is the figure which showed the example of a relationship between the output voltage and output current in the constant voltage circuit of FIG. It is the figure which showed the example of a relationship between the output voltage and output current in the constant voltage circuit of FIG. It is the circuit diagram which showed the example of the constant voltage circuit in the 2nd Embodiment of this invention. It is the circuit diagram which showed the other example of the constant voltage circuit in the 2nd Embodiment of this invention. It is the circuit diagram which showed the other example of the constant voltage circuit in the 2nd Embodiment of this invention. It is the partial circuit diagram which showed the example of the constant voltage circuit in the 3rd Embodiment of this invention. It is the figure which showed the example of a relationship between the output voltage and output current in the constant voltage circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Constant voltage circuit 2 Overcurrent protection circuit 3 Reference voltage generation circuit 4 Output voltage detection circuit 5 Error amplifier M1-M15, M31 PMOS transistor M16-M27, M32, M33 NMOS transistor R1-R5 Resistance 1a Constant voltage circuit 2a Overcurrent protection Circuit 3a Reference voltage generation circuit 4a Output voltage detection circuit 5a Error amplifier M71 to M76 PMOS transistor M77 to M81 NMOS transistor R71 to R76 Resistance

Claims (18)

An output control transistor for controlling a current output from the output terminal so that an output voltage output from the predetermined output terminal is constant at a predetermined value, and the current output from the output control transistor is In a constant voltage circuit including an overcurrent protection circuit that controls the operation of the output control transistor so as not to exceed a predetermined value,
The overcurrent protection circuit is
A proportional current generation circuit unit that generates a current proportional to the current output from the output control transistor;
A current dividing circuit unit that divides the current output from the proportional current generation circuit unit by a predetermined ratio;
A division ratio control circuit unit for controlling a ratio divided by the current dividing circuit unit;
A current-voltage conversion circuit unit that converts a predetermined one of the currents divided by the current dividing circuit unit into a voltage and outputs the voltage;
An output current control circuit unit that performs output current control on the output control transistor in accordance with the voltage converted by the current-voltage conversion circuit unit;
With
When the output voltage of the current-voltage conversion circuit unit reaches a predetermined voltage, the output current control circuit unit suppresses an increase in output current to the output control transistor and is output from the output terminal. When the output voltage drops to a predetermined first limit voltage, the division ratio control circuit unit increases the current supplied to the current-voltage conversion circuit unit and is output from the output control transistor. A constant voltage circuit characterized in that the ratio divided by the current dividing circuit section is changed so that the current decreases.   The overcurrent protection circuit includes a conversion ratio change circuit unit that changes a current-voltage conversion ratio of the current-voltage conversion circuit unit according to an output voltage output from the output terminal, and the conversion ratio change circuit unit includes: When the output voltage output from the output terminal drops to a predetermined second limit voltage, the output voltage of the current-voltage conversion circuit unit increases and the current output from the output control transistor decreases. 2. The constant voltage circuit according to claim 1, wherein the current-voltage conversion ratio of the voltage conversion circuit section is changed.   The constant voltage circuit according to claim 2, wherein the first limit voltage is set to be larger than the second limit voltage.   4. The constant voltage circuit according to claim 1, wherein the current-voltage conversion circuit unit includes a plurality of resistors for converting a current into a voltage.   The conversion ratio changing circuit unit includes a switch element that short-circuits a predetermined resistance of the current-voltage conversion circuit unit, and the switch element performs switching according to an output voltage output from the output terminal, and the switching element 5. The constant voltage circuit according to claim 4, wherein a combined resistance value of the current-voltage conversion circuit unit is changed to change a current-voltage conversion ratio of the current-voltage conversion circuit unit.   6. The constant voltage circuit according to claim 4, wherein a resistance value of at least one resistor of the current-voltage conversion circuit unit is set by trimming.   The proportional current generation circuit unit includes a first transistor that is a transistor having a reduced transistor size of the output control transistor, and the first transistor outputs a current proportional to the current output from the output control transistor. The constant voltage circuit according to claim 1, 2, 3, 4, 5 or 6.   The current dividing circuit unit is configured by a plurality of transistors each having a voltage corresponding to an output voltage output from the output terminal, which is input to a control signal input terminal, and each of the transistors is output from the proportional current generation circuit unit 8. The constant voltage circuit according to claim 1, wherein a current corresponding to the transistor size ratio is output and a current corresponding to a transistor size ratio is output.   The current dividing circuit unit is configured such that a predetermined transistor is connected to the current-voltage conversion circuit unit among the transistors, and a switching element is connected to a predetermined transistor among the other transistors. 9. The ratio control circuit unit controls the ratio divided by the current dividing circuit unit by controlling switching of the switch element in accordance with a voltage output from the output terminal. Constant voltage circuit. A reference voltage generation circuit for generating and outputting a predetermined reference voltage;
An output voltage detection circuit that detects an output voltage output from a predetermined output terminal and generates and outputs a voltage proportional to the detected output voltage; and
An error amplifier for controlling the operation of the output control transistor with a voltage output by amplifying a voltage difference between the reference voltage and the voltage output from the output voltage detection circuit;
With
The reference voltage generation circuit includes:
A second transistor comprising a depletion type NMOS transistor in which the gate and the source are short-circuited;
A third transistor comprising an enhancement type NMOS transistor in which the gate and drain are short-circuited;
Have
The second transistor and the third transistor are connected in series, the drain of the second transistor is connected to the positive power supply voltage side of the DC power supply, and the source of the third transistor is connected to the negative power supply voltage side of the DC power supply. 4. The constant voltage circuit according to claim 2, wherein the constant voltage circuit is connected and outputs the reference voltage from a connection portion of the second transistor and the third transistor.   The division ratio control circuit unit includes a fourth transistor that is turned on when an output voltage output from the output terminal exceeds the first limit voltage and that is the same type as the third transistor and has a larger transistor size than the third transistor. And when the fourth transistor is turned off, the current is divided by the current dividing circuit unit so that the current supplied to the current-voltage conversion circuit unit is increased and the current output from the output control transistor is decreased. The constant voltage circuit according to claim 10, wherein the ratio is changed.   The conversion ratio changing circuit section is turned on when an output voltage output from the output terminal exceeds the second limit voltage, and is the same type as the fourth transistor and has a transistor size larger than or equal to the fourth transistor. A fifth transistor having a small value voltage, and when the output voltage output from the output terminal decreases to the second limit voltage and the fifth transistor is turned off, the output voltage of the current-voltage conversion circuit unit increases. 12. The constant voltage circuit according to claim 10, wherein the current-voltage conversion ratio of the current-voltage conversion circuit unit is changed so that the current output from the output control transistor decreases.   Each of the fourth transistor and the fifth transistor includes a plurality of MOS transistors and at least one fuse connected in series to a predetermined MOS transistor of each MOS transistor, and selectively disconnects the fuse. 13. The constant voltage circuit according to claim 12, wherein transistor sizes are respectively set.   A current mirror circuit section for supplying currents corresponding to the currents flowing through the second transistor and the third transistor to the fourth transistor and the fifth transistor, respectively, and threshold voltages of the fourth transistor and the fifth transistor; 13. The constant voltage circuit according to claim 12, wherein the transistor sizes of the second transistor, the fourth transistor, and the fifth transistor are set so as to cancel the temperature characteristics of each β value.   A conversion ratio changing circuit unit that changes a current-voltage conversion ratio of the current-voltage conversion circuit unit according to an output voltage output from the output terminal, the conversion ratio changing circuit unit being output from the output terminal; The current-voltage conversion ratio of the current-voltage conversion circuit unit is changed so that the current output from the output control transistor decreases in accordance with a decrease in the output voltage. The constant voltage circuit according to 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14.   The conversion ratio changing circuit unit changes the ratio divided by the current dividing circuit unit so that the current output from the output control transistor decreases when the output voltage decreases to a predetermined third limit voltage. The constant voltage circuit according to claim 15.   The conversion ratio changing circuit unit changes a ratio divided by the current dividing circuit unit so that a current output from the output control transistor further decreases when the output voltage decreases to a predetermined fourth limit voltage. The constant voltage circuit according to claim 16.   The first limit voltage is set to be higher than the second limit voltage, the second limit voltage is set to be higher than the third limit voltage, and the third limit voltage is set to be higher than the fourth limit voltage. The constant voltage circuit according to claim 17.

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