JP4051007B2 - Shift register circuit and display device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a shift register circuit and a display device using the same, and more particularly to a TFT active matrix display such as a liquid crystal display, and also to a shift register circuit for driving the display.
[0002]
[Prior art]
In recent years, TFT-LCDs using polycrystalline silicon (p-Si) have a scan line driver circuit and a signal line driver circuit that use a shift register circuit as a basic circuit in order to reduce costs and ensure reliability. On the same substrate as the display portion substrate, it is formed simultaneously with a thin film transistor for driving the display portion. Such simultaneous formation on the same substrate is also performed in an amorphous silicon (a-Si) TFT-LCD, which brings various advantages including cost reduction.
[0003]
However, in the a-Si TFT, when a voltage higher (lower) than the first terminal and the second terminal (source terminal and drain terminal) is continuously applied to the gate terminal, the threshold value of the TFT is high ( There is a unique problem of threshold shift that shifts towards the lower), and it is necessary to avoid this. Moreover, it has been found that not only a-Si TFTs but also organic TFTs have similar problems.
[0004]
[Patent Document 1]
JP 2002-258819 A
A shift register circuit using an a-Si TFT is described in, for example, Patent Document 1, but this circuit is a generally called ratio circuit, and a through current flows during operation. Is not enough.
[0005]
[Patent Document 2]
JP 2002-215118 A
Further, as an example of a dynamic ratioless shift register circuit using a p-Si TFT but having no through current, Patent Document 2 previously filed by the present applicant is cited. However, since this circuit has p-Si TFTs in mind, the countermeasures against threshold shift that a-Si TFTs and organic TFTs described above have are insufficient.
[0006]
Here, the dynamic ratioless shift register circuit described in Patent Document 2 is shown in FIG. 16, and the timing chart of the circuit is shown in FIG.
[0007]
When φIN changes from L to H between times t0 and t1, NMT3 gated by φIN is turned ON, and its ON output is VSS, so NMT2 gated by VSS is turned OFF. Therefore, N1 is in a floating state. Also, the diode connection NMT1 for inputting φIN becomes conductive, and the voltage VN1 of N1 drops by the threshold voltage Vth of NMT1 to VN1 = Vφ−Vth (where Vφ is φIN or the synchronization pulses φ1, φ2 Voltage).
[0008]
When the threshold voltage Vth of NMT7 connected to N1 is set so that VN1> Vth, NMT7 is also turned on and NMT6 is turned off, so that N3 enters a floating state. At this time, only the gates of NMT4 and NMT8 connected to the synchronization pulses φ1 and φ2 are in a floating state.
[0009]
When φ2 changes from L to H at time t2, since NMT4 is in an ON state since φIN is H, N2 voltage VN2 = Vφ. At this time, the voltage of N1 rises to VN1 = (Vφ−Vth) + Vφ (CB / (CB + Cs)) by the action of the bootstrap capacitor CB1. However, CB is a capacity of CB1, and Cs is a stray capacity. Further, when NMT4 is turned on, diode-connected NMT5 becomes conductive and VN3 = Vφ−Vth. As a result, NMT11 having N3 as a gate is turned ON, the voltage of N11 is changed from H to L, NMT15 having N11 as a gate is turned OFF, and N6 is in a floating state.
[0010]
At time t3, φ1 changes from L to H, and φ2 changes from H to L. At this time, in order for VN2 to change from H to L, when φ2 changes from H to L, the gate potential N1 of NMT4 needs to be at the H level. Since N1 becomes L slightly later than t3 for the reason described later, φ2 changes from H to L while N1 is H, and VN2 changes from H to L. At this time, VN3 is maintained at H by the action of the diode connection NMT5. When φ1 changes from L to H, the voltage of N4 becomes VN4 = Vφ through NMT8 in the ON state. Further, NMT16 is turned on upon receiving the output of diode connection NMT9 conducted by VN4, N14 changes from H to L, NMT20 is turned off in response to this change, and N9 enters a floating state.
[0011]
At the same time, VN5 = Vφ−Vth is obtained by the diode-connected NMT10. As a result, NMT2 having N5 as a gate is turned on and N1 and VSS are connected, and NMT4 is forcedly turned off with its gate connected to VSS. However, since NMT10 is diode-connected, a delay effect is produced, and the potential of VN5 does not rise instantaneously but reaches Vφ−Vth with a slight delay. For this reason, as described above, the gate potential of NMT4 becomes L slightly later than time t3. Since NMT10 is diode-connected, VN5 maintains the H state even when VN4 = L thereafter. That is, until the φIN becomes H again, the forced OFF state in which the gate of NMT4 is connected to VSS is maintained.
[0012]
At time t4, φ2 changes from L to H, and φ1 changes from H to L. φ1 changes from H to L and VN4 changes from H to L, but VN6 maintains H. By changing φ2 from L to H, the voltage VN7 of N7 becomes Vφ through NMT12 in the ON state. Due to the diode-connected NMT13, VN9 = Vφ−Vth. As a result, NMT21 having N9 as a gate is turned on, N17 is changed from H to L, NMT25 is turned off, and N12 is brought into a floating state.
[0013]
At the same time, VN8 = Vφ−Vth is obtained by the diode-connected NMT14. As a result, NMT6 having N8 as a gate is turned on, N3 and VSS are connected, and NMT8 is forcedly turned off with its gate connected to VSS. Since NMT14 is diode-connected, VN8 maintains the H state even when VN7 = L thereafter. That is, until φIN becomes H again, the forced OFF state in which the gate of NMT8 is connected to VSS is maintained. Thereafter, the above operation is sequentially repeated to operate the shift register.
[0014]
The shift register configured as described above has a configuration in which all gates of MOS transistors unnecessary for operation among MOS transistors connected to the synchronization pulses φ1 and φ2 are connected to VSS. For this reason, MOS transistors unnecessary for operation can be forcibly turned off, so that occurrence of unstable operation can be avoided.
[0015]
[Problems to be solved by the invention]
The shift register circuit described in Patent Document 2 includes a circuit that keeps unselected nodes at a low level in order to achieve stable operation. For example, in order to keep the node N3 at the low level, the gate of NMT6 is used as the output VN8 in the subsequent stage, and the gate of NMT6 is kept on for as long as possible, so that the node N3 which is a floating node is connected to VSS To stabilize and to stabilize.
[0016]
However, the operation that continues to apply a high level to the gate of NMT6 in this way is not only DC stress in a-Si TFTs and organic TFTs, but also causes threshold shifts in TFTs such as NMT6. End up.
[0017]
The present invention provides a dynamic ratioless shift register circuit capable of stabilizing a floating node while reducing the operating duty of a TFT and applying a DC stress as much as possible, and a display device using the same. With the goal.
[0018]
[Means for Solving the Problems]
In order to solve the above problems, the specific configuration of the invention according to claims 1 and 2 is shown in FIG. 13, and will be described with reference to FIG. 1 which is a more specific configuration.
[0019]
Provided with a shift register circuit (20) on the substrate surface of the display unit,
The shift register circuit is configured by connecting a first stage circuit (21) and a plurality of basic circuits (22), and the shift register circuit includes a start pulse (φIN), a first basic pulse (φ1), a first The second basic pulse (φ2) and the first to fourth auxiliary pulses (φ2CA, φ1CA, φ2CB, φ1CB) in reverse phase with the basic pulse are input, and pulses are sequentially output from the basic circuits,
In the basic circuit, the first terminal of the first TFT (NMT4) serves as a first input unit, the gate terminal of the first TFT is the first terminal of the first capacitor (CB1), the third terminal TFT (NMT2) first terminal, connected to the second terminal and gate terminal of the fifth TFT (NMTC1) to be the discharge circuit (23), the second input unit and the third output unit (24 )
The second terminal of the first TFT is connected to the first terminal and gate terminal of the second TFT (NMT5), the second terminal of the first capacitor, and serves as a first output unit.
The second terminal of the second TFT is the second output unit,
The gate terminal of the third TFT and the second terminal of the fourth TFT (NMT3) are connected to become a fourth input unit,
The gate terminal of the fourth TFT becomes the third input unit,
The second terminal of the third TFT and the first terminal of the fourth TFT are equal to or at least equal to a voltage that is a source voltage of the TFT among the voltages of the first and second basic pulses. Connected to a fixed power supply or ground potential that is not different from the voltage that is the voltage of the first and second basic pulses above the threshold voltage of 1 TFT,
The first terminal of the fifth TFT is the fifth input unit,
The start pulse is input to the first terminal of the TFT (NMT1) in the first stage circuit, the first basic pulse is input to the gate terminal thereof, and the second terminal of the TFT is the output unit.
In the basic circuit of each stage,
In the first input unit, the first basic pulse or the second basic pulse is alternately input sequentially for each stage,
The second input section is connected to the second output section of the previous basic circuit.
The third input section is connected to the third output section of the previous basic circuit.
The fourth input part is connected to the first output part of the basic circuit of the next stage,
In the fifth input section, any one of the first to fourth auxiliary pulses is sequentially input for each stage,
In the basic circuit of the first stage, the second input unit is connected to the output unit of the first stage circuit, the start pulse is input to the third input unit,
The high period of the auxiliary pulse is longer than the period of the basic pulse, the period of the auxiliary pulse is twice the period of the basic pulse, and the phase of each auxiliary pulse is It is characterized in that the signals are different for each half cycle (FIG. 2).
[0020]
Next, FIG. 13 shows a specific configuration of the invention described in claims 1 and 2, and this configuration includes a shift register circuit (20) on the substrate surface of the display unit,
The shift register circuit includes a discharge circuit (23),
In the discharge circuit, a TFT to which a first terminal and a gate terminal are connected is connected to a floating node (N1, 24) of the shift register circuit,
The second terminal of the TFT is connected to a clear pulse (φ2CA, φ1CA, φ2CB, φ1CB) which is a signal in which a ground level periodically appears.
[0022]
Claim 2 A specific configuration of the invention described in FIG. 9 is shown in FIG. 1 The connection relationship of the second TFT of the basic circuit in the invention of the invention is changed,
The gate terminal of the second TFT is connected to the second terminal of the first TFT and the second terminal of the first capacitor,
The first terminal of the second TFT is connected to a fixed power source equal to the voltage that becomes the drain voltage of the TFT among the voltages of the first and second basic pulses.
[0023]
Claim 3 The specific configuration of the invention according to claim is as follows. 1 The first stage circuit in the invention of FIG.
The first terminal and gate terminal of the TFT (NMT1) in the first stage circuit are connected to the start pulse, and the second terminal of the TFT serves as the output part of the first stage circuit.
[0024]
Claim 4 The specific configuration of the invention according to claim 1 is the scanning line drive shift register 3 shown in FIG. 1 This invention is applied.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a display device according to the present invention will be described in detail with reference to the drawings. FIG. 4 is a schematic diagram showing the overall configuration of the liquid crystal display device according to the present invention. This display device includes a display unit 1, a signal data writing circuit 2, and a scanning line drive shift register 3. In the display unit 1 formed on the glass substrate, the pixel units 4 are arranged in a matrix. The pixel unit 4 has a structure in which a thin film transistor (TFT) 7 exists at the intersection of the scanning line 5 and the signal line 6. The scanning line 5 is connected to the gate terminal of the TFT 7, the data line 6 is connected to the first terminal, and the pixel electrode 8 is connected to the second terminal. Note that the first terminal and the second terminal of the TFT are described separately, but there is no functional difference between the two terminals. A liquid crystal layer 9 is sandwiched between the pixel electrode 8 and the counter electrode 10. The counter electrode 10 is held at a predetermined potential by a counter electrode driving circuit (not shown).
[0026]
In this circuit, the signal data writing circuit 2 is an individual integrated circuit using single crystal silicon or the like, and is connected to a terminal portion provided on a glass substrate directly or via a flexible substrate or the like. On the other hand, the scanning line drive shift register 3 is configured using a large number of MOS transistors having the same structure as the TFT 7 and is formed on the glass substrate simultaneously with the display unit 1. In this case, the semiconductor layer of the MOS transistor constituting the TFT 7 and the scanning line drive shift register 3 is amorphous silicon (a-Si), but these transistors have the same problems as the a-Si TFT and the organic TFT. For those, the present invention is equally applicable.
[0027]
FIG. 1 is a circuit diagram showing an embodiment of the scanning line drive shift register 3. FIG. 2 is a timing chart showing the start pulse φIN, synchronization pulses φ1, φ2, and auxiliary pulses φ1CA, φ1CB, φ2CA. , ΦN2CB, each output VN1 to VN17 at nodes N1 to N17 is shown.
[0028]
As shown in FIG. 1, first, the MOS transistor NMT1 has its first terminal connected to the input pulse φIN and its gate terminal connected to φ1, thereby forming an input section. The second terminal of the MOS transistor NMT1 is connected to the gate terminal of the MOS transistor NMT4 and the first terminal of the MOS transistor NMT2, and is connected to the first terminal of the capacitor CB1. This terminal is also connected to the second terminal and gate of NMTC1. The second terminal of the capacitor CB1 is connected to the second terminal of the MOS transistor NMT4, the first terminal and the gate terminal of the MOS transistor NMT5, and forms a first output terminal.
[0029]
The first terminal of the MOS transistor NMT2 is connected to the gate terminal of the MOS transistor NMT7, the gate terminal of the MOS transistor NMT2 and the second terminal of the MOS transistor NMT3 are the gate terminal and the first terminal of the MOS transistor NMT9, The second terminal of the NMT8 is connected to the second terminal of the capacitor CB2, and the second terminal of the capacitor CB2 forms a second output terminal VN5.
[0030]
The second terminal of the MOS transistor NMT2 and the first terminal of the MOS transistor NMT3 are connected to the fixed power supply VSS or the ground potential (GND), and this voltage is one of the high and low voltages of the synchronization pulses φ1 and φ2. It is equal to the voltage that is the source voltage of the MOS transistor NMT23 (the lowest voltage for the n-type, the highest voltage for the p-type), or at least not equal to or higher than the threshold voltage of the MOS transistor NMT4.
[0031]
The first terminal of the MOS transistor NMT4 is connected to the input terminal of the synchronization pulse φ2, and the second terminal of the MOS transistor NMT5 is the gate terminal of the MOS transistor NMT8, the first terminal of the MOS transistor NMT6, and the MOS transistor NMTC2. The capacitor is connected to the second terminal and the gate terminal, and is connected to the first terminal of the capacitor CB2.
[0032]
The first terminal of the MOS transistor NMT6 is connected to the gate terminal of the MOS transistor NMT11, and the first terminal of the MOS transistor NMT11 is connected to the fixed power supply VSS or the ground potential (GND). The first terminal of the MOS transistor NMT8 is connected to the input terminal of the synchronization pulse φ1.
[0033]
The gate terminal of the MOS transistor NMT6 and the second terminal of the MOS transistor NMT7 are connected to the second terminal of the capacitor CB3, the second terminal of the TFT12, the first terminal of the TFT13, and the gate terminal of the TFT13. The terminal of CB3 forms a third output terminal. In the same manner, these connections are repeated.
[0034]
The first terminals of the MOS transistors NMTC1 to NMTC6 are connected to auxiliary pulses φ2CA, φ1CA, φ2CB, φ1CB, respectively, and this connection is repeated periodically thereafter.
[0035]
The operation of the shift register configured as described above will be described below with reference to the timing chart of FIG. In the following description, each MOS transistor is described on the assumption that it is an n-type. However, even if a p-type is used, circuit design is easy if the same means as in the present invention are taken. Vth represents the threshold voltage of the MOS transistor, and Vφ represents the highest voltage (minimum voltage in the case of the p-type) of the synchronization pulses φ1 and φ2.
[0036]
Since φIN is at the H level between times t0 and t1, NMT3 to which φIN is input is turned ON, the output node N5 of NMT3 is connected to VSS (= GND), and the voltage VN5 = VSS of node N5 Therefore, NMT2 in which node N5 is connected to the gate is turned off, and node N1 is in a floating state.
[0037]
Note that a diode-connected MOS transistor NMTC1 is connected to the node N1 and a signal φ2CA is supplied to the NMTC1, but since this φ2CA is at the H level at this time, the presence of the MOS transistor NMTC1 It can be almost ignored to maintain the floating state.
[0038]
When φ1 changes from L to H at the next time t1, φIN is H at this time, and NMT1 is in the ON state, so the voltage VN1 of N1 becomes Vφ1−Vth. When NMT7 for inputting VN1 is set so that Vφ−Vth> Vth, NMT7 is also turned on, N8 and VSS (= VSS) are connected, VN8 = VSS, and N8 as a gate. NMT6 is turned off and N3 is floating.
[0039]
At this time, the diode NMOS transistor NMTC2 is connected to the node N3, and the signal φ1CA is supplied to the NMTC2, but this φ1CA is at the H level at this time, and therefore the presence of the MOS transistor NMTC2 is N3 It is almost negligible to maintain the floating state.
[0040]
When φ2 changes from L to H at time t2, since the gate input of NMT4 is H, NMT4 is in an ON state, the potential of the output node N2 of NMT4 rises, and VN2 = Vφ is set by the bootstrap capacitor CB1. . At this time, N1 is boosted to increase the voltage to VN1 = (Vφ−Vth) + Vφ (CB / (CB + Cs)) (where CB is the bootstrap capacitance and Cs is the stray capacitance), but φIN is H. From the above, since the gate of NMT2 is VSS (= GND), NMT2 maintains forced OFF.
[0041]
Here, the H level voltage of the auxiliary signal φ2CA will be described. For example, when importance is attached to the life and power consumption, it may be set to Vφ. At this time, the charge accumulated in the bootstrap capacitor CB1 also escapes to the φ2CA signal line via the MOS transistor NMTC1, so that the voltage of VN1 at this time is lower than the voltage VN1. However, since the voltage of VN1 only needs to be sufficient to cover the voltage drop due to the threshold value, there is no particular problem even if the H level voltage of φ2CA is set to Vφ. Further, the channel width W of NMTC1 may be designed to be, for example, about 1/10 smaller than other channels. As a result, the on-resistance of NMTC1 is increased, and the amount of charge escaping to the φ2CA power line can be reduced.
[0042]
If the bootstrap effect is important, the H level voltage of φ2CA may be set to about twice Vφ. This is because the voltage of VN1 does not exceed twice Vφ even if boosted by the bootstrap capacitor. The same can be said for the remaining auxiliary pulses φ1CA, φ1CB, and φ2CB.
[0043]
Then, due to the diode-connected NMT5, VN3 = Vφ−Vth. As a result, NMT11 having N3 as a gate is turned on, and N11 is connected to VSS. Then, NMT15 is turned off and N6 is in a floating state. As before, the diode-connected MOS transistor NMTC3 is connected to the node N6, and the signal φ2CB is supplied to the NMTC3. Since this φ2CB is at the H level at this time, the presence of the MOS transistor NMTC3 exists. Is almost negligible in maintaining the floating state of N6.
[0044]
At time t3, φ1 changes from L to H, and φ2 changes from H to L. A little prior to this, φ2 is changed from H to L. Although φ2 changes from H to L and VN2 changes from H to L, VN3 is maintained through H through a diode-connected NMT5. When φ1 changes from L to H, N5 voltage VN5 = Vφ and N6 also becomes H through NMT8 in the ON state. As a result, NMT16 having N6 as a gate is turned on, N14 is connected to VSS, NMT20 is turned off, and N9 is in a floating state.
[0045]
Further, a diode-connected MOS transistor NMTC4 is connected to the node N9, and a signal φ1CB is supplied to the NMTC4. Since this φ1CB is at the H level at this time, the presence of the MOS transistor NMTC4 is N9 It is almost negligible to maintain the floating state.
[0046]
Since VN5 = Vφ, NMT2 having N5 as a gate is turned on and N1 and VSS are connected, and the gate of NMT4 is connected to VSS and turned off. However, since Vφ2 is L prior to this, NMT4 is turned OFF after VN2 becomes L. At this time t3, φ2CA changes from H to L level, so that N1 is connected to L level via a diode-connected MOS transistor NMTC1. Thereafter, φ2CA periodically becomes L level, and the charge of N1 is released through NMTC1 each time, so that N1 can be kept stable at L level.
[0047]
At time t4, φ2 changes from L to H. A little prior to this, φ1 is changed from H to L. φ1 changes from H to L and VN5 changes from H to L. However, since VN6 passes through the diode-connected NMT9, H is maintained. When VN5 becomes L, the gate of NMT2 becomes L and N1 enters a floating state. However, as described above, NMTC1 works to periodically release the charge, so NMT4 is turned off with N1 as the gate. Is kept stable. Further, as φ2 changes from L to H, the voltage of N8 becomes VN8 = Vφ through NMT12 in the ON state.
[0048]
Due to the diode-connected NMT13, VN9 = Vφ−Vth. As a result, NMT21 having N9 as a gate is turned on, N17 is connected to VSS, NMT25 is turned off, and N12 is in a floating state. At this time, a diode-connected MOS transistor NMTC5 is connected to the node N12, and a signal φ2CA is supplied to the NMTC5. Since this φ2CA is at the H level at this time, the presence of the MOS transistor NMTC5 is It is almost negligible in maintaining the floating state of N12.
[0049]
When VN8 = Vφ, NMT6 having N8 as a gate is turned on, N3 and VSS are connected, and NMT8 having N3 connected to the gate is forcibly turned off.
[0050]
At time t4, φ1CA is changed from H to L, so that N3 is connected to the L level via the diode-connected MOS transistor NMTC2. Thereafter, φ1CA periodically becomes L level, and the charge of N3 is released through NMTC2 each time, so that N3 can be kept stable at L level.
[0051]
Thereafter, the above operation is sequentially repeated to operate the shift register.
Since the shift register configured as described above has a mechanism for periodically releasing the charges of the gates of the MOS transistors connected to the synchronization pulses φ1 and φ2, the occurrence of unstable operation can be avoided.
[0052]
Further, as can be seen from FIG. 2, in this circuit, the DC stress takes only one period of the synchronization pulse even if it takes the longest time. Comparing the time during which DC stress is applied to the gate of the MOS transistor, the conventional method has been several milliseconds in at least one frame period, whereas the display device according to the present invention has several tens to hundreds of tens. It is about μs. Thereby, it is possible to prevent the threshold shift and extend the life by several hundred times.
[0053]
Further, the waveform of the auxiliary pulse is not limited to that shown in FIG. 2, and in short, when the potentials of the nodes N1, N3, N6, N9,. The waveform of the auxiliary pulse corresponding to this node may be an H level that does not hinder the potential rise, and may be, for example, the waveform shown in FIG. In FIG. 3, when VN1 is at H level, φ2CA is also at H level. In the following, φ1CA is at H level for VN3, φ2CB for VN6, and φ1CB for VN9.
[0054]
FIG. 5 is a circuit diagram of another embodiment obtained by improving the circuit of FIG. 1. In order to further increase the stability of the floating node, N2 on the opposite side of the bootstrap capacitor CB is also used as a discharge means. , NMTD3 ...). The first terminal and the gate terminal of NMTD1 are connected to N2, and the second terminal is connected to φ2CA, like NMTC1. The operation waveform is the same as that shown in FIG. With such a configuration, it is possible to prevent electric charges from accumulating in CB and to connect the gate line output OUT1 to the L level via the NMTD1, thereby further improving the operation stability. . In addition, since the output of the gate line at the H level can be lowered to the L level using the TFT of NMTD1 and the like, the rise of φ1 and the fall of φ2 (rise of φ2 and φ1 depending on the channel width W of NMTD1) It is also possible to eliminate the interval between the falling edges of. The timing chart in that case is, for example, as shown in FIG.
[0055]
FIG. 7 is a circuit diagram of another embodiment in which the circuit of FIG. 1 is further improved, and FIG. 8 is a timing chart thereof. When the circuit that forms each output after the input unit is viewed as a basic circuit, NMT10 or other corresponding MOS transistors (NMT14, NMT19, NMT24, NMT29, ...) are connected. The MOS transistor NMT10 (or another MOS transistor corresponding to this in another basic circuit) has the first terminal of the MOS transistor NMT6 (or another MOS transistor corresponding to this in another basic circuit). Connected to the first terminal, the gate terminal is connected to the start pulse φIN, and the second terminal is connected to the fixed power supply VSS or the ground potential (GND). The dynamic ratioless shift register configured as described above has the effect of resetting the state of each node to be aligned every time φIN is input.
[0056]
FIG. 9 is a circuit diagram showing another embodiment of the present invention. In FIG. 9, the MOS transistor NMT1 has its first terminal connected to the input pulse φIN and its gate terminal connected to φ1, thereby forming an input section. The second terminal of the MOS transistor NMT1 is connected to the gate terminal of the MOS transistor NMT4 and the first terminal of the MOS transistor NMT2, and is connected to the first terminal of the capacitor CB1. This terminal is also connected to the second terminal and gate of NMTC1. The second terminal of the capacitor CB1 is connected to the second terminal of the MOS transistor NMT4 and the gate terminal of the MOS transistor NMT5, and forms a first output terminal.
[0057]
The first terminal of the MOS transistor NMT2 is connected to the gate terminal of the MOS transistor NMT7. The gate terminal of the MOS transistor NMT2 and the second terminal of the MOS transistor NMT3 are the gate terminal of the MOS transistor NMT9 and the second terminal of the NMT8. And a second output terminal while being connected to the second terminal of the capacitor CB2.
[0058]
The second terminal of the MOS transistor NMT2 is connected to the fixed power supply VSS or the ground potential (GND), and the first terminal of the MOS transistor NMT3 is also connected to the fixed power supply VSS or the ground potential (GND).
[0059]
The first terminal of the MOS transistor NMT4 is connected to the input terminal of the synchronization pulse φ2, and the second terminal of the MOS transistor NMT5 is the gate terminal of the MOS transistor NMT8, the first terminal of the MOS transistor NMT6, and the second terminal of the MOS transistor NMTC2. 2 and the MOS transistor NMTC2 gate terminal, and also connected to the first terminal of the capacitor CB2.
[0060]
The first terminal of the MOS transistor NMT5 is connected to a fixed potential VDD that is the same potential as Vφ. The first terminal of the MOS transistor NMT6 is connected to the gate terminal of the MOS transistor NMT11, and the second terminal of the MOS transistor NMT11 is connected to the fixed power supply VSS or the ground potential (GND). The first terminal of the MOS transistor NMT8 is connected to the input terminal of the synchronization pulse φ1.
[0061]
The gate terminal of the MOS transistor NMT6 and the second terminal of the MOS transistor NMT7 correspond to the second terminal of the other capacitor corresponding to CB1 of the next stage circuit having the same configuration as the circuit described above, corresponding to NMT4. Connected to the second terminal of the other TFT and the gate terminal of the other TFT corresponding to NMT5, and forms an output section, and the first terminal of the other TFT corresponding to NMT5 is VDD It is connected to the. However, the first terminals of the MOS transistors NMTC1 to NMTC6 are connected to auxiliary pulses φ2CA, φ1CA, φ2CB, φ1CB, respectively, and this connection is repeated periodically thereafter.
[0062]
By configuring in this way, the transmission capability of NMT5 (and other TFTs corresponding thereto) is increased compared to the circuit shown in FIG. 1, and the bootstrap capacity can be charged in a shorter time. It leads to the speeding up of the circuit. In the circuit shown in FIG. 9, it is needless to say that a reset MOS can be arranged as in FIG.
[0063]
FIG. 10 shows a circuit configuration for increasing the circuit speed, similar to the circuit shown in FIG. 9. The MOS transistor NMT1 has a first terminal at the input pulse φIN and a gate terminal at the gate terminal. Each is connected to φ1 to form an input section.
[0064]
The second terminal of the MOS transistor NMT1 is connected to the gate terminal of the MOS transistor NMT4 and the first terminal of the MOS transistor NMT2, and is connected to the first terminal of the capacitor CB1. This terminal is also connected to the second terminal and gate of the diode-connected NMTC1. The second terminal of the capacitor CB1 is connected to the second terminal of the MOS transistor NMT4 and the gate terminal of the MOS transistor NMT5, and forms a first output terminal.
[0065]
The first terminal of the MOS transistor NMT2 is connected to the gate terminal of the MOS transistor NMT7. The gate terminal of the MOS transistor NMT2 and the second terminal of the MOS transistor NMT3 are the gate terminal of the MOS transistor NMT9 and the second terminal of the NMT8. The terminal is connected to the second terminal of the capacitor CB2 and forms a second output terminal.
[0066]
The second terminal of the MOS transistor NMT2 is connected to the fixed power supply VSS or the ground potential (GND), and the first terminal of the MOS transistor NMT3 is also connected to the fixed power supply VSS or the ground potential GND.
[0067]
The first terminal of the MOS transistor NMT4 is connected to the input terminal of the synchronization pulse φ2, the second terminal of the MOS transistor NMT5 is connected to the gate terminal of the MOS transistor NMT8 and the first terminal of the MOS transistor NMT6, and the MOS transistor It is connected to the second terminal and gate terminal of NMTC2, and is also connected to the first terminal of CB2.
[0068]
The first terminal of the MOS transistor NMT5 is connected to the synchronization pulse φ2. The first terminal of the MOS transistor NMT6 is connected to the gate terminal of the MOS transistor NMT11, and the first terminal of the MOS transistor NMT11 is connected to the fixed power supply VSS or the ground potential (GND).
[0069]
The first terminal of the MOS transistor NMT8 is connected to the input terminal of the synchronization pulse φ1. The gate terminal of the MOS transistor NMT6 and the second terminal of the MOS transistor NMT7 include the second terminal of the capacitor CB2, the second terminal of the NMT8, and the second terminal having the same configuration as the circuit described above, and The NMT9 is connected to the gate terminal of the NMT9 and forms an output section. The first terminal of the NMT9 is connected to the input terminal of the synchronization pulse φ1.
[0070]
However, the first terminals of the MOS transistors NMTC1, NMTC2, NMTC3, and NMTC4 are connected to auxiliary pulses φ2CA, φ1CA, φ2CB, and φ1CB, respectively, and this connection is repeated periodically thereafter.
[0071]
With this configuration, the same effect as that of the circuit shown in FIG. 9 can be obtained, leading to an increase in circuit speed. In the circuit shown in FIG. 10, it goes without saying that a reset MOS can be arranged as in FIG.
[0072]
In FIG. 11, NMT7, NMT11, NMT16,... In FIG. 7 are omitted. From the viewpoint of stable operation of the circuit, these MOS transistors should be present. It can be omitted for the purpose of reduction or the like. The operation waveform is the same as in FIG.
[0073]
Further, FIG. 12 omits NMT7, NMT11, NMT16,... In FIG. 7 and also omits NMT7, NMT11, NMT16,. I can say that.
[0074]
FIG. 13 is a block diagram showing an embodiment of the present invention. The shift register circuit 20 includes an input terminal for a start pulse φIN, input terminals for two-phase synchronization pulses φ1, φ2, a reference potential VSS input terminal, and outputs. Each output terminal of OUT1... And a floating node 21 are included.
[0075]
Here, the floating node corresponds to each output terminal and is an operation related to its own output among nodes that are not directly connected to any power supply line (connected via a switch element or the like). Other than the above, it is defined as a node that is particularly important to keep at a stable low level.
[0076]
A discharge circuit 23 is connected to each floating node 24. The discharge circuit 23 has an input terminal to which the floating node 24 is connected and a clear pulse (φ1CA, φ2CA, φ1CB, φ2CB) input terminal.
[0077]
The number and waveform of the clear pulses are set according to the waveform required to clear the corresponding floating node 24, the low level appears periodically, and at least the corresponding floating node is at the high level. If it is desirable, the waveform is set so as to be high level.
[0078]
FIG. 14 shows an example of the operation waveform of FIG. 13, where the floating node 24 corresponding to the output OUT1 is the node 1 (N1), and the waveforms of the input pulses and the desired waveforms of OUT1 and N1 are shown.
[0079]
The discharge circuit 23 connected to N1 is connected to the clear pulse φ2CA. The relationship between VN1 and φ2CA is that when the potential of N1 rises and is going to become high level, φ2CA is also at high level and does not hinder its operation. Thereafter, when φ2CA is at the high level, the discharge circuit 22 discharges the charge of N1 during the period of the low level without affecting the potential of N1, and functions to keep it stably at the low level.
[0080]
In any of the embodiments described so far, the input section is not limited to that shown in each circuit diagram. As shown in FIG. 15, the first terminal and the gate of the MOS transistor NMT1. The terminal may be connected to the input terminal of the input pulse φIN, and the same effect can be obtained.
【The invention's effect】
According to the shift register circuit and the display device of the present invention, in the dynamic ratioless shift register circuit, there is no problem of threshold shift and stable operation can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a dynamic ratioless shift register according to an embodiment of the present invention.
FIG. 2 is a timing chart of FIG.
FIG. 3 is a timing chart showing another example of an auxiliary pulse (clear pulse) in the present invention.
FIG. 4 is a schematic view showing the entirety of an embodiment of a display device according to the present invention.
FIG. 5 is a circuit diagram showing another embodiment of the present invention.
FIG. 6 is a timing chart of FIG.
FIG. 7 is a circuit diagram showing another embodiment of the present invention.
FIG. 8 is a timing chart of FIG.
FIG. 9 is a circuit diagram showing another embodiment of the present invention.
FIG. 10 is a circuit diagram showing another embodiment of the present invention.
FIG. 11 is a circuit diagram showing another embodiment of the present invention.
FIG. 12 is a circuit diagram showing another embodiment of the present invention.
FIG. 13 is a dynamic ratioless shift register circuit according to the present invention.
FIG. 14 is a timing chart of FIG.
FIG. 15 is a circuit diagram showing another example of the first stage circuit according to the present invention.
FIG. 16 is a circuit diagram of a conventional dynamic ratioless shift register realized using p-Si TFT.
FIG. 17 is a timing chart of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Display part, 2 ... Signal data writing circuit, 3 ... Scanning line drive shift register circuit, 4 ... Pixel part, 5 ... Scanning line, 6 ... Signal line, 7・ ・ Thin film transistor (TFT), 8 ... Pixel electrode, 9 ... Liquid crystal layer, 10 ... Counter electrode, 20 ... Dynamic ratioless shift register circuit, 21 ... First stage circuit, 22 ... Basic circuit, 23 ... discharge circuit, 24 ... floating node.

Claims (4)

In a shift register circuit in which a plurality of basic circuits are cascade-connected via a floating node following the first stage circuit and driven by two-phase synchronization pulses having different phases ,
A discharge circuit connected to the floating node;
The discharge circuit includes a TFT, a first terminal and a gate terminal of the TFT are connected to the floating node, and a second terminal is connected to receive a clear pulse,
The clear pulse is a four-phase pulse signal having a cycle twice that of the synchronization pulse and having a phase different from each other, periodically having a low level, and a high level when the floating node is at a high level. A shift register circuit characterized by the following waveform . The shift register circuit according to claim 1 , wherein
A shift register circuit, wherein a first terminal of a TFT whose second terminal is connected to a floating node in a basic circuit of the next stage is connected to a fixed power supply (drain voltage). The shift register circuit according to claim 1 , wherein
A first stage circuit includes a TFT having a first terminal to which a start pulse is input, a gate terminal to which a synchronization pulse is input, and a second terminal connected to a floating node, or a first terminal to which a start pulse is input And a second terminal connected to the floating node. A shift register circuit, comprising: In a display device including a shift register circuit in which pixel portions arranged in a matrix are driven by two-phase synchronization pulses having different phases ,
The shift register circuit includes a discharge circuit in which a plurality of basic circuits are cascade-connected via a floating node following the first stage circuit, and is connected to the floating node. The discharge circuit includes a TFT, and the TFT The first terminal and the gate terminal are connected to the floating node, and the second terminal is connected to receive a clear pulse ,
The clear pulse is a four-phase pulse signal having a cycle twice that of the sync pulse and having a phase different from each other, and periodically has a low level, and becomes a high level when the floating node is at a high level A display device characterized by a waveform .

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