JP4052145B2 - Etching method - Google Patents

Description

【００５２】
図４（Ａ）〜（Ｅ）は、半導体レーザ１ｅを製造している状態の一例を示す工程図である。ここでは、まず、基体１ａを準備する。基体１ａは、ｎ型半導体基板９０ａ（基体）上に形成された前述の下部クラッド層２２と第１上部クラッド層２６との間に設けられたＭＱＷ−ＳＣＨ層２４を含むストライプ状メサ構造の両側が、ｐ型ＩｎＰ層３２ａ及びｎ型ＩｎＰ層３４ａで埋め込まれ、更にその上にｐ型ＩｎＰ層２８ａ（第２の半導体層）及びｐ⁺型ＧａＩｎＡｓ層３０ａ（第１の半導体層）が被着されたものである。
【００５３】
この状態の基体１ａを形成する手順は、以下の通りである。最初に、下部クラッド層２２、ＭＱＷ−ＳＣＨ層２４、及び第１上部クラッド層２６で構成されるストライプ状メサ構造を形成すべく、ｎ型半導体基板９０ａの主面上に各層２２，２４，２６を構成する半導体多層膜を、例えば有機金属気相成長法（ＭＯ−ＣＶＤ）等により順次エピタキシャル成長させる。なお、回折格子を設けるときには、例えば、ＭＱＷ−ＳＣＨ層２４の最上層である第４ＳＣＨ層と第１上部クラッド層２６との界面に形成する。
【００５４】
次に、第１上部クラッド層２６上にダミー層としてのキャップ層を設け、ＳｉＮ膜、ＳｉＯ₂膜、ＳｉＯＮ膜等の絶縁膜を形成した後、その上に一定幅のフォトレジストを形成し、所定のパターニングを施す。このレジスト膜をマスクとし、例えばドライエッチングにより一定幅を有するストライプ状の絶縁体マスクを形成する。この絶縁体マスクの延在する方向は、半導体多層膜のオリエンテーションフラットに垂直な方向とされる。
【００５５】
次いで、ダミー層であるキャップ層や半導体多層膜の組成等に応じたエッチング剤を適宜選択し、例えばＧａＩｎＡｓ系又はＩｎＰ系のキャップ層の場合には、リン酸系エッチング液によるウェットエッチを用いて、絶縁体マスクが形成されていないキャップ層の露出部をエッチングして、ストライプを形成させる。さらに、リン酸系エッチング液を洗浄した後、例えば臭素及びエタノールの混合液から成るエッチング液を用い、ｎ型半導体基板９０ａの一部が露出する程度まで、ウェットエッチを施す。これにより、キャップ層及び半導体多層膜の一定の結晶面が露呈するような異方性成分を含むメサエッチングが行われて裾広がりの断面形状を有する各層２２，２４，２６から成るストライプ状メサが形成される。
【００５６】
それから、絶縁体マスクを残した状態で、ｐ型ＩｎＰ層３２ａ及びｎ型ＩｎＰ層３４ａ（それぞれ第２の半導体層）を堆積させる（第２半導体層形成工程）。これらの層の成膜は、例えばＭＯ−ＣＶＤチャンバ（第２半導体層形成部）等を用いたエピタキシャル成長により実施することができる。このとき、絶縁体マスク上には半導体結晶が成長せず、ストライプ状メサの側方が埋め込まれて平坦化される。その後、絶縁体マスク及びその下のエッチングされなかったキャップ層を順次選択除去する。さらに、平坦化されたメサ上の領域にｐ型ＩｎＰ層２８ａ（第２の半導体層）を、例えばＭＯ−ＣＶＤチャンバ（第２半導体層形成部）等を用いてエピタキシャル成長によって形成させる（第２半導体層形成工程）。
【００５７】
それから、更にその上にｐ⁺型ＧａＩｎＡｓ層３０ａ（第１の半導体層）を、例えばＭＯ−ＣＶＤチャンバ（第１半導体層形成部）等を用いてエピタキシャル成長によって形成させる（第１半導体層形成工程）。形成する。それから、ｐ⁺型ＧａＩｎＡｓ層３０ａ上にＳｉＮ膜、ＳｉＯ₂膜、ＳｉＯＮ膜等の絶縁膜を形成した後、更にその上に一定幅のフォトレジストを形成し、所定のパターニングを施す。このレジスト膜をマスクとして用い、例えばドライエッチングにより一定幅を有するストライプ状の絶縁体マスクＭ１を形成し、基体１ａを得る（図４（Ａ）参照）。
【００５８】
この基体１ａをチャンバ１３内のサセプタ上に移載し、ｐ⁺型ＧａＩｎＡｓ層３０ａ、ｐ型ＩｎＰ層２８ａ、ｎ型ＩｎＰ層３４ａ、及びｐ型ＩｎＰ層３２ａをＩＣＰ−ＲＩＥによるドライエッチングに供してトレンチＴを形成する。ここでは、基体１ａが図２に示す半導体基板１２に相当する。また、ＣＨ₄ガス、Ｈ₂ガス、及びＣｌ₂ガス供給源を有するガス導入系Ｇを使用する。
【００５９】
まず、排気系を運転してチャンバ内を所定の圧力に減圧する。圧力が安定した後、制御系１００，１０１から、ガス導入系ＧのＣＨ₄ガス供給源、Ｈ₂ガス供給源、及びＣｌ₂ガス供給源にそれぞれ接続された各ＭＦＣに、所定の弁開度信号を送出する。これにより、チャンバ１３内に、一定の混合比でＣＨ₄／Ｈ₂／Ｃｌ₂混合ガスを供給すると共に、排気系の運転を継続しチャンバ１３内圧力を一定に保持する（ガス供給工程）。
【００６０】
その後、制御系１００，１０１の制御信号により高周波電源１７，１９を運転し、誘導コイル１５及びサセプタ１１に高周波電力を印加する。これにより、チャンバ１３内のサセプタ１１上方の空間にはＩＣＰが形成されてＣＨ₄活性種及び塩素活性種が生じる。それと同時に、サセプタ１１に印加された交流バイアス電圧によってイオン活性種が基体１ａ上に入射し、ｐ⁺型ＧａＩｎＡｓ層３０ａ（第１の半導体層）のドライエッチングが行われる（エッチング工程）。
【００６１】
ここで、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチング及び後述するｐ型ＩｎＰ層２８ａのエッチングにおいては、各種エッチングパラメータのうち高周波電源１７，１９の出力が下記式（１）及び／又は式（２）で表される関係を満たすように、制御系１００によってプロセス条件を調整する。
Ｂａ＜Ｂｂ …（１）
ここでのＢａは、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングにおいて、高周波電源１７からサセプタ１１へ印加する高周波電力の最大バイアス電圧を示し、Ｂｂは、ｐ⁺型ＧａＩｎＡｓ層３０ａの下層であるｐ型ＩｎＰ層２８ａのエッチング（後述）において、高周波電源１７からサセプタ１１へ印加する高周波電力の最大バイアス電圧を示す。
【００６２】
Ｒａ＞Ｒｂ …（２）
ここでのＲａは、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングにおいて、高周波電源１９から誘導コイル１５へ印加する高周波電力（すなわちＩＣＰ出力）を示し、Ｒｂは、ｐ型ＩｎＰ層２８ａのエッチングにおいて、高周波電源１９から誘導コイル１５へ印加する高周波電力を示す。
【００６３】
具体的には、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングは、他のエッチングパラメータを含めて以下のプロセス条件で実施することが好ましい。なお、カッコ内の数値は代表的な値を示す。
ＣＨ₄ガス流量：９〜１３sccm（１０sccm）、
Ｃｌ₂ガス流量：９〜１１sccm（１０sccm）、
Ｈ₂ガス流量：４．５〜５．５sccm（５sccm）、
チャンバ１３内圧力：２〜３Pa（３Pa）、
基体１ａ温度：５０〜８０℃（６０℃）
高周波電源１７（バイアス）出力：１０〜３０W（１０W）、
最大バイアス電圧（シース基準予測値）：８０〜１２０V（８０V）、
高周波電源１９出力（ＩＣＰ出力）：２０００〜４０００W（２０００W）＠１３．６５ＭＨｚ
【００６４】
本発明者の知見によれば、上記カッコ内に示す条件を用いると、ｐ⁺型ＧａＩｎＡｓ層３０ａの深さ方向（層面に垂直な方向）のエッチレートは０．１μｍ／ｍｉｎであることが確認された。なお、同条件でのｐ型ＩｎＰ層２８ａの深さ方向のエッチレートは０．３μｍ／ｍｉｎであり、ｎ型ＩｎＰ層３４ａ、及びｐ型ＩｎＰ層３２ａについてもｐ型ＩｎＰ層２８ａと同等であることが確認された。
【００６５】
このようなｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングでは、サセプタ１１へ印加されるバイアス電圧Ｂａが、ｐ型ＩｎＰ層２８ａのエッチングにおける同バイアス電圧Ｂｂより小さくされるので、ｐ⁺型ＧａＩｎＡｓ層３０ａに対する垂直エッチングに寄与するイオン衝撃エネルギーが緩和される。また、ＩＣＰ出力ＲａがＩＰＣ出力Ｒｂより大きくされるので、ｐ⁺型ＧａＩｎＡｓ層３０ａの等方性エッチングに寄与する活性種密度が増大する。よって、ｐ⁺型ＧａＩｎＡｓ層３０ａの垂直エッチング量が減少すると共にサイドエッチングされ易くなる。したがって、側面が裾広がりのメサ形状を成すコンタクト層３０が形成され、基体１ｂが得られる（図４（Ｂ）参照）。
【００６６】
ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチング時間（プロセスタイム）は、その層厚及びエッチング条件に応じて予め求めておき、その情報を制御系１００に予め記憶させておくか、プロセス毎に制御系１００に適宜の入力手法により入力しておくことができる。前者の場合、ｐ⁺型ＧａＩｎＡｓ層３０ａの層厚、エッチング条件、及びエッチレートの関係を表すテーブル又は関数式を用いてもよい。
【００６７】
また、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングの進行状況を実時間でモニターしながら、その終了時点を判断することもできる。このためには、図２に示すエッチング装置２０が有効である。この場合、光検出器１２０によってチャンバ１３内のプラズマ発光分光スペクトルを測定する。具体的には、Ｉｎの発光ピーク（波長４５１ｎｍ、４１０ｎｍ等）又はＧａの発光ピーク（波長４１７ｎｍ、４０３ｎｍ等）をモニターすることが好ましい。ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングの終了間際つまりｐ⁺型ＧａＩｎＡｓ層３０ａとその下層であるｐ型ＩｎＰ層２８ａとの境界部に達した時点でピーク強度が顕著に低下する。その一方で、Ｉｎの発光は増大し始める。
【００６８】
予め設定したプロセスタイムが経過した後、或いは、Ｇａ及び／又はＩｎの発光ピーク強度の変化からｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングが完了したと判定された後、チャンバ１３内で引き続き、ｐ型ＩｎＰ層２８ａ、ｎ型ＩｎＰ層３４ａ、及びｐ型ＩｎＰ層３２ａ（それぞれ第２の半導体層）のエッチングを順次実施する。ここでは、上記式（１）及び式（２）で表される関係を満たすように制御系１００，１０１でエッチングパラメータを調整する。
【００６９】
具体的には、各ＩｎＰ層２８ａ，３４ａ，３２ａのエッチングは、他のエッチングパラメータを含めて以下のプロセス条件で実施することが好ましい。なお、カッコ内の数値は代表的な値を示す。
ＣＨ₄ガス流量：５〜７sccm（６sccm）、
Ｃｌ₂ガス流量：５〜７sccm（６sccm）、
Ｈ₂ガス流量：２．５〜３．５sccm（３sccm）、
チャンバ１３内圧力：１〜１．５Pa（１．５Pa）、
基体１ｂ温度：５０〜８０℃（６０℃）
高周波電源１７（バイアス）出力：５０〜１００W（５０W）、
最大バイアス電圧（シース基準予測値）：１６０〜２６０V（１６０V）、
高周波電源１９出力（ＩＣＰ出力）：１０００〜１５００W（１０００W）＠１３．６５ＭＨｚ
【００７０】
本発明者の知見によれば、上記カッコ内に示す条件を用いると、ｐ型ＩｎＰ層２８ａの深さ方向（層面に垂直な方向）のエッチレートは０．４μｍ／ｍｉｎであり、ｎ型ＩｎＰ層３４ａ、及びｐ型ＩｎＰ層３２ａについてもｐ型ＩｎＰ層２８ａと同等であることが確認された。なお、同条件でのｐ⁺型ＧａＩｎＡｓ層３０ａの深さ方向のエッチレートは０．１２μｍ／ｍｉｎであることが確認された。
【００７１】
このような各ＩｎＰ層２８ａ，３４ａ，３２ａのエッチングでは、サセプタ１１へ印加されるバイアス電圧Ｂｂが、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングにおける同バイアス電圧Ｂａより大きくされるので、各ＩｎＰ層２８ａ，３４ａ，３２ａに対する垂直エッチングに寄与するイオン衝撃エネルギーが過度に緩和されることがない。
【００７２】
また、ＩＣＰ出力ＲｂがＩＰＣ出力Ｒａより小さくされるので、各ＩｎＰ層２８ａ，３４ａ，３２ａの等方性エッチングに寄与する活性種密度が過度に増大することがない。よって、各ＩｎＰ層２８ａ，３４ａ，３２ａのエッチングでは、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングほどにサイドエッチング量が増えることがなく、且つ垂直エッチング成分が比較的増強される。したがって、若干裾広がりではあるがコンタクト層３０の側面ほどテーパ角度が緩やかではないメサ形状を成す第２上部クラッド層２８、埋込層３４、及び埋込層３２が形成され、基体１ｃを得る（エッチング工程；図４（Ｃ）参照）。
【００７３】
ｎ型半導体基板９０ａの上層の一部がエッチングされてｎ型半導体基板９０が形成された時点でエッチングを終了し、絶縁体マスクＭ１を選択除去した後、基体１ｃ上にＳｉＮ膜を一様に形成する。次いで、そのＳｉＮ膜上にフォトレジストを形成し、コンタクト層３０上部に一定幅のストライプ状開口部が形成されるように所定のパターニングを施す。次に、このレジスト膜をマスクとして例えばドライエッチングを行い、コンタクト層３０上に一定幅のストライプ状開口部を有する絶縁体層６０を形成して基体１ｄを得る（図４（Ｄ）参照）。それから、基体１ｄ上に金属膜を堆積させてｐ型オーミック電極層５０を形成し、半導体レーザ１ｅを得る（図４（Ｅ）参照）。
【００７４】
このとき、コンタクト層３０の側壁が突出しておらず、‘庇’の無いメサ形状が形成されているので、庇Ｈが障害となってメサ側壁上に金属が堆積し難くなるといった不都合を解消できる。したがって、絶縁体層６０及びｐ型オーミック電極層５０がメサ側壁全面を十分に覆うようにコンフォーマルに形成され、その結果、ｐ型オーミック電極層５０の断切れによる断線を抑止できる。
【００７５】
また、このような本発明のエッチング方法によれば、同一のチャンバ１３内でのドライエッチング処理で、ｐ⁺型ＧａＩｎＡｓ層３０ａ、ｐ型ＩｎＰ層２８ａ、ｎ型ＩｎＰ層３４ａ、及びｐ型ＩｎＰ層３２ａといった複数の半導体層を有する積層体にメサ形状を簡易に形成することができる。さらに、ドライエッチングのみでエッチング工程を行うので、ウェットエッチングとドライエッチングとを組み合わせる場合と比べても工程を格段に簡略化できる。さらに、ドライエッチングのみでエッチング工程を実施するので、深さ方向の形状制御性に優れた加工が可能となる。
【００７６】
以上、本発明をその実施形態に基づいて詳細に説明したが、本発明は上記の各実施形態に限定されるものではない。本発明は、その要旨を逸脱しない範囲で様々な変形が可能である。例えば、本発明は、半導体レーザ１ｅのみならず、他の半導体装置、例えばフォトダイオード、光増幅器、受光素子、マッハツェンダ型変調器、光導波器、合波器、分波器といった他の素子又はそれらの素子の複合装置の製造に有効である。
【００７７】
また、下記式（３）；
Ｘ１＞Ｘ２ …（３）、
で表される関係を満たすように、ガス導入系Ｇの各ＭＦＣの開度を調節してＣＨ₄ガス、Ｈ₂ガス、及びＣｌ₂ガスのチャンバへの各供給流量を調整すると好ましい。ここで、式中、Ｘ１はｐ⁺型ＧａＩｎＡｓ層のエッチングにおけるエッチングガス（混合ガス）中のＣｌ₂ガスの混合比を示し、Ｘ２はｐ型ＩｎＰ層２８ａ、ｎ型ＩｎＰ層３４ａ、及びｐ型ＩｎＰ層３２ａのエッチングにおけるエッチングガス中のＣｌ₂ガスの混合比を示す。
【００７８】
塩素活性種のｐ⁺型ＧａＩｎＡｓ層３０ａに対する反応性は、各ＩｎＰ層２８ａ，ＩｎＰ層３４ａ，及びＩｎＰ層３２ａに対する反応性よりも高い。よって、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチレートがｐ型ＩｎＰ層２８ａよりも大きくされ、ｐ⁺型ＧａＩｎＡｓ層３０ａのサイドエッチを行い易くなる。これに対し、各ＩｎＰ層２８ａ，３４ａ，３２ａでは、エッチングガスにＣＨ₄ガスを混合しないとエッチレートが不都合な程に低下してしまう。また、Ｃｌ₂ガスのみを用いて各ＩｎＰ層２８ａ，３４ａ，３２ａのエッチングを行うと、エッチング面の‘あれ’が生じ易い傾向にある。
【００７９】
より好ましくは、Ｘ１を１００容積％（質量流量％）、及びＸ２を１００容積％未満、特に好ましくは実質的に０容積％とする。つまり、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチングには実質的にＣｌ₂ガスのみ用いてＣＨ₄ガス及びＨ₂ガスを使用しない一方で、各ＩｎＰ層２８ａ，３４ａ，３２ａのエッチングには、ＣＨ₄／Ｈ₂／Ｃｌ₂混合ガス、又はＣＨ₄／Ｈ₂混合ガスを使用すると好適である。
【００８０】
この際、制御系１００，１０１から、ガス導入系ＧのＣＨ₄ガス源及びＨ₂ガス源に接続されたＭＦＣに対し質量流量ゼロ信号を送出してこれらガスの供給を停止する。この場合、エッチングガスはＣｌ₂ガス単独となり、チャンバ１３内に主に塩素活性種のみが生じる。塩素活性種のｐ⁺型ＧａＩｎＡｓ層３０ａに対する反応性は、ｐ型ＩｎＰ層２８ａ、ｎ型ＩｎＰ層３４ａ、及びｐ型ＩｎＰ層３２ａに対する反応性よりも高い。よって、ｐ⁺型ＧａＩｎＡｓ層３０ａのエッチレートがｐ型ＩｎＰ層２８ａよりも大きく、ｐ⁺型ＧａＩｎＡｓ層３０ａのサイドエッチを行い易い。これに対し、各ＩｎＰ層２８ａ，３４ａ，３２ａでは、エッチングガスにＣＨ₄ガスを混合しないとエッチレートが不都合な程に低下してしまう。また、Ｃｌ₂ガスのみを用いて各ＩｎＰ層２８ａ，３４ａ，３２ａのエッチングを行うと、エッチング面の‘あれ’が生じ易い傾向にある。
【００８１】
【発明の効果】
以上説明したように、本発明のエッチング方法及びエッチング装置、並びに半導体装置の製造方法及びその製造装置によれば、複数の半導体層を有する積層体にメサ形状を簡易に形成することができ、そのメサ上に設けられる保護膜や電極の断線を防止でき、しかも形状制御性を向上させることができる。
【図面の簡単な説明】
【図１】本発明に用いられるエッチング装置の好適な一実施形態を模式的に示す構成図である。
【図２】本発明に用いられるエッチング装置の好適な他の実施形態を模式的に示す構成図である。
【図３】本発明のエッチング方法を適用して製造される半導体装置の一例を示す模式断面図である。
【図４】（Ａ）〜（Ｅ）は、半導体レーザ１ｅを製造している状態の一例を示す工程図である。
【図５】（Ａ）〜（Ｄ）は、一度のドライエッチングによりメサ形状を有する半導体装置を製造する従来方法の手順の一例を示す工程図である。
【符号の説明】
１ｅ…半導体レーザ（半導体装置）、１ａ，１ｂ，１ｃ，１ｄ…基体、１０，２０…エッチング装置、１１…サセプタ、１２…半導体基板（基体）、１３…チャンバ、１４…高周波導入窓、１５…誘導コイル（高周波誘導コイル）、１６，１８…インピーダンス整合器、１７…高周波電源（バイアス用電源）、１９…高周波電源（高周波電源部）、２２…下部クラッド層、２４…ＭＱＷ−ＳＣＨ層、２６…第１上部クラッド層、２８…第２上部クラッド層、２８ａ…ｐ型ＩｎＰ層２８ａ（第２の半導体層）、３０…コンタクト層、３０ａ…ｐ⁺型ＧａＩｎＡｓ層（第１の半導体層）、３２，３４…埋込層、３２ａ…ｐ型ＩｎＰ層（第２の半導体層）、３４ａ…ｎ型ＩｎＰ層（第２の半導体層）、５０…ｐ型オーミック電極層、５２ｎ型オーミック電極層、６０…絶縁体層、１００，１０１…制御系（制御部）、１２０…光検出器（光検出部）、Ｇ…ガス導入系（ガス供給部）、Ｈ…庇、Ｋ_in…ガス導入口、Ｋ_out…ガス排出口、Ｍ１…絶縁体マスク、Ｔ…トレンチ、Ｗ…光透過窓。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an etching method and apparatus, and a semiconductor device manufacturing method and manufacturing apparatus.
[0002]
[Prior art]
In recent years, in an optical communication system that provides high-speed optical communication, a further increase in communication speed has been eagerly desired, and a high-performance semiconductor optical device such as a semiconductor laser device constituting such a system is required. Such a semiconductor optical device is generally provided with a buried layer as a current confinement portion on both sides of an optical waveguide mesa including an active layer formed on a semiconductor substrate, on which a cladding layer and a contact layer are deposited. It has the structure which was made. The side wall of the buried layer is processed into a taper shape that spreads in the bottom in order to limit the light emitting region and sufficiently reduce the capacitance of the device. That is, each semiconductor optical device has a mesa shape as a whole, and when a plurality of devices are arranged, a trench is provided between the devices.
[0003]
Conventionally, mesa formation in a stack of a plurality of semiconductor layers is usually performed by a single etching process. Specifically, for example, (1) a method of forming a mesa by providing a mask on the uppermost layer upper surface of a plurality of III-V compound semiconductor multilayer films and performing wet etching to the lowermost layer with a Br-based etchant or the like ( For example, refer to the prior art in Patent Document 1). Alternatively, as a method using multi-stage etching, (2) a method in which the multilayer film is etched stepwise from the upper layer to the lower layer, and the mask formation and wet etching are repeated while gradually changing the etching mask to a wider one. Has been proposed (see, for example, Patent Document 1). Furthermore, (3) a method using a single dry etching process is also conceivable.
[0004]
[Patent Document 1]
JP 2001-28455 A
[0005]
[Problems to be solved by the invention]
However, as pointed out in the description of the prior art in Patent Document 1, the method of the above-mentioned wet etching (1) has a lower ethylate than the lower layer depending on the material of the uppermost layer. The so-called '庇' that protrudes to the side of the lower layer is formed. In this case, the protective film or electrode layer deposited so as to cover the mesa side wall from the upper wall to the bottom surface of the convex portion is broken, and the element is not established. In addition, when wet etching is used, the dimension and shape controllability of the multilayer film particularly in the depth direction tends to be inferior to that of dry etching.
[0006]
On the other hand, the method (2) has been proposed in order to prevent the protective film and electrode layer from being cut due to the formation of '庇'. However, in order to form a mesa, mask formation and wet etching are performed. It is necessary to repeat the number of layers. Therefore, the number of steps increases, which is not necessarily preferable from the viewpoint of ease of manufacture. Furthermore, the method (3) reduces the number of steps because mesa formation is performed once, and is superior in dimension and shape controllability in the depth direction because of dry etching. However, in this method, like the method (1), ‘庇’ tends to be easily formed. This will be described more specifically.
[0007]
FIGS. 5A to 5D are process diagrams showing an example of a procedure of a conventional method for manufacturing a semiconductor device (element) having a mesa shape by dry etching once. The base 2a has a stripe shape including an active layer 224 provided between an n-type InP lower clad layer 222 and a p-type InP first upper clad layer 226 formed on a semiconductor substrate 290a made of n-type InP. Both sides of the mesa are embedded with a p-type InP layer 232a and an n-type InP layer 234a, and further, a p-type InP layer 228a and p⁺A type GaInAs layer 230a is deposited.
[0008]
First, an insulator mask M1 having a predetermined width is formed on the substrate 2a and patterned (see FIG. 5A). Next, CH_Four/ H₂Mixed gas or CH_Four/ H₂/ Cl₂Using a mixed gas as an etchant, dry etching is performed under a constant pressure and plasma conditions in which an isotropic component is strengthened by high frequency induction plasma reactive ion (dry) etching (ICP-RIE) or the like. As a result, a mesa shape is formed, and the contact layer 230, the second upper cladding layer 228, and the buried layers 234 and 232 are formed in order from the upper layer (state of the base body 2b; see FIG. 5B).
[0009]
At this time, since the etching rate of GaInAs is smaller than InP, the side etching amount of the p-type InP layer 228a is p.⁺It tends to be less than the type GaInAs layer 230a. Therefore, wrinkles H are likely to occur in the lower part of the peripheral edge of the insulator mask M1 in the second upper cladding layer 228. Subsequently, the insulator mask M1 is removed and an insulating film is formed, and then a part of the insulating film on the upper surface of the contact layer 230 is etched to form the insulating layer 260 (state of the base 2c; FIG. 5 (C)).
[0010]
Then, a metal film is further deposited thereon to form the electrode layer 150 so as to cover the structure, and the semiconductor laser 2d is obtained. However, since the side wall of the contact layer 230 protrudes on both sides to form 庇 H (in other words, the mesa has a shape recessed inward), the 庇 H becomes an obstacle and the metal on the mesa side wall is formed. Is difficult to deposit. As a result, the electrode layer 150 is disconnected and the wiring is disconnected, which may cause no function as an element (see FIG. 5D).
[0011]
Therefore, the present invention has been made in view of such circumstances, and a mesa shape can be easily formed in a stacked body having a plurality of semiconductor layers, and a protective film or electrode breakage provided so as to cover the mesa. It is an object of the present invention to provide an etching method and apparatus capable of preventing the above-described problem and having excellent dimensional and shape controllability, and a method and apparatus for manufacturing a semiconductor device having such a mesa structure.
[0012]
[Means for Solving the Problems]
  In order to solve the above problems, an etching method according to the present invention is a method of forming a mesa shape by etching a substrate including a first semiconductor layer and a second semiconductor layer different from the first semiconductor layer. A gas supply step of supplying an etching gas into the chamber in which the substrate is accommodated, a bias voltage is applied to the substrate, and a high frequency power is applied to the chamber, thereby causing high frequency induction plasma (hereinafter referred to as “ICP”). And a bias voltage used for etching each of the first semiconductor layer and the second semiconductor layer when the etching process is performed, ICP The high frequency power for forming, the high frequency for forming the ICP, the flow rate of the etching gas, and when the etching gas is a mixed gas At least one of the mixing ratio of each gas, and a control step for varying independently of each other based on the physical and / or chemical characteristics of the first semiconductor layer and the second semiconductor layer.
  Furthermore, in this invention, in a control process, following formula (1) and formula (2);
Ba <Bb (1),
  Ba: a bias voltage used for etching a semiconductor layer having a relatively low etch rate when an etching gas is used among the first semiconductor layer and the second semiconductor layer,
  Bb: bias voltage used for etching a semiconductor layer having a relatively high etch rate when an etching gas is used among the first semiconductor layer and the second semiconductor layer,
Ra> Rb (2),
  Ra: high frequency power used for etching a semiconductor layer having a relatively low etch rate when an etching gas is used among the first semiconductor layer and the second semiconductor layer,
  Bb: high frequency power used for etching a semiconductor layer having a relatively high etch rate when an etching gas is used among the first semiconductor layer and the second semiconductor layer,
At least one of the bias voltage and the high frequency power is changed independently of each other so as to satisfy at least one of them.
  Alternatively, in the present invention, the first semiconductor layer mainly includes at least a Ga element. III A second semiconductor layer mainly containing no Ga element and containing an In element. III -V group compound semiconductor, and the etching gas is CH ₄ Gas, H ₂ Gas and Cl ₂ In the control step using a mixed gas containing gas, the following formula (3);
X1> X2 (3),
  X1: mainly the first III The Cl in the mixed gas used for etching the first semiconductor layer made of a group V compound semiconductor ₂ Gas mixing ratio,
  X2: mainly the second III The Cl in the mixed gas used for etching the second semiconductor layer made of a group V compound semiconductor ₂ Gas mixing ratio,
The CH in the gas supply step so as to satisfy the relationship represented by ₄ Gas, H ₂ Gas, and said Cl ₂ The supply flow rate of gas to the chamber is adjusted.
[0013]
In this etching method, a mesa is formed by dry etching once in an etching process on a substrate having at least a first and a second semiconductor layer. In the etching process, based on the characteristics of the first semiconductor layer and the second semiconductor layer, the etching parameters for each layer (bias voltage, high frequency power, flow rate of etching gas, and etching gas are mixed gas). In this case, at least one of the mixing ratios of the respective gases is appropriately changed.
[0014]
In other words, different process conditions are applied at the time of etching the first semiconductor layer and the second semiconductor layer. For example, when the first semiconductor layer is on the upper layer side with respect to the base with respect to the second semiconductor layer, it is possible to arbitrarily select and use the conditions such that the former side etching amount is larger than the latter. it can. By doing so, the formation of “庇”, which has been a problem in the prior art, is suppressed in the first semiconductor layer. In addition, since plasma etching by ICP is used, the active species density (concentration) and thus the reactivity are enhanced as compared with plasma formation by other discharge types. Therefore, the side etching efficiency can be enhanced, and the side etching amount can be delicately controlled by changing the plasma conditions.
[0015]
Specifically, in the control step, it is preferable to use the chemical composition (the constituent elements or the composition ratio of each element) of each of the first semiconductor layer and the second semiconductor layer as the “characteristic”.
[0016]
In dry etching, an active species (especially an ionic active species) derived from an etchant gas reacts with a constituent component to be etched (RIE), and the generated volatile substance is removed from the system and etching proceeds. Conceivable. If the chemical composition of the first semiconductor layer and the second semiconductor layer, for example, the constituent elements (component elements) are different, the degree of volatility differs for each reaction product of the active species and each element, so there is a difference in the etch rate. Tend to occur. In the mesa formation, the difference in the side etch rate is an especially important factor for the formation of the above-mentioned '庇'. Even if the types of constituent elements are the same, a difference in etch rate may occur in the same manner due to a difference in composition ratio (stoichiometry) of each element. Therefore, it is effective to appropriately select the etching parameters based on the chemical compositions of both layers.
[0017]
In addition to the chemical composition, the crystal structure of each layer, hardness, in-film composition distribution, electrical or electromagnetic characteristics, conditions for film formation, post-treatment such as a modification step after film formation, etc. In such cases, those based on factors that may affect the film quality and film characteristics of the first semiconductor layer or the second semiconductor layer, such as subsequent processing conditions, are also included in the “physical or chemical characteristics” in the present invention. included.
[0018]
More directly, in the control step, it is useful to use the respective etch rates in the first semiconductor layer and the second semiconductor layer when the etching gas is used as the “characteristic”. As described above, since the etch rate is governed by the reactivity between the active species in the plasma and the constituent components, the etch rate and therefore the side etching amount differ depending on the type of etching gas. Therefore, it is useful to obtain in advance the etching rates of the first semiconductor layer and the second semiconductor layer for each etching gas used prior to the actual process.
[0019]
Furthermore, in the control step, the following formula (1) and formula (2);
Ba <Bb (1)
Ra> Rb (2)
It is preferable to change at least one of the bias voltage and the high-frequency power independently of each other so that at least one of them, preferably both, is satisfied.
[0020]
Here, in the formula, Ba represents a bias voltage used in etching of the first semiconductor layer and the second semiconductor layer, which has an etching rate with a relatively low etching rate when the etching gas is used, and Bb represents the first semiconductor layer. A bias voltage used for etching of the semiconductor layer and the second semiconductor layer having a relatively large etching rate when the etching gas is used is shown. Ra represents the high-frequency power used for etching of the first semiconductor layer and the second semiconductor layer having an etching rate with a relatively low etching rate when using the etching gas, and Bb represents the first semiconductor layer and the second semiconductor layer. 2 shows high-frequency power used for etching of a semiconductor layer having a relatively large etching rate when the etching gas is used.
[0021]
When the bias voltage applied to the substrate is increased or decreased, the energy of the ion active species drawn into the first semiconductor layer and the second semiconductor layer side on the substrate, that is, the vertical as the anisotropic component (perpendicular to the layer surface, The ion bombardment energy contributing to the etching increases or decreases. Further, when the high-frequency power applied to the chamber, that is, the ICP output is increased or decreased, the density of active species in the plasma sheath contributing to isotropic etching increases or decreases.
[0022]
Therefore, taking as an example the case where the etch rate of the first semiconductor layer is smaller than the etch rate of the second semiconductor layer, the bias voltage for the first semiconductor layer is set to satisfy the formula (1). Since the ratio of the vertical component in the etching of the first semiconductor layer is reduced, the ratio of the isotropic component is relatively increased, and the amount of side etching of the first semiconductor layer within the same time is reduced. Will increase.
[0023]
On the other hand, when the high frequency power applied to the chamber for the first semiconductor layer is made larger than that for the second semiconductor layer so as to satisfy the formula (2), the absolute amount of active species increases, and the ratio of the isotropic component Is relatively enhanced. Therefore, the side etch amount within the same time increases. Furthermore, if both the formula (1) and the formula (2) are satisfied, the side etch amount in the first semiconductor layer is further increased by these synergistic effects.
[0024]
More specifically, it is particularly useful when the first semiconductor layer and the second semiconductor layer are made of different types of III-V group compound semiconductors.
[0025]
Furthermore, the first semiconductor layer is mainly composed of a first III-V group compound semiconductor containing at least Ga element, and the second semiconductor layer is mainly composed of a first element not containing Ga element and containing In element. It is more useful when it consists of two III-V group compound semiconductors. If the first semiconductor layer is a layer (usually an upper layer) that is etched before the second semiconductor layer, the generation of '庇' becomes a problem, and the present invention is particularly useful in that case. is there.
[0026]
Here, in the first group III-V compound semiconductor, Ga may or may not be a main component. The second group III-V compound semiconductor is substantially free of Ga, but includes a semiconductor containing a small amount of Ga as an inevitable component.
[0027]
CH often used in dry etching of III-V semiconductors_Four/ H₂Mixed gas or CH_Four/ H₂/ Cl₂Taking a mixed gas as an example, In is more CH than chlorine active species._FourDerived active species (hereinafter referred to as “CH_FourIt is called “active species”. ) Is highly reactive, while Ga is CH_FourThe reactivity with the active species tends to be significantly low. Therefore, when such an etching gas is used, the etching rate of the first III-V compound semiconductor containing Ga as an essential constituent element is the second III-- containing no In and containing In as an essential constituent element. Significantly smaller than Group V compound semiconductors. Therefore, the present invention is extremely effective in such a case.
[0028]
More specifically, the first semiconductor layer is mainly made of GaAs, GaInAs, GaInAsP, or GaInP, and the second semiconductor layer is mainly made of InP.
[0029]
In this case, the etching gas is CH_FourGas, H₂Gas and Cl₂In the control process using a mixed gas containing gas, the following formula (3);
X1> X2 (3),
CH in the gas supply process so as to satisfy the relationship represented by_FourGas, H₂Gas and Cl₂It is more preferable to adjust the flow rate of the gas supplied to the chamber. Here, in the formula, X1 is Cl in a mixed gas used for etching the first semiconductor layer mainly composed of the first III-V group compound semiconductor containing at least Ga element.₂The gas mixing ratio, X2 being Cl in the mixed gas used for etching the second semiconductor layer mainly composed of the second group III-V compound semiconductor not containing Ga element and containing In element₂The gas mixing ratio is shown.
[0030]
More preferably, X1 is 100% by volume (mass flow rate%), and X2 is less than 100% by volume, particularly preferably substantially 0% by volume. In other words, the etching of the first semiconductor layer mainly composed of the first III-V compound semiconductor is substantially Cl.₂CH using only gas_FourGas and H₂In the etching of the second semiconductor layer mainly composed of the second group III-V compound semiconductor while using no gas,_Four/ H₂/ Cl₂Mixed gas or CH_Four/ H₂Use a mixed gas.
[0031]
As described above, In is more CH than chlorine active species._FourWhile the reactivity with active species is high, Ga is CH_FourReactivity with active species tends to be relatively low. Conversely, In is CH_FourIn contrast to the active species, the reactivity with the chlorine active species is low, whereas Ga has a relatively high reactivity with the chlorine active species. This is GaCl_ThreeInCl_ThreeSince the saturated vapor pressure of InCl is low, InCl is produced by the reaction between In and chlorine active_ThreeIs difficult to desorb from the substrate, whereas GaCl is produced by the reaction of chlorine and chlorine active species._ThreeThis is because it is easily detached from the substrate. Therefore, CH is satisfied so as to satisfy equation (3)._Four/ H₂/ Cl₂If the mixing ratio (mass flow rate ratio) of each gas in the mixed gas is adjusted, the side etch amount of the first semiconductor layer increases.
[0032]
Further, as an apparatus for effectively carrying out such an etching method according to the present invention, a mesa shape is formed by etching a substrate including a first semiconductor layer and a second semiconductor layer different from the first semiconductor layer. An apparatus to be formed, which is connected to a chamber in which a substrate is accommodated, a gas supply unit that supplies an etching gas into the chamber, and is connected to the chamber, and a bias voltage is applied to the substrate. At least one of a bias power supply unit to be applied, a high frequency induction coil provided in the chamber, a high frequency power supply unit connected to the high frequency induction coil, a bias power supply unit, a high frequency power supply unit, and a gas supply unit A bias voltage used for etching each of the first semiconductor layer and the second semiconductor layer, high frequency power for forming ICP, and I At least one of the high-frequency frequency for forming P, the flow rate of the etching gas, and the mixing ratio of each gas when the etching gas is a mixed gas is the physical and / or the first semiconductor layer and the second semiconductor layer. Or what is provided with the control part adjusted so that it may mutually change based on a chemical characteristic is mentioned.
[0033]
Preferably, a light detection unit that detects light emitted from the chamber and connected to the control unit is provided, and the control unit starts or ends etching of the first semiconductor layer, or The time when the etching of the semiconductor layer 2 starts or ends is determined based on the detection signal from the light detection unit (the intensity of the specific wavelength light in the spectral spectrum).
[0034]
For example, when shifting from the etching of the first semiconductor layer to the etching of the second semiconductor layer, the reaction products of the constituent components of the two layers and the etchant are different, so that the plasma emission in the chamber is spectroscopically measured. Thus, the transition point is reliably determined. Therefore, desired etching can be reliably performed on both semiconductor layers by changing the etching conditions based on the determination result.
[0035]
A method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device (element) having a plurality of semiconductor layers and having a mesa shape, and is intended to promote an increase in communication and / or modulation speed. A first semiconductor layer forming step of forming a first semiconductor layer on one side of the substrate, and a method for forming the first substrate on the substrate can be widely applied to the manufacture of a semiconductor device (element) in which a mesa shape can be formed in order to reduce the element capacitance. A second semiconductor layer forming step of forming a second semiconductor layer different from the first semiconductor layer on the side, and dry etching the first semiconductor layer and the second semiconductor layer on the substrate by the etching method according to the present invention; A method including an etching step is preferable.
[0036]
The semiconductor device formed on the substrate is a single or single type of semiconductor element (for example, a photodiode, a semiconductor laser element, an optical amplifier, a light receiving element, a Mach-Zehnder modulator, an optical waveguide, a multiplexer, a demultiplexer). The semiconductor device is not limited to a container, etc., and may be a monolithic structure in which a plurality or types of semiconductor elements are formed.
[0037]
The semiconductor device manufacturing apparatus is a device for manufacturing a semiconductor device having a plurality of semiconductor layers and having a mesa shape, wherein the first semiconductor layer is formed on one side of the substrate. It is preferable to include a semiconductor layer forming portion, a second semiconductor layer forming portion in which a second semiconductor layer different from the first semiconductor layer is formed on one side of the substrate, and the etching apparatus according to the present invention.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. For the convenience of illustration, the dimensional ratios in the drawings are not limited to the values shown in the drawings, and do not necessarily match those described. Further, the positional relationship such as up, down, left and right is based on the positional relationship in the drawings unless otherwise specified.
[0039]
FIG. 1 is a configuration diagram schematically showing a preferred embodiment of an etching apparatus used in the present invention. The etching apparatus 10 includes a chamber 13 for generating ICP therein. Inside the chamber 13 is provided a susceptor 11 on which a semiconductor substrate 12 (base body) is placed. The chamber 13 has a gas inlet K._in, Gas outlet K_outAnd a high-frequency introduction window 14.
[0040]
Gas inlet K_inIs CH_FourGas, H₂Gas and Cl₂This is an opening for introducing an etching gas composed of a gas into the chamber 13. This gas inlet K_inThe gas introduction system G (gas supply part) which has the supply source of each gas and those individually connected mass flow controllers (MFC) is connected to. Gas outlet K_outIs an opening for exhausting the gas in the chamber 13. This gas outlet K_outAn exhaust system (not shown) including a turbo pump and an exhaust amount adjustment valve for adjusting the exhaust conductance is connected to the exhaust system.
[0041]
Further, the susceptor 11 incorporates a heater (not shown) and is connected with a coolant circulation pipe 110. As a result, the susceptor 11 is heated and held at a desired constant temperature, or cooled and maintained below a desired constant temperature. Furthermore, a high frequency power source 17 (bias power source) for applying bias high frequency power to the susceptor 11 is connected to the susceptor 11 via an impedance matching unit (matching network) 16. The high-frequency introduction window 14 that forms the upper wall of the chamber 13 is formed of a dielectric, and passes a high-frequency electromagnetic field generated by an induction coil 15 (high-frequency induction coil) installed outside the chamber 13 into the chamber 13. It is for making it happen. A high frequency power supply 19 (high frequency power supply unit) for applying high frequency power to the induction coil 15 is connected to the induction coil 15 via an impedance matching unit 18. The high frequency power supplies 17 and 19 are each grounded to a predetermined same potential.
[0042]
Furthermore, a control system 100 (control unit) is connected to each MFC of the gas introduction system G and the high-frequency power sources 17 and 19. The control system 100 is for independently controlling the opening of the flow rate adjustment valve of each MFC and the outputs of the high frequency power supplies 17 and 19, and each operation recipe (condition) is input or stored in advance. Alternatively, it is appropriately input by an input means (not shown).
[0043]
FIG. 2 is a block diagram schematically showing another preferred embodiment of the etching apparatus used in the present invention. The etching apparatus 20 is provided with a light transmission window W that can face the inside of the chamber 13, and a photodetector 120 (photodetection) disposed opposite to the light transmission window W and having a spectroscopic function. And a control system 101 (control unit) connected to each MFC of the gas introduction system G, the high-frequency power sources 17 and 19, and the photodetector 120 instead of the control system 100. 1 is configured in the same manner as the etching apparatus 10 shown in FIG. As will be described later, a spectral output signal from the photodetector 120 is input to the control system 101, and the operating states of the MFCs and the high-frequency power sources 17 and 19 are controlled based on the signal.
[0044]
An etching method according to the present invention using the etching apparatuses 10 and 20 thus configured will be described. Note that the procedure when the etching apparatus 10 is used will be mainly described, and different procedures when the etching apparatus 20 is used will be referred to as appropriate.
[0045]
FIG. 3 is a schematic cross-sectional view showing an example of a semiconductor device manufactured by applying the etching method of the present invention. In the semiconductor device 1, a plurality of semiconductor lasers 1 e are separated by trenches T and integratedly arranged on one n-type semiconductor substrate 90. Each semiconductor laser 1e includes a lower clad layer 22 made of n-type InP sequentially deposited on one side of a semiconductor substrate 90 made of n-type InP, and a layer 24 having a multiple quantum well-separated confinement structure (MQW-SCH). , And a first upper cladding layer 26 made of p-type InP. Each of these layers 22, 24, and 26 is a mesa type III-V group compound semiconductor layer, and a striped mesa structure composed of a III-V group semiconductor multilayer film is formed therefrom. The lower clad layer 22, the upper clad layer 26, and the upper clad layer 28 described later are for confining light generated in the MQW-SCH layer 24 in the MQW-SCH layer 24, and all are from the MQW-SCH layer 24. Has a low refractive index.
[0046]
The MQW-SCH layer 24 is a multilayer semiconductor in which, for example, a first SCH layer, a second SCH layer, an active layer, a third SCH layer, and a fourth SCH layer are sequentially stacked from the lower cladding layer 22 toward the first upper cladding layer 26. Each layer is made of, for example, quaternary compound semiconductor InGaAsP. Although the detailed structure is not shown, the first SCH layer and the fourth SCH layer have the same band gap and form a separate confinement heterostructure in pairs. Further, the second SCH layer and the third SCH layer also have the same band gap different from those of the first SCH layer and the fourth SCH layer, and form a separated confinement heterostructure in pairs. Further, the active layer sandwiched between the second SCH layer and the third SCH layer has a multiple quantum well (MQW) structure in which a plurality of barrier layers and a plurality of well layers are alternately stacked.
[0047]
The MQW-SCH layer 24 thus configured has a refractive index distribution similar to the band gap wavelength distribution. Note that the band gap wavelength distribution and refractive index distribution of each layer are realized by appropriately adjusting the composition of InGaAsP. In addition, the active layer in the MQW-SCH layer 24 is preferably an undoped semiconductor, whereby a semiconductor layer (for example, i layer) having a relatively low carrier concentration is formed. However, it may be an n-type or p-type semiconductor layer whose carrier concentration is absolutely lower than that of the adjacent layer.
[0048]
As the semiconductor laser 1e, a vertical structure (resonator structure) capable of obtaining a desired oscillation spectrum according to the application, for example, a Fabry-Perot structure, a DFB structure, a DBR structure, or the like is appropriately adopted. In the case of the DFB structure and the DBR structure, the interface between the MQW-SCH layer 24 and the first upper cladding layer 26, more specifically, the fourth SCH layer and the first upper cladding layer that are the uppermost layers of the MQW-SCH layer 24. For example, a uniform diffraction grating (not shown) having a sine wave cross section, for example, is provided at the interface with 26. This diffraction grating is formed on the upper surface of the fourth SCH layer, for example, and constitutes a laser resonator. The diffraction grating may be provided at the interface between the first SCH layer and the lower cladding layer 22 described above. In the case of the Fabry-Perot structure, a reflecting mirror surface using a crystal edge is used instead of the diffraction grating.
[0049]
Further, both side surfaces of the lower clad layer 22, the MQW-SCH layer 24, and the first upper clad layer 26 are buried layers 32 made of p-type InP and buried layers 34 made of n-type InP laminated thereon. Covered with. Further thereon, a second upper clad layer 28 made of p-type InP is deposited. Note that an n-type current blocking layer may be interposed between the second upper cladding layer 28 and the buried layer 34.
[0050]
Furthermore, a predetermined region on the second upper cladding layer 28 includes p⁺A contact layer 30 made of type InGaAs is formed. In addition, an insulating layer 60 having an opening in a part on the contact layer 30 is deposited from the upper surface of the contact layer 30 to the surface of the n-type semiconductor substrate 90, and a p-type ohmic as an upper electrode is further formed thereon. An electrode layer 50 is provided. Further, an n-type ohmic electrode layer 52 as a lower electrode is provided on the lower surface of the n-type semiconductor substrate 90. The second upper cladding layer 28 may have higher p-type conductivity than the first upper cladding layer 26, and the n-type semiconductor substrate 90 has higher n-type conductivity than the lower cladding layer 22. You may have. Here, Table 1 shows an example of specific dimensions of each layer constituting the semiconductor laser 1e.
[0051]
[Table 1]

[0052]
4A to 4E are process diagrams showing an example of a state in which the semiconductor laser 1e is manufactured. Here, first, the base 1a is prepared. The base 1a has both sides of a striped mesa structure including the MQW-SCH layer 24 provided between the lower clad layer 22 and the first upper clad layer 26 formed on the n-type semiconductor substrate 90a (base). Is buried with a p-type InP layer 32a and an n-type InP layer 34a, and a p-type InP layer 28a (second semiconductor layer) and a p-type InP layer 28a are further formed thereon.⁺A type GaInAs layer 30a (first semiconductor layer) is deposited.
[0053]
The procedure for forming the substrate 1a in this state is as follows. First, in order to form a striped mesa structure composed of the lower cladding layer 22, the MQW-SCH layer 24, and the first upper cladding layer 26, each layer 22, 24, 26 is formed on the main surface of the n-type semiconductor substrate 90a. Is sequentially epitaxially grown by, for example, metal organic chemical vapor deposition (MO-CVD). When the diffraction grating is provided, for example, it is formed at the interface between the fourth SCH layer, which is the uppermost layer of the MQW-SCH layer 24, and the first upper cladding layer 26.
[0054]
Next, a cap layer as a dummy layer is provided on the first upper cladding layer 26, and a SiN film, SiO 2₂After forming an insulating film such as a film or a SiON film, a photoresist having a certain width is formed thereon and subjected to predetermined patterning. Using this resist film as a mask, a striped insulator mask having a certain width is formed by dry etching, for example. The extending direction of the insulator mask is a direction perpendicular to the orientation flat of the semiconductor multilayer film.
[0055]
Next, an etching agent corresponding to the composition of the cap layer, which is a dummy layer, and the semiconductor multilayer film is appropriately selected. For example, in the case of a GaInAs-based or InP-based cap layer, wet etching using a phosphoric acid-based etching solution is used. Then, the exposed portion of the cap layer where the insulator mask is not formed is etched to form a stripe. Further, after the phosphoric acid-based etching solution is washed, wet etching is performed using, for example, an etching solution made of a mixed solution of bromine and ethanol until a part of the n-type semiconductor substrate 90a is exposed. As a result, a mesa etching including an anisotropic component that exposes a certain crystal plane of the cap layer and the semiconductor multilayer film is performed, so that a striped mesa composed of the layers 22, 24, and 26 having a flared cross-sectional shape is obtained. It is formed.
[0056]
Then, the p-type InP layer 32a and the n-type InP layer 34a (each second semiconductor layer) are deposited with the insulator mask left (second semiconductor layer forming step). These layers can be formed by epitaxial growth using, for example, an MO-CVD chamber (second semiconductor layer forming portion) or the like. At this time, the semiconductor crystal does not grow on the insulator mask, and the side of the stripe mesa is buried and flattened. Thereafter, the insulator mask and the unetched cap layer underneath are selectively removed. Further, a p-type InP layer 28a (second semiconductor layer) is formed in the region on the planarized mesa by epitaxial growth using, for example, an MO-CVD chamber (second semiconductor layer forming portion) or the like (second semiconductor). Layer forming step).
[0057]
Then p on it⁺The type GaInAs layer 30a (first semiconductor layer) is formed by epitaxial growth using, for example, an MO-CVD chamber (first semiconductor layer forming portion) or the like (first semiconductor layer forming step). Form. Then p⁺SiN film, SiO on the GaInAs layer 30a₂After an insulating film such as a film or a SiON film is formed, a photoresist having a certain width is further formed thereon, and predetermined patterning is performed. Using this resist film as a mask, a striped insulator mask M1 having a certain width is formed by dry etching, for example, to obtain a substrate 1a (see FIG. 4A).
[0058]
This substrate 1a is transferred onto the susceptor in the chamber 13, and p⁺The trench T is formed by subjecting the type GaInAs layer 30a, the p-type InP layer 28a, the n-type InP layer 34a, and the p-type InP layer 32a to dry etching by ICP-RIE. Here, the base 1a corresponds to the semiconductor substrate 12 shown in FIG. CH_FourGas, H₂Gas and Cl₂A gas introduction system G having a gas supply source is used.
[0059]
First, the exhaust system is operated to reduce the pressure in the chamber to a predetermined pressure. After the pressure is stabilized, the control system 100, 101 sends the CH of the gas introduction system G_FourGas supply source, H₂Gas supply and Cl₂A predetermined valve opening signal is sent to each MFC connected to each gas supply source. As a result, the CH 13 has a constant mixing ratio with CH._Four/ H₂/ Cl₂While supplying the mixed gas, the operation of the exhaust system is continued to keep the pressure in the chamber 13 constant (gas supply step).
[0060]
Thereafter, the high frequency power supplies 17 and 19 are operated by the control signals of the control systems 100 and 101 to apply high frequency power to the induction coil 15 and the susceptor 11. As a result, an ICP is formed in the space above the susceptor 11 in the chamber 13 and CH_FourActive species and chlorine active species are generated. At the same time, the ion active species is incident on the substrate 1a by the AC bias voltage applied to the susceptor 11, and p⁺The type GaInAs layer 30a (first semiconductor layer) is dry-etched (etching step).
[0061]
Where p⁺In the etching of the type GaInAs layer 30a and the etching of the p-type InP layer 28a described later, among the various etching parameters, the relationship between the outputs of the high-frequency power sources 17 and 19 is expressed by the following formula (1) and / or formula (2). The process condition is adjusted by the control system 100 so as to satisfy.
Ba <Bb (1)
Ba here is p⁺In the etching of the GaInAs layer 30a, the maximum bias voltage of the high frequency power applied from the high frequency power supply 17 to the susceptor 11 is shown, and Bb is p⁺The maximum bias voltage of the high frequency power applied from the high frequency power supply 17 to the susceptor 11 in the etching (described later) of the p type InP layer 28a, which is the lower layer of the type GaInAs layer 30a, is shown.
[0062]
Ra> Rb (2)
Ra here is p⁺In the etching of the p-type InP layer 28a, Rb is applied from the high-frequency power source 19 to the induction coil 15 in the etching of the p-type InP layer 28a. Indicates high frequency power.
[0063]
Specifically, p⁺The etching of the type GaInAs layer 30a is preferably performed under the following process conditions including other etching parameters. The numerical values in parentheses are representative values.
CH_FourGas flow rate: 9-13 sccm (10 sccm),
Cl₂Gas flow rate: 9-11 sccm (10 sccm),
H₂Gas flow rate: 4.5-5.5 sccm (5 sccm),
Pressure in the chamber 13: 2 to 3 Pa (3 Pa)
Substrate 1a temperature: 50 to 80 ° C. (60 ° C.)
High frequency power supply 17 (bias) output: 10 to 30 W (10 W),
Maximum bias voltage (sheath reference predicted value): 80 to 120V (80V),
High-frequency power supply 19 output (ICP output): 2000 to 4000 W (2000 W) @ 13.65 MHz
[0064]
According to the inventor's knowledge, using the conditions shown in parentheses above, p⁺It was confirmed that the etch rate in the depth direction (direction perpendicular to the layer surface) of the type GaInAs layer 30a was 0.1 μm / min. Note that the etch rate in the depth direction of the p-type InP layer 28a under the same conditions is 0.3 μm / min, and the n-type InP layer 34a and the p-type InP layer 32a are also equivalent to the p-type InP layer 28a. It was confirmed.
[0065]
Such p⁺In the etching of the type GaInAs layer 30a, the bias voltage Ba applied to the susceptor 11 is made smaller than the same bias voltage Bb in the etching of the p-type InP layer 28a.⁺The ion bombardment energy contributing to the vertical etching with respect to the type GaInAs layer 30a is relaxed. Further, since the ICP output Ra is made larger than the IPC output Rb, p⁺The density of active species contributing to the isotropic etching of the type GaInAs layer 30a increases. Therefore, p⁺The vertical etching amount of the type GaInAs layer 30a is reduced and the side etching is facilitated. Therefore, a contact layer 30 having a mesa shape with side surfaces spreading is formed, and the substrate 1b is obtained (see FIG. 4B).
[0066]
p⁺The etching time (process time) of the type GaInAs layer 30a is obtained in advance according to the layer thickness and etching conditions, and the information is stored in the control system 100 in advance, or the control system 100 appropriately stores the information for each process. It can be input by an input method. In the former case, p⁺A table or a functional expression representing the relationship between the layer thickness of the GaInAs layer 30a, the etching conditions, and the etching rate may be used.
[0067]
P⁺The end point can be determined while monitoring the progress of the etching of the GaInAs layer 30a in real time. For this purpose, the etching apparatus 20 shown in FIG. 2 is effective. In this case, the plasma emission spectrum in the chamber 13 is measured by the photodetector 120. Specifically, it is preferable to monitor the In emission peak (wavelength 451 nm, 410 nm, etc.) or the Ga emission peak (wavelength 417 nm, 403 nm, etc.). p⁺Immediately before the etching of the p-type GaInAs layer 30a, that is, p⁺When the boundary between the p-type InP layer 28a, which is the lower layer of the p-type GaInAs layer 30a, is reached, the peak intensity is significantly reduced. On the other hand, the emission of In begins to increase.
[0068]
After a preset process time has elapsed or from the change in the emission peak intensity of Ga and / or In, p⁺After it is determined that the etching of the p-type GaInAs layer 30a is completed, the p-type InP layer 28a, the n-type InP layer 34a, and the p-type InP layer 32a (each second semiconductor layer) are continuously etched in the chamber 13. Implement sequentially. Here, the etching parameters are adjusted by the control systems 100 and 101 so as to satisfy the relationship expressed by the above formulas (1) and (2).
[0069]
Specifically, the etching of each InP layer 28a, 34a, 32a is preferably performed under the following process conditions including other etching parameters. The numerical values in parentheses are representative values.
CH_FourGas flow rate: 5-7 sccm (6 sccm),
Cl₂Gas flow rate: 5-7 sccm (6 sccm),
H₂Gas flow rate: 2.5-3.5 sccm (3 sccm),
Pressure in the chamber 13: 1 to 1.5 Pa (1.5 Pa)
Substrate 1b temperature: 50 to 80 ° C. (60 ° C.)
High frequency power supply 17 (bias) output: 50 to 100 W (50 W),
Maximum bias voltage (sheath reference predicted value): 160 to 260 V (160 V),
High frequency power supply 19 output (ICP output): 1000-1500 W (1000 W) @ 13.65 MHz
[0070]
According to the knowledge of the present inventor, when the conditions shown in the parentheses are used, the etch rate in the depth direction (direction perpendicular to the layer surface) of the p-type InP layer 28a is 0.4 μm / min, and n-type InP It was confirmed that the layer 34a and the p-type InP layer 32a are equivalent to the p-type InP layer 28a. P under the same conditions⁺It was confirmed that the etch rate in the depth direction of the type GaInAs layer 30a was 0.12 μm / min.
[0071]
In such etching of each InP layer 28a, 34a, 32a, the bias voltage Bb applied to the susceptor 11 is p.⁺Since the bias voltage Ba is higher than the bias voltage Ba in the etching of the type GaInAs layer 30a, the ion bombardment energy contributing to the vertical etching with respect to each InP layer 28a, 34a, 32a is not excessively relaxed.
[0072]
Further, since the ICP output Rb is made smaller than the IPC output Ra, the density of active species contributing to the isotropic etching of the InP layers 28a, 34a, 32a is not excessively increased. Therefore, in the etching of each InP layer 28a, 34a, 32a, p⁺The side etching amount does not increase as much as the etching of the type GaInAs layer 30a, and the vertical etching component is relatively enhanced. Accordingly, the second upper clad layer 28, the buried layer 34, and the buried layer 32 having a mesa shape with a slightly wider skirt but with a taper angle that is not as gentle as the side surface of the contact layer 30 are formed, thereby obtaining the substrate 1c ( Etching step; see FIG. 4C).
[0073]
When a part of the upper layer of the n-type semiconductor substrate 90a is etched to form the n-type semiconductor substrate 90, the etching is finished, and after selectively removing the insulator mask M1, a SiN film is uniformly formed on the substrate 1c. Form. Next, a photoresist is formed on the SiN film, and predetermined patterning is performed so that a stripe-shaped opening having a constant width is formed on the contact layer 30. Next, using this resist film as a mask, for example, dry etching is performed to form an insulator layer 60 having a stripe-shaped opening having a certain width on the contact layer 30 to obtain a substrate 1d (see FIG. 4D). Then, a metal film is deposited on the substrate 1d to form the p-type ohmic electrode layer 50, thereby obtaining the semiconductor laser 1e (see FIG. 4E).
[0074]
At this time, since the side wall of the contact layer 30 does not protrude and a mesa shape without '庇' is formed, the inconvenience that the metal becomes difficult to deposit on the mesa side wall due to the 庇 H can be solved. . Therefore, the insulator layer 60 and the p-type ohmic electrode layer 50 are formed conformally so as to sufficiently cover the entire surface of the mesa side wall, and as a result, disconnection due to breakage of the p-type ohmic electrode layer 50 can be suppressed.
[0075]
Further, according to the etching method of the present invention, p is obtained by dry etching in the same chamber 13.⁺A mesa shape can be easily formed in a stacked body including a plurality of semiconductor layers such as a type GaInAs layer 30a, a p type InP layer 28a, an n type InP layer 34a, and a p type InP layer 32a. Furthermore, since the etching process is performed only by dry etching, the process can be greatly simplified as compared with the case where wet etching and dry etching are combined. Furthermore, since the etching process is performed only by dry etching, processing with excellent shape controllability in the depth direction can be performed.
[0076]
As mentioned above, although this invention was demonstrated in detail based on the embodiment, this invention is not limited to said each embodiment. The present invention can be variously modified without departing from the gist thereof. For example, the present invention includes not only the semiconductor laser 1e but also other semiconductor devices such as photodiodes, optical amplifiers, light receiving elements, Mach-Zehnder type modulators, optical waveguides, multiplexers, duplexers, or the like. It is effective for the manufacture of a composite device of these elements.
[0077]
Moreover, following formula (3);
X1> X2 (3),
By adjusting the opening of each MFC of the gas introduction system G so as to satisfy the relationship expressed by_FourGas, H₂Gas and Cl₂It is preferable to adjust each supply flow rate to the gas chamber. Where X1 is p.⁺Cl in etching gas (mixed gas) in etching of type GaInAs layer₂X2 represents the gas mixture ratio, and X2 represents Cl in the etching gas in the etching of the p-type InP layer 28a, the n-type InP layer 34a, and the p-type InP layer 32a.₂The gas mixing ratio is shown.
[0078]
P of chlorine active species⁺The reactivity with respect to the type GaInAs layer 30a is higher than the reactivity with respect to each InP layer 28a, InP layer 34a, and InP layer 32a. Therefore, p⁺The etching rate of the p-type GaInAs layer 30a is made larger than that of the p-type InP layer 28a, and p⁺It becomes easy to perform side etching of the type GaInAs layer 30a. On the other hand, in each InP layer 28a, 34a, 32a, the etching gas is CH._FourIf the gas is not mixed, the etch rate is lowered to an inconvenient level. In addition, Cl₂When the InP layers 28a, 34a, and 32a are etched using only the gas, there is a tendency that ‘that’ occurs on the etched surface.
[0079]
More preferably, X1 is 100% by volume (mass flow rate%), and X2 is less than 100% by volume, particularly preferably substantially 0% by volume. That is, p⁺The etching of the type GaInAs layer 30a is substantially Cl₂CH using only gas_FourGas and H₂While the gas is not used, the InP layers 28a, 34a, and 32a are etched using CH._Four/ H₂/ Cl₂Mixed gas or CH_Four/ H₂It is preferable to use a mixed gas.
[0080]
At this time, from the control systems 100 and 101, the CH of the gas introduction system G_FourGas source and H₂A mass flow zero signal is sent to the MFC connected to the gas source to stop the supply of these gases. In this case, the etching gas is Cl.₂Only gas is produced, and only chlorine active species are generated in the chamber 13. P of chlorine active species⁺The reactivity with respect to the type GaInAs layer 30a is higher than the reactivity with respect to the p-type InP layer 28a, the n-type InP layer 34a, and the p-type InP layer 32a. Therefore, p⁺The etch rate of the p-type GaInAs layer 30a is larger than that of the p-type InP layer 28a, and p⁺It is easy to perform side etching of the type GaInAs layer 30a. On the other hand, in each InP layer 28a, 34a, 32a, the etching gas is CH._FourIf the gas is not mixed, the etch rate is lowered to an inconvenient level. In addition, Cl₂When the InP layers 28a, 34a, and 32a are etched using only the gas, there is a tendency that ‘that’ occurs on the etched surface.
[0081]
【The invention's effect】
As described above, according to the etching method and the etching apparatus of the present invention, and the semiconductor device manufacturing method and the manufacturing apparatus thereof, a mesa shape can be easily formed in a stacked body having a plurality of semiconductor layers. Disconnection of the protective film and electrodes provided on the mesa can be prevented, and shape controllability can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram schematically showing a preferred embodiment of an etching apparatus used in the present invention.
FIG. 2 is a configuration diagram schematically showing another preferred embodiment of an etching apparatus used in the present invention.
FIG. 3 is a schematic cross-sectional view showing an example of a semiconductor device manufactured by applying the etching method of the present invention.
4A to 4E are process diagrams showing an example of a state in which a semiconductor laser 1e is manufactured.
FIGS. 5A to 5D are process diagrams showing an example of a procedure of a conventional method for manufacturing a semiconductor device having a mesa shape by one dry etching. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1e ... Semiconductor laser (semiconductor device), 1a, 1b, 1c, 1d ... Base | substrate 10,20 ... Etching apparatus, 11 ... Susceptor, 12 ... Semiconductor substrate (base | substrate), 13 ... Chamber, 14 ... High frequency introduction window, 15 ... Inductive coil (high frequency induction coil), 16, 18 impedance matching unit, 17 high frequency power source (bias power source), 19 high frequency power source (high frequency power source), 22 lower clad layer, 24 MQW-SCH layer, 26 ... first upper cladding layer, 28 ... second upper cladding layer, 28a ... p-type InP layer 28a (second semiconductor layer), 30 ... contact layer, 30a ... p⁺Type GaInAs layer (first semiconductor layer), 32, 34 ... buried layer, 32a ... p type InP layer (second semiconductor layer), 34a ... n type InP layer (second semiconductor layer), 50 ... p Type ohmic electrode layer, 52n type ohmic electrode layer, 60 ... insulator layer, 100, 101 ... control system (control unit), 120 ... photodetector (photodetection unit), G ... gas introduction system (gas supply unit), H ... 庇, K_in... gas inlet, K_out... gas outlet, M1 ... insulator mask, T ... trench, W ... light transmission window.

Claims (8)

A method of forming a mesa shape by etching a substrate including a first semiconductor layer and a second semiconductor layer different from the first semiconductor layer,
A gas supply step of supplying an etching gas into the chamber in which the substrate is housed;
An etching step of applying a bias voltage to the substrate and forming a high frequency induction plasma by applying a high frequency power in the chamber to supply active species derived from the etching gas onto the substrate;
When performing the etching step, the bias voltage, the high frequency power, the high frequency, the flow rate of the etching gas, and the etching gas used for the etching of the first semiconductor layer and the second semiconductor layer, respectively. Control that changes at least one of the mixing ratio of each gas in the case of a mixed gas independently of each other based on physical and / or chemical characteristics of the first semiconductor layer and the second semiconductor layer Process,
Equipped with a,
In the control step, the following formula (1) and formula (2);
Ba <Bb (1),
Ba: the bias voltage used in etching a semiconductor layer having a relatively low etch rate when the etching gas is used in the first semiconductor layer and the second semiconductor layer,
Bb: the bias voltage used for etching a semiconductor layer having a relatively high etch rate when the etching gas is used among the first semiconductor layer and the second semiconductor layer,
Ra> Rb (2),
Ra: the high-frequency power used for etching a semiconductor layer having a relatively low etch rate when the etching gas is used among the first semiconductor layer and the second semiconductor layer,
Bb: the high-frequency power used for etching a semiconductor layer having a relatively high etch rate when the etching gas is used among the first semiconductor layer and the second semiconductor layer,
At least any one so as to satisfy either the bias voltage and at least one from each other etching methods Ru contain altered independently of the high-frequency power of. The first semiconductor layer is mainly composed of a first III-V group compound semiconductor containing at least Ga element, and the second semiconductor layer is mainly composed of a second element not containing Ga element and containing In element. A group III-V compound semiconductor of
The etching method according to claim 1 . As the etching gas, a mixed gas containing CH ₄ gas, H ₂ gas, and Cl ₂ gas is used,
In the control step, the following formula (3):
X1> X2 (3),
X1: a mixing ratio of the Cl ₂ gas in the mixed gas used for etching the first semiconductor layer mainly composed of the first III-V compound semiconductor,
X2: a mixing ratio of the Cl ₂ gas in the mixed gas used for etching the second semiconductor layer mainly composed of the second III-V compound semiconductor,
The supply flow rate of the CH ₄ gas, the H ₂ gas, and the Cl ₂ gas to the chamber in the gas supply process is adjusted so as to satisfy the relationship represented by:
The etching method according to claim 2 . A method of forming a mesa shape by etching a substrate including a first semiconductor layer and a second semiconductor layer different from the first semiconductor layer,
A gas supply step of supplying an etching gas into the chamber in which the substrate is housed;
An etching step of applying a bias voltage to the substrate and forming a high frequency induction plasma by applying a high frequency power in the chamber to supply active species derived from the etching gas onto the substrate;
When performing the etching step, the bias voltage, the high frequency power, the high frequency, the flow rate of the etching gas, and the etching gas used for the etching of the first semiconductor layer and the second semiconductor layer, respectively. Control that changes at least one of the mixing ratio of each gas in the case of a mixed gas independently of each other based on physical and / or chemical characteristics of the first semiconductor layer and the second semiconductor layer Process,
With
The first semiconductor layer is mainly composed of a first III- V group compound semiconductor containing at least Ga element , and the second semiconductor layer is mainly composed of a second element not containing Ga element and containing In element. A group III- V compound semiconductor,
As the etching gas, a mixed gas containing CH ₄ gas, H ₂ gas, and Cl ₂ gas is used,
In the control step, the following formula (3):
X1> X2 (3),
X1: a mixing ratio of the Cl ₂ gas in the mixed gas used for etching the first semiconductor layer mainly composed of the first III- V compound semiconductor ;
X2: a mixing ratio of the Cl ₂ gas in the mixed gas used for etching the second semiconductor layer mainly composed of the second III- V compound semiconductor ,
In so satisfy the relation represented by the CH ₄ gas in the gas supply process, the H ₂ gas, and that to adjust the supply flow rate to the chamber of the Cl ₂ gas, an etching method. In the control step, the chemical composition of each of the first semiconductor layer and the second semiconductor layer is used as the characteristic.
The etching method as described in any one of Claim 1, Claim 2, and Claim 4 . In the control step, as the characteristics, the respective etching rates in the first semiconductor layer and the second semiconductor layer when the etching gas is used are used.
The etching method according to any one of claims 1, 2, 4, and 5 . The first semiconductor layer and the second semiconductor layer are made of different types of III-V compound semiconductors;
The etching method as described in any one of Claim 1, Claim 2, and Claims 4-6 . The first semiconductor layer is mainly composed of GaAs, GaInAs, GaInAsP, or GaInP;
The second semiconductor layer is mainly composed of InP;
The etching method as described in any one of Claims 2-4.

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