JP4053256B2 - Semiconductor device manufacturing method and semiconductor manufacturing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device including a semiconductor film having a crystal structure. In particular, the present invention relates to a method for manufacturing a semiconductor device that requires a step of crystallizing a semiconductor film having an amorphous structure.
[0002]
[Prior art]
A thin film transistor (TFT, hereinafter referred to as TFT) is known as a typical example of a semiconductor element using a semiconductor film. Since a TFT can be formed on a glass substrate, it is currently actively applied as a switching element provided in a pixel of a liquid crystal display device. In particular, by forming an active layer such as a channel formation region using a semiconductor film having a crystal structure, a shift register or a sampling circuit can be operated at a practical driving frequency using a TFT.
[0003]
As an alternative method for forming a semiconductor film having a crystalline structure (hereinafter referred to as a crystalline semiconductor film), a technique in which an amorphous semiconductor film is formed on a glass substrate and then crystallized by laser light irradiation is known. ing. With this technique, a randomly oriented crystalline semiconductor film composed of a large number of crystal grains has been obtained.
[0004]
On the other hand, the techniques disclosed in Japanese Patent Application Laid-Open Nos. 6-232059 and 7-130652 use a metal element (typically nickel) that promotes crystallization of silicon, thereby causing a temperature of 500 to 600 ° C. It is possible to form a crystalline silicon film having excellent crystallinity by heat treatment for about 4 hours. A crystalline semiconductor film manufactured by this technique has a feature that the crystal orientation ratio is relatively high.
[0005]
By the way, when an integrated circuit is formed using TFTs, it is necessary to control the threshold voltage (Vth) in order to obtain a desired switching operation. The threshold voltage (Vth) is an important parameter representing the switching characteristics of the TFT, and if this value deviates from the expected value, the circuit operation is hindered. However, the threshold voltage of the TFT easily changes due to fixed charges in the gate insulating film, impurities in the semiconductor film, and the like.
[0006]
For example, in the case of an n-channel TFT, there is a problem that it shifts to the minus side and becomes normally on (a state in which the gate voltage is not applied). In order to prevent this, a means for adding a p-type impurity (acceptor) to the channel formation region and shifting the threshold voltage to the positive side is taken. This treatment is also called channel doping, and is an important step in the TFT manufacturing process. Usually, diborane (B ₂ H ₆ ) Gas is used for ion implantation or ion doping (a method for implanting ions without mass separation).
[0007]
[Problems to be solved by the invention]
However, the impurity concentration necessary to control the threshold voltage is 10 ¹⁶ -10 ¹⁸ /cm ^Three A trace amount of about is sufficient. However, the method of adding boron (B) to the semiconductor film by ion implantation or ion doping has problems that it is difficult to control the concentration of the trace amount, and that the semiconductor film is damaged. For the purpose of concentration control and reduction of damage, means for forming an insulating film of about 100 nm on the semiconductor film is often employed. By performing such a doping process, the number of TFT manufacturing steps increases, which causes a cost increase and a decrease in productivity.
[0008]
Further, when impurities floating in the air adhere to the surface of the amorphous semiconductor film, the element added at a very small concentration as described above does not work effectively in the semiconductor.
[0009]
The present invention is intended to solve such problems, and an object of the present invention is to provide a technique for controlling the threshold voltage of a TFT more reliably with good reproducibility without increasing the number of steps. To do.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, the structure of the present invention is an amorphous material in which a plurality of kinds of elements contained in a cathode are released by sputtering by discharge of an inert gas under reduced pressure in a reaction chamber equipped with a cathode. The amorphous semiconductor film is added to the crystalline semiconductor film, and then the amorphous semiconductor film is crystallized.
[0011]
One of the elements supplied from the cathode and added to the amorphous semiconductor film is an element that can promote crystallization of the amorphous semiconductor film or lower the crystallization temperature. There are one or more elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au as elements that can obtain such effects. These elements are hereinafter referred to as catalytic elements. The other element is an element that imparts p-type to the semiconductor, and group 13 elements such as B (boron), Al, Ga, and In can be raised. Preferably, B is used.
[0012]
By adding a catalytic element, the amorphous semiconductor film can be easily crystallized by heat treatment at 600 ° C. or lower. Further, the threshold voltage of the TFT can be controlled by adding an impurity element imparting p-type at a desired concentration. According to the present invention, the process of adding the catalytic element and the impurity element imparting p-type from the formation of the amorphous semiconductor film can be continuously performed under reduced pressure, and the number of processes is greatly increased. Thus, a semiconductor device can be manufactured.
[0013]
The catalytic element and the impurity element imparting p-type may be added simultaneously in the same reaction chamber, or the same effect can be obtained by adding them separately in different reaction chambers.
[0014]
In the structure of the above invention, an insulating film made of silicon oxide, silicon nitride, silicon oxynitride, or the like may be formed on the base of the amorphous semiconductor film.
[0015]
On the other hand, the configuration of the semiconductor manufacturing apparatus according to the present invention includes a first reaction chamber for forming an amorphous semiconductor film, a catalytic element for promoting crystallization of the amorphous semiconductor film, and an impurity element for imparting p-type conductivity. A second reaction chamber provided with a cathode containing a cathode, and connected between the first reaction chamber and the second reaction chamber so that the substrate can be moved without being exposed to the atmosphere. The second reaction chamber is connected to a means for introducing an inert gas.
[0016]
In another configuration, the second reaction chamber includes a first reaction chamber for forming an amorphous semiconductor film and a first cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film. And a third reaction chamber provided with a second cathode containing an impurity element imparting p-type to the semiconductor, and a fourth reaction chamber for performing heat treatment, the first reaction chamber through the fourth reaction chamber The reaction chamber is connected so that the substrate can be moved without being exposed to the atmosphere, and means for introducing an inert gas is connected to the second reaction chamber and the third reaction chamber. It is characterized by being.
[0017]
According to another aspect of the invention, there is provided a second reaction chamber including a first reaction chamber for forming an amorphous semiconductor film and a first cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film. A reaction chamber and a third reaction chamber including a second cathode containing an impurity element imparting p-type to the semiconductor, and the substrate is interposed between the first reaction chamber and the third reaction chamber. The second reaction chamber and the third reaction chamber are connected to each other so as to be able to move without being exposed to the atmosphere, and a means for introducing an inert gas is connected to the second reaction chamber and the third reaction chamber.
[0018]
According to another aspect of the invention, there is provided a cathode containing a first reaction chamber for forming an amorphous semiconductor film, a catalytic element for promoting crystallization of the amorphous semiconductor film, and an impurity element for imparting p-type conductivity. And a third reaction chamber for performing heat treatment, and the substrate is placed in the atmosphere between the first reaction chamber, the second reaction chamber, and the third reaction chamber. The second reaction chamber is connected so as to be able to move without being exposed, and a means for introducing an inert gas is connected to the second reaction chamber.
[0019]
According to another aspect of the present invention, there is provided an inert gas under reduced pressure in a first process for forming an amorphous semiconductor film on a substrate in a first reaction chamber and a second reaction chamber provided with a cathode. And a catalytic element that promotes crystallization of the amorphous semiconductor film contained in the cathode by sputtering with a mixed gas of a gas containing a gas containing a periodic group 13 element and a periodic group 13 element And a third step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the second step. It is said.
[0020]
With the above structure, the formation of the amorphous semiconductor film to the addition of the catalytic element and the impurity element imparting p-type can be performed continuously under reduced pressure, and contamination from the environment can be prevented. As a result, the concentration of the element to be added and its effect can be precisely controlled with good reproducibility, and productivity can be improved by performing continuous treatment.
[0021]
The method of adding an element emitted from the cathode using plasma to the amorphous semiconductor film is to adjust the concentration of the element contained in the cathode, or to adjust the discharge power, pressure and processing time for forming plasma. The concentration can be controlled by adding a trace amount of elements with good controllability. As a result, the threshold voltage of the TFT can be controlled with good reproducibility.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1A, a silicon oxynitride film (A) 101a is formed as an insulating film on a substrate 100 such as glass or quartz to a thickness of 10 to 100 nm. A silicon oxynitride film (B) 101b is formed thereon with a thickness of 10 to 100 nm. Further, an amorphous silicon film 102 is formed to a thickness of 20 to 80 nm. The underlying silicon oxynitride film (A) exhibits a high blocking effect such as alkali metal ions from a glass substrate, which is an advantage of the silicon nitride film. On the other hand, the base silicon oxynitride film (B) shows advantages of the silicon oxide film such as a wide band gap, high insulation, and a low trap level.
[0023]
Next, as shown in FIG. 1B, Ni, which is a catalytic element that promotes crystallization, and B, which is an impurity element imparting p-type, are added to the formed amorphous silicon film. Here, as a catalyst element for promoting crystallization, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, or the like may be used in addition to Ni. In addition to B, an impurity element imparting p-type conductivity may be a group 13 element such as Al or Ga.
[0024]
FIG. 2 shows a configuration of a semiconductor manufacturing apparatus suitable for the present invention. As shown in FIG. 2, by providing a plurality of reaction chambers, it is possible to perform continuous processing under reduced pressure without exposing the underlying insulating film to formation of an amorphous semiconductor film and addition of Ni or B to the atmosphere. Become. The semiconductor manufacturing apparatus shown in FIG. 2 includes a load lock chamber 201, a transfer chamber 202, and reaction chambers 203 to 206, and a substrate set in the load lock chamber 201 is a transfer robot 207 installed in the transfer chamber 202. Is transferred to each reaction chamber. Each reaction chamber is provided with plasma generation means, gas introduction means and exhaust means. The load lock chamber 201 and the transfer chamber 202 are provided with exhaust means.
[0025]
In the reaction chamber 203, a silicon oxynitride film provided for a base is formed. In the reaction chamber 204, an amorphous silicon film is formed. The cathode of the reaction chamber 205 is made of a material containing Ni and B. Ni and B can be added to the film formed in the reaction chamber 204 by introducing an inert gas such as Ar gas or He gas into the reaction chamber 205 having such a cathode to generate plasma. it can. The concentration of Ni added here is 1 × 10 ^Ten ~ 1x10 ¹³ /cm ^Three , B concentration is 1 × 10 ¹⁶ ~ 5x10 ¹⁷ /cm ^Three It is desirable that After the addition of Ni and B, the amorphous silicon film is heated to 500 to 600 ° C. and crystallized. Further, if necessary, the crystallinity may be improved by irradiation with laser light.
[0026]
FIG. 18 shows the structure of a cathode made of a material containing Ni and B, which is applied to the present invention. FIG. 18A shows a cathode made of an alloy of Ni and B. The mixing ratio may be determined depending on the amount to be added in consideration of the sputtering efficiency. FIG. 18B shows a case where a B or Ni tablet is arranged on a Ni or B cathode, respectively. FIG. 18C shows a structure in which the cathode itself or the surface of the cathode is meshed so that Ni and B tablets can be arranged. FIG. 18D is a modification of the cathode of FIG. 18C, so that a bar-shaped tablet can be arranged. The cathode shown in FIGS. 18B to 18C has an advantage that the number and arrangement of tablets can be freely changed. In addition, the shape of the tablet is not limited to a square shape, and various shapes such as a circle and a sphere can be used. In the present invention, any of the cathodes having the shapes as shown in FIGS. 18A to 18D can be used.
[0027]
FIG. 3 shows a reaction chamber of the semiconductor manufacturing apparatus of the present invention. The reaction chamber 301 includes a cathode 302 and a susceptor 303, a high frequency power source 305 is connected to the cathode, and a heater 304 is connected to the susceptor. A gas system 306 and an exhaust system 307 are connected. The gas system includes a gas type 314 to be used, a mass flow controller (MFC) 312 and a valve 313. The exhaust system includes a gate valve 308, an auto pressure controller (APC) 309, a turbo molecular pump 310, and a dry pump 311. The pressure in the reaction chamber during film formation is preferably 6 to 160 Pa, and the substrate temperature is preferably in the range of 300 to 400 ° C. The high frequency power supply frequency used is in the range of 13.56 MHz to 120 MHz.
[0028]
[Embodiment 2]
In addition to the above embodiment, there is a method in which Ni and B are added in a separate reaction chamber. The process up to the formation of the amorphous silicon film is performed in the same manner as in the first embodiment. In FIG. 2, the cathode of the reaction chamber 205 is formed of a material containing Ni, and the cathode of the reaction chamber 206 is formed of a material containing B. First, Ni is added in the reaction chamber 205, and then B is added in the reaction chamber 206. Of course, it is also possible to add Ni after B is added first. The subsequent steps are the same as those in the first embodiment.
[0029]
[Embodiment 3]
When an apparatus having a reaction chamber and a heat treatment furnace as shown in FIG. 17 is used, amorphous silicon film formation, Ni and B addition, and crystallization of the amorphous silicon film are processed under reduced pressure. Is possible. Here, the reaction chamber 206 is a heat treatment furnace. As in Embodiment Mode 1 or 2, the substrate on which the amorphous silicon film is formed and Ni and B are added is transferred to the load lock chamber 208 and transferred to the heat treatment furnace 206 by the transfer robot 209. The method for crystallizing the amorphous silicon film may be performed in the same manner as in Embodiment Mode 1 or 2.
[0030]
【Example】
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate using the present invention will be described in detail.
[0031]
As the substrate 100, a glass substrate is used. First, as shown in FIG. 4A, a silicon oxynitride film 101a is formed as an insulating film over a substrate 100 to a thickness of 50 nm. Next, a silicon oxynitride film 101b is formed to a thickness of 100 nm. Although a two-layer structure is used as the insulating film 101 in this embodiment, a single layer of silicon oxynitride film or a structure in which two or more layers are stacked may be used. An amorphous silicon film 102 is formed thereon with a thickness of 55 nm.
[0032]
Next, Ni, which is a catalyst element that promotes crystallization, and B, which is an impurity element imparting p-type, are added to the formed amorphous silicon film. As a method, Ar is introduced as an inert gas into a reaction chamber having a cathode made of Ni and B, and the pressure is 6.65 to 1.33 × 10 6. ² Plasma is generated at Pa and high frequency power of 30 to 100 W (power supply frequency of 13.56 to 60 MHz). Since the cathode is negatively charged by self-bias, positive ions in the plasma are accelerated by the sheath formed in the vicinity of the cathode and enter the cathode. Ni and B, which are elements constituting the cathode, are released by ion collision sputtering and adhere to the amorphous silicon film.
[0033]
The inert gas introduced to generate plasma may be He, Kr, or Xe as well as Ar. In addition, N ₂ May be used. Also, by adding hydrogen simultaneously, the surface of the amorphous silicon film can be inactivated by terminating with hydrogen, and the movement of Ni or B attached to the surface is promoted, and the distribution of the element is dispersed. It can be made.
[0034]
This processing time may be appropriately set by a practitioner, but is determined in consideration of the component ratio of Ni and B in the cathode and the high frequency power to be applied.
[0035]
In this way, Ni is 1 × 10. ^Ten ~ 1x10 ¹³ /cm ² , B is 1 × 10 ¹³ ~ 5x10 ¹⁴ /cm ² Thus, an amorphous silicon film added at a concentration of 1 is obtained. In addition to Ni, examples of the catalytic element that promotes crystallization of the amorphous silicon film include Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. In addition to B, periodic group 13 elements such as Al and Ga are known as elements that impart p-type to the semiconductor film.
[0036]
The processes up to the above can be continuously performed under reduced pressure without exposing the formation of the insulating film, the formation of the amorphous semiconductor film, and the addition of Ni and B to the atmosphere.
[0037]
After adding Ni and B to the amorphous silicon film, a dehydrogenation treatment is performed at 500 ° C. for 1 hour, and a heat treatment is performed at 550 ° C. for 4 hours, whereby the crystalline silicon film 103 is obtained. Further, laser light may be irradiated to improve crystallinity. In the crystalline silicon film thus formed, B is 1 × 10 5 as a p-type impurity element. ¹⁵ ~ 1x10 ¹⁷ /cm ^Three Contained at a concentration of
[0038]
Then, a patterning process using a photolithography method is performed on the crystalline semiconductor film to form crystalline silicon layers 104 to 108 divided into island shapes (FIG. 4C).
[0039]
When crystallinity is improved by laser irradiation, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YLF laser, YVO _Four A laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The practitioner may select the crystallization conditions as appropriate.
[0040]
Next, a gate insulating film 109 that covers the crystalline silicon films 104 to 108 is formed. The gate insulating film 109 is formed by a plasma CVD method or a sputtering method, and is formed of an insulating film containing silicon with a thickness of 40 to 150 nm. Needless to say, this gate insulating film can be formed using an insulating film containing silicon as a single layer or a stacked structure.
[0041]
In the case of using a silicon oxide film, TEOS (Tetraethyl Ortho Silicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus formed can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. after the formation.
[0042]
Next, a first conductive film 110 with a thickness of 20 to 100 nm and a second conductive film 111 with a thickness of 100 to 400 nm are stacked over the gate insulating film 109 (FIG. 5A). These conductive films may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus (P) may be used. Also, a combination in which the first conductive film is formed of a Ta film, the second conductive film is a W film, the first conductive film is formed of a tantalum nitride film, and the second conductive film is an Al film. Alternatively, the first conductive film may be formed of a tantalum nitride film, and the second conductive film may be a Cu film.
[0043]
Next, as shown in FIG. 5B, resist masks 112 to 117 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ The gas flow ratio is 25:25:10, and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.
[0044]
Thereafter, the resist masks 112 to 117 are not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ The gas flow ratio is 30:30, and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching for about 30 seconds. . 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the tantalum nitride film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0045]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 119 to 124 (the first conductive layers 119a to 124a and the second conductive layers 119b to 124b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 118 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 119 to 124 is etched and thinned by about 20 to 50 nm.
[0046]
Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer (FIG. 5B). The doping process may be performed by ion doping or ion implantation. The condition of the ion doping method is that the dose is 1.5 × 10 ¹⁵ /cm ² The acceleration voltage is set to 60 to 100 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In this case, the conductive layers 119 to 123 serve as a mask for the impurity element imparting n-type, and the first impurity regions 125 to 129 are formed in a self-aligning manner. The first impurity regions 125 to 129 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} /cm ^Three An impurity element imparting n-type is added in a concentration range of.
[0047]
Next, a second etching process is performed as shown in FIG. 5C without removing the resist mask. CF as etching gas _Four And Cl ₂ And O ₂ The gas flow ratio is 20:20:20, and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under this third etching condition, the W film is anisotropically etched to form second-shaped conductive layers 131 to 136.
[0048]
Next, a second doping process is performed as shown in FIG. 6A without removing the resist mask. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV, and in this embodiment, the acceleration voltage is set to 90 keV. ¹⁴ /cm ² Then, a new impurity region is formed in the semiconductor layer inside the first impurity region formed in FIG. 5B. Doping is performed using the second shape conductive layers 131 to 135 as masks against the impurity elements so that the impurity elements are also added to the semiconductor layers below the first conductive layers 131a to 135a.
[0049]
In this manner, second impurity regions 137 to 141 overlapping with the first conductive layers 131a to 135a are formed.
[0050]
Next, after removing the resist mask, new resist masks 147 and 148 are formed, and a third etching process is performed as shown in FIG. 6B. SF for etching gas ₆ And Cl ₂ The gas flow ratio is 50:10, and 500 W of RF (13.56 MHz) power is applied to the coiled electrode at a pressure of 1.3 Pa to generate plasma and perform etching for about 30 seconds. Do. 10 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In this way, the third shape conductive layers 149 to 152 are formed by etching the tantalum nitride films of the p-channel TFT and the pixel portion TFT under the third etching condition.
[0051]
Then, after removing the resist mask, the gate insulating film is etched as shown in FIG. CHF as etching gas _Three Etching is performed by generating plasma with a gas flow rate of 35 SCCM and an RF power of 800 W. Here, the second shape conductive layers 131 and 133 and the third conductive layers 149 to 152 serve as a mask, and the gate insulating film is cut for each TFT (154 to 160).
[0052]
Next, masks 161 to 163 are formed, and a third doping process is performed as shown in FIG. By this third doping treatment, second impurity regions 164 to 167 are formed in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer that becomes the active layer of the p-channel TFT. . Using the third shape conductive layers 149 and 153 as masks against the impurity element, an impurity element imparting p-type is added to form a third impurity region in a self-aligning manner. In this embodiment, the impurity regions 164 to 167 are diborane (B ₂ H ₆ ) Using an ion doping method. In the third doping process, the semiconductor layer forming the n-channel TFT is covered with masks 161 to 163 made of resist. Phosphorus (P) is added to the impurity regions 164 to 167 at different concentrations by the first doping process and the second doping process. The concentration of the impurity element imparting p-type in any of the regions. By performing the doping process so as to be higher, no problem arises because it functions as the source region and drain region of the p-channel TFT.
[0053]
Through the above steps, impurity regions are formed in the respective semiconductor films. In this embodiment, all impurity regions are formed in a self-aligned manner using the conductive layer as a mask. The third shape conductive layers 131, 132, 149, and 150 overlapping with the semiconductor film function as gate electrodes. Reference numeral 152 functions as a source wiring, and 151 functions as a second electrode for forming a storage capacitor.
[0054]
Next, the masks 161 to 163 are removed, and a first interlayer insulating film 168 covering the entire surface is formed. The first interlayer insulating film 168 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by plasma CVD. Needless to say, the first interlayer insulating film 168 is not limited to a silicon oxynitride film, and an insulating film containing other silicon may be used as a single layer or a stacked structure.
[0055]
Next, as shown in FIG. 7B, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere with an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0056]
In this embodiment, simultaneously with the activation process, Ni used as a catalyst during crystallization can be gettered into the impurity regions 142 to 146, 164, and 166 containing phosphorus (P) at a high concentration. Thus, the Ni concentration in the crystalline silicon mainly serving as the channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0057]
Next, a second interlayer insulating film 169 made of an organic insulating material is formed on the first interlayer insulating film 168. Next, patterning is performed to form contact holes that reach the source wiring 152 and contact holes that reach the impurity regions 142, 144, 145 a, 164, and 166.
[0058]
In the driver circuit 406, wirings 170 to 175 that are electrically connected to the first impurity region or the third impurity region are formed. These wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 to 250 nm and an alloy film (alloy film of Al and Ti) having a thickness of 300 to 500 nm.
[0059]
In the pixel portion 407, a pixel electrode 178, a gate conductive film 177, and a connection electrode 176 are formed (FIG. 7C). With this connection electrode 176, the source wiring 152 is electrically connected to the pixel TFT 404. The gate conductive film 177 is electrically connected to the first electrode (the third shape conductive layer 150). In addition, the pixel electrode 178 is electrically connected to a drain region of the pixel TFT, and is further electrically connected to a semiconductor layer functioning as one electrode forming a storage capacitor.
[0060]
As described above, the driver circuit 406 including the n-channel TFT 401, the p-channel TFT 402, and the n-channel TFT 403, and the pixel portion 407 including the pixel TFT 404 and the storage capacitor 405 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0061]
The n-channel TFT 401 of the driver circuit 406 includes a channel formation region 178, a second impurity region 137 that overlaps with the third shape conductive layer 131 that forms a gate electrode, and a first impurity region 142 that functions as a source region or a drain region. have. The p-channel TFT 402 includes a channel formation region 179, a third impurity region 165 formed outside the gate electrode, and a third impurity region 164 functioning as a source region or a drain region. The n-channel TFT 403 includes a channel formation region 180, a second impurity region 139 that overlaps with the third shape conductive layer 133 that forms a gate electrode, and a first impurity region 144 that functions as a source region or a drain region. ing.
[0062]
A pixel TFT 404 in the pixel portion 407 includes a channel formation region 181, a second impurity region 140 formed outside the gate electrode, and a first impurity region 145 a functioning as a source region or a drain region. Further, an impurity element imparting p-type conductivity is added to each of the semiconductor layers 166 and 167 functioning as one electrode of the storage capacitor 405 at the same concentration as that of the third impurity region. The storage capacitor 405 is formed of the second electrode 151 and the semiconductor layers 166 and 167 using an insulating film (the same film as the gate insulating film) as a dielectric.
[0063]
A top view of the pixel portion of the active matrix substrate manufactured in this embodiment is shown in FIG. In addition, the same code | symbol is used for the part corresponding to FIGS. A chain line AA ′ in FIG. 10 corresponds to a cross-sectional view taken along the chain line AA ′ in FIG. Further, a chain line BB ′ in FIG. 10 corresponds to a cross-sectional view taken along the chain line BB ′ in FIG. With such a pixel structure, a pixel electrode having a large area can be disposed, and the aperture ratio can be improved.
[0064]
According to the steps shown in this embodiment, the number of photomasks necessary for manufacturing the active matrix substrate is six (semiconductor layer pattern mask, first wiring pattern mask (first electrode 150, second electrode 151, source Including a wiring 152), a pattern mask for forming a conductive layer of a p-channel TFT and a pixel portion TFT, a pattern mask for forming a source region and a drain region of a p-channel TFT, a pattern mask for forming a contact hole, A pixel electrode 178, a connection electrode 176, and a gate conductive film 177). In addition, since Ni addition and B addition are performed simultaneously and continuously with the formation of the amorphous semiconductor film, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.
[0065]
In the above steps, a catalytic element that promotes crystallization of the amorphous silicon film is continuously added after the amorphous silicon film is formed, so that contamination of the surface can be prevented, and a highly uniform crystalline silicon film Can be formed. Furthermore, since the B doping is continuously performed after the amorphous silicon film is formed, the crystal structure of the channel formation region is prevented from being destroyed, so that the threshold voltage can be controlled with good reproducibility. Moreover, productivity can be improved by adding a catalyst element and B simultaneously.
[0066]
FIG. 8 is a cross-sectional view of an active matrix substrate suitable for a transmissive liquid crystal display device. The processes up to the formation of the second interlayer film are the same as those of the reflection type. A transparent conductive film is formed on the second interlayer film. Then, patterning is performed to form the transparent conductive film layer 185. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.
[0067]
Then, wirings 170 to 175 that are electrically connected to the first impurity region or the third impurity region in the driver circuit 406 are formed. These wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 to 250 nm and an alloy (alloy film of Al and Ti) having a thickness of 300 to 500 nm. In the pixel portion 407, a pixel electrode 185, a gate conductive film 177, and connection electrodes 186 and 187 are formed. The connection electrodes 186 and 187 are formed so as to overlap the pixel electrode 185. In this manner, an active matrix substrate suitable for a transmissive liquid crystal display device can be manufactured by increasing the number of masks by one.
[0068]
[Example 2]
In Example 1, the case of performing different addition methods of Ni and B will be described. The drawings used for the description are the same as those in the first embodiment.
[0069]
Similar to the first embodiment, the insulating film 101 to the amorphous silicon film 102 are formed. Next, plasma is generated in a reaction chamber having a cathode made of Ni, Ni is added by exposing the amorphous silicon film 102 to the plasma, and then plasma is generated in a reaction chamber having a cathode made of B. B is added by exposing the amorphous semiconductor film that has been formed and doped with Ni to the plasma. Thereafter, dehydrogenation is performed at 500 ° C. for 1 hour, followed by crystallization at 550 ° C. for 4 hours to form a crystalline silicon film 103. Further, laser light irradiation may be performed to improve crystallization.
[0070]
When it is difficult to obtain an alloy of Ni and B, or when it is difficult to obtain an appropriate concentration when Ni and B are added in the same reaction chamber, as in this example In addition, a method of adding Ni and B in separate reaction chambers is effective. For subsequent steps, Example 1 may be referred to.
[0071]
[Example 3]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 or Embodiment 2 will be described below. It is also possible to use an active matrix substrate manufactured in Example 5 described later. FIG. 9 is used for the description.
[0072]
First, an active matrix substrate in the state of FIG. 7C is manufactured according to Example 1 or Example 2, and then an alignment film 567 is formed over the active matrix substrate of FIG. 7C and a rubbing process is performed. In this embodiment, before forming the alignment film 567, an organic resin film such as an acrylic resin film is patterned to form columnar spacers 572 for maintaining a substrate interval at a desired position.
[0073]
Next, colored layers 570 and 571 and a planarization film 573 are formed over the counter substrate 569. The red colored layer 570 and the blue colored layer 571 are partially overlapped to form the second light shielding portion.
[0074]
Next, a counter electrode 576 is formed in the pixel portion, an alignment film 574 is formed over the entire surface of the counter substrate, and a rubbing process is performed.
[0075]
Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are bonded together with a sealant 568. A filler is mixed in the sealant 568, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer 572. Thereafter, a liquid crystal material is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. In this way, the active matrix liquid crystal display device shown in FIG. 9 is completed.
[0076]
In this embodiment, the substrate shown in Embodiment 1 is used. Therefore, in FIG. 10 showing a top view of the pixel portion of Example 1, at least the gap between the gate wiring 177 and the pixel electrode 178, the gap between the gate wiring 177 and the connection electrode 176, and the gap between the connection electrode 176 and the pixel electrode 178 are shown. It is necessary to shield the light. In this embodiment, the counter substrate is bonded so that the first light-shielding portion and the second light-shielding portion overlap each other at the position where light should be shielded.
[0077]
The liquid crystal display device manufactured as described above can be used as a display portion of various electronic devices.
[0078]
[Example 4]
In this embodiment, a method for manufacturing a crystalline semiconductor film over a substrate will be described with reference to FIGS.
[0079]
After the insulating film 301 is formed over the substrate 300, an amorphous semiconductor film 302 is formed. A catalytic element Ni for promoting crystallization and an element B for imparting p-type are added to the amorphous semiconductor film 302 (FIG. 19A), and a crystalline semiconductor film 303 is obtained by crystallization (FIG. 19B )). Example 1 or Example 2 is applied to the above process.
[0080]
A mask layer 304 is formed using a silicon oxide film or the like over the obtained amorphous semiconductor film 303, and first patterning is performed (FIG. 19C). The mask layer 304 is etched using the patterned resist 305 as a mask. Next, a first doping process is performed using the resist 305 and the mask layer 306 as a mask. In the first doping treatment, phosphorus (P) is added to the crystalline semiconductor layer 303 to form an impurity region 307 (FIG. 19D).
[0081]
Next, heat treatment is performed. In this step, Ni added to the semiconductor layer diffuses into the impurity region 307. After the heat treatment, Ni which is an impurity can be removed from the channel portion of the TFT by etching and removing the impurity region 307 (FIG. 19E).
[0082]
The resist 305 and the mask layer 306 are peeled off to obtain a crystalline semiconductor film 308 (FIG. 19F). For subsequent steps, a known TFT manufacturing method may be referred to.
[0083]
In the above steps, a catalytic element that promotes crystallization of the amorphous silicon film is continuously added after the amorphous silicon film is formed, so that contamination of the surface can be prevented, and a highly uniform crystalline silicon film Can be formed. Furthermore, since the B doping is continuously performed after the amorphous silicon film is formed, the crystal structure of the channel formation region is prevented from being destroyed, so that the threshold voltage can be controlled with good reproducibility. Moreover, productivity can be improved by adding a catalyst element and B simultaneously. By removing Ni, which is an impurity, from the channel portion of the TFT, the off-current value can be lowered and the variation can be reduced.
[0084]
[Example 5]
In this embodiment, a method of simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) for forming a driver circuit around the pixel portion on the same substrate using inverted staggered TFTs is shown in FIG. -13 will be used for explanation.
[0085]
First, as shown in FIG. 11 (A), one or more kinds preferably selected from Mo, W, and Ta are formed on a substrate 1101 made of glass such as barium borosilicate glass or alumino borosilicate glass. Gate electrodes 1102 to 1104, source wirings 1106 and 1107, and a capacitor wiring 1105 for forming a storage capacitor of the pixel portion are formed from the conductive film. For example, an alloy of Mo and W is suitable from the viewpoint of resistance reduction and heat resistance. Alternatively, aluminum may be used to oxidize the surface to form the gate electrode.
[0086]
In order to improve the coverage (step coverage) of the film formed on the upper layer of the gate electrode formed using the first photomask, the thickness of the gate electrode is 200 to 400 nm, preferably 250 nm. The end is formed to have a tapered shape. The angle of the tapered portion is 5 to 30 degrees, preferably 15 to 25 degrees. The tapered portion is formed by a dry etching method, and its angle is controlled by an etching gas and a bias voltage applied to the substrate side.
[0087]
Next, as illustrated in FIG. 11B, an insulating layer is formed as the first insulating layer 1108 covering the gate electrodes 1102 to 1104, the source wirings 1106 and 1107, and the capacitor wiring 1105 for forming a storage capacitor of the pixel portion. . Although a two-layer structure is used as the first insulating layer 1108 in this embodiment, a single-layer film of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or a structure in which two or more layers are stacked may be used. As the first layer of the first insulating layer 1108, SiH _Four , NH _Three , N ₂ O and H ₂ A silicon oxynitride film 1108a is formed to have a thickness of 50 to 100 nm formed using a reactive gas as a reactive gas. Next, as the second layer of the first insulating layer 1108, SiH _Four And N ₂ A silicon oxynitride film 1108b formed using O as a reactive gas is stacked to a thickness of 100 to 150 nm. Next, an amorphous semiconductor film 1109 is formed with a thickness of 30 to 60 nm on the first insulating layer. There is no limitation on the material of the amorphous semiconductor film, but silicon is preferably used. In this example, SiH _Four An amorphous silicon film 1109 is formed using a gas.
[0088]
The first insulating layer 1108 is used as a gate insulating film by forming a semiconductor layer thereon, and functions as a blocking layer that prevents impurities such as alkali metals from diffusing from the substrate 1101 to the semiconductor layer. Also have.
[0089]
A catalyst element for promoting crystallization and an impurity element for imparting p-type are added to the formed amorphous silicon film. The method of Example 1 or Example 2 is applied for the addition method.
[0090]
Next, the formed amorphous silicon film is crystallized by heat treatment. The crystallization method may be referred to Example 1 or Example 2.
[0091]
The obtained crystalline silicon film is formed into a predetermined pattern using a second photomask. FIG. 11C illustrates the semiconductor layers 1110 to 1213 formed in an island shape. The semiconductor layers 1110 to 1112 are formed so as to partially overlap the gate electrodes 1102 and 1104.
[0092]
Thereafter, an insulating film made of silicon oxide or silicon nitride is formed on the crystalline silicon films 1110 to 1113 to a thickness of 100 to 200 nm. In FIG. 11D, third insulating layers 1114 to 1118 which are channel protective films are formed on the crystalline silicon films 1110 to 1112 in a self-aligning manner by an exposure process from the back surface using the gate electrode as a mask.
[0093]
Then, a first doping process for forming the LDD region of the n-channel TFT is performed. The doping method may be an ion doping method or an ion implantation method. Phosphorus (P) is added as an n-type impurity (donor), and first impurity regions 1119 to 1122 formed using the third insulating layers 1115 to 1118 as masks are formed. The donor concentration in this region is 1 × 10 ¹⁶ ~ 2x10 ¹⁷ /cm ^Three Concentration.
[0094]
The second doping step is a step of forming a source region and a drain region of an n-channel TFT, and masks 1123 to 1125 are formed using a third photomask as shown in FIG. To do. The masks 1124 and 1125 are formed so as to cover the LDD region of the n-channel TFT, and the second impurity regions 1126 to 1128 have 1 × 10 6. ²⁰ ~ 1x10 ^{twenty one} /cm ^Three The donor impurity is added in the concentration range of.
[0095]
Before and after the second doping step, it is preferable to remove the third insulating layers 1114 and 1118 by performing an etching process using hydrofluoric acid in a state where the masks 1123 to 1125 are formed.
[0096]
As shown in FIG. 12B, the source region and the drain region of the p-channel TFT are formed by a third doping process, and a p-type impurity (acceptor) is added by an ion doping method or an ion implantation method to add a third region. The impurity regions 1130 and 1131 are formed. The p-type impurity concentration in this region is 2 × 10 ²⁰ ~ 2x10 ^{twenty one} /cm ^Three To be. In this step, a p-type impurity is also added to the semiconductor layer 1113.
[0097]
Next, as illustrated in FIG. 12C, a second insulating layer is formed over the semiconductor layer. Preferably, the second insulating layer is formed using a plurality of insulating films. The first layer 1132 of the second insulating layer formed over the semiconductor layer is an inorganic insulator made of a silicon nitride film or a silicon nitride oxide film containing hydrogen and has a thickness of 50 to 200 nm. Thereafter, a step of activating the impurities added to the respective semiconductor layers is performed. In this step, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0098]
By this activation treatment, hydrogen of the silicon nitride film or the silicon nitride oxide film of the first layer 1132 of the second insulating layer is released simultaneously with the activation of the impurity element, so that the semiconductor layer can be hydrogenated.
[0099]
A second layer 1133 of the second insulating layer shown in FIG. 13A is formed of an organic insulating material such as polyimide or acrylic and the surface thereof is planarized. Of course, a silicon oxide film formed using TEOS by a plasma CVD method may be applied, but it is preferable to use the organic material from the viewpoint of improving flatness.
[0100]
Next, a contact hole is formed using a fifth photomask. Then, the connection electrode 1134 and the source or drain wirings 1135 to 1137 are formed in the driver circuit 1305 using Al, Ti, Ta, or the like using a sixth photomask. In the pixel portion 1306, a pixel electrode 1140, a gate wiring 1139, and a connection electrode 1138 are formed.
[0101]
Thus, a driver circuit 1305 having a p-channel TFT 1301 and an n-channel TFT 1302, and a pixel portion 1306 having a pixel TFT 1303 and a storage capacitor 1304 are formed over the same substrate. In the p-channel TFT 1301 of the driver circuit 1305, a channel formation region 1307 and a source or drain region 1308 including a third impurity region are formed. In the n-channel TFT 1302, a channel formation region 1309, an LDD region 1310 composed of a first impurity region, and a source or drain region 1311 composed of a second impurity region are formed. A pixel TFT 1303 in the pixel portion 1306 has a multi-gate structure, and a channel formation region 1312, an LDD region 1313, and source or drain regions 1314 and 1316 are formed. The second impurity region 1315 located between the LDD regions is useful for reducing off current. The storage capacitor 1304 is formed of a capacitor wiring 1105, a semiconductor layer 1113, and a first insulating layer formed therebetween.
[0102]
In the pixel portion 1306, the source wiring 1107 is electrically connected to the source or drain region 1314 of the pixel TFT 1303 by the connection electrode 1138. In addition, the gate wiring 1139 is electrically connected to the first electrode. The pixel electrode 1140 is connected to the source or drain region 1316 of the pixel TFT 1303 and the semiconductor layer 1113 of the storage capacitor 1304.
[0103]
FIG. 13B illustrates a contact portion between the gate electrode 1104 and the gate wiring 1139. The gate electrode 1104 also serves as one electrode of a storage capacitor of an adjacent pixel, and forms a capacitor in a portion overlapping with the semiconductor layer 1144 connected to the pixel electrode 1145. FIG. 13C shows the arrangement relationship between the source wiring 1107, the pixel electrode 1140, and the adjacent pixel electrode 1146. The end of the pixel electrode is provided over the source wiring 1107, and stray light is generated by forming an overlapping portion. Improves light shielding properties.
[0104]
One of the advantages of forming the TFT with an inverted stagger type is that the LDD region overlapping the gate electrode in the n-channel TFT can be formed in a self-aligned manner by the backside exposure process. In combination with the feature that can be continuously formed, variation in TFT characteristics can be reduced. Further, by using the present invention, it is possible to prevent the crystal structure of the semiconductor layer from being broken, so that stable TFT characteristics can be obtained.
[0105]
Furthermore, a catalytic element that promotes crystallization of the amorphous silicon film is continuously added after the amorphous silicon film is formed, thereby preventing surface contamination and forming a highly uniform crystalline silicon film. be able to. Furthermore, since the B doping is continuously performed after the amorphous silicon film is formed, the crystal structure of the channel formation region is prevented from being destroyed, so that the threshold voltage can be controlled with good reproducibility. Moreover, productivity can be improved by adding a catalyst element and B simultaneously.
[0106]
[Example 6]
In this embodiment, a method for manufacturing a crystalline semiconductor film over a substrate will be described with reference to FIGS.
[0107]
As the substrate 600, a quartz substrate is used. In addition, if it has heat resistance, it can be used. An amorphous semiconductor film 601 is formed on the substrate 600 with a thickness of 30 to 60 nm. In this embodiment, an insulating film is not formed, but it is of course possible to form an insulating film. A catalyst element Ni that promotes crystallization and an element B that imparts p-type are added to the formed amorphous semiconductor film 601. Example 1 or Example 2 is applied as the addition method.
[0108]
Next, thermal crystallization is performed (FIG. 20B). It is good to carry out at 570-600 degreeC for about 12-14 hours. By this heat treatment, a crystalline semiconductor film 602 is obtained. The crystalline semiconductor film is patterned to obtain a crystalline semiconductor film 603 (FIG. 20C). For subsequent steps, a known TFT manufacturing method may be referred to.
[0109]
[Example 7]
This embodiment shows another example of a method of adding Ni, which is a catalyst element for promoting crystallization, and an impurity element imparting p-type (periodic group 13 element) to an amorphous silicon film.
[0110]
First, an amorphous silicon film is formed in the same manner as in Example 1. Thereafter, the substrate is moved to another reaction chamber in order to add the catalyst element. The cathode of this reaction chamber contains Ni. For example, a flat plate electrode made of Ni alone or a mesh electrode can be used.
[0111]
The inert gas introduced into the reaction chamber for generating plasma may be Ar, and He, Kr, Xe, etc. may be used. N as an inert gas ₂ Can also be added. Furthermore, 1 to 1000 ppm of a gas containing a periodic group 13 element is added to this inert gas. As a gas containing a periodic group 13 element, B ₂ H ₆ , BF _Three Etc. can be applied.
[0112]
A suitable example is Ar and B ₂ H ₆ And by generating a plasma with this mixed gas, sputtering action of Ar ions on the cathode, and B ₂ H ₆ Ni and B can be added to the amorphous silicon film by this dissociation. B ₂ H ₆ May be diluted with Ar, or may be diluted with hydrogen.
[0113]
When it is difficult to obtain an alloy of Ni and B, or when it is difficult to obtain an appropriate concentration when Ni and B are added in the same reaction chamber, the method shown in this example is as follows. It is valid. Such a method shown in this embodiment can be performed by replacing the Ni and B addition method shown in Embodiment 1.
[0114]
[Example 8]
TFTs manufactured by implementing the present invention can be used in various electro-optical devices (typically, active matrix liquid crystal displays). That is, the present invention can be applied to all electronic devices in which these electro-optical devices and semiconductor circuits are incorporated as components.
[0115]
Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, and portable information terminal devices (mobile computers, mobile phones). Phone or electronic book). Examples of these are shown in FIGS.
[0116]
FIG. 14A shows a personal computer, which includes a main body 1401, an image input portion 1402, a display portion 1403, a keyboard 1404, and the like. The present invention can be applied to the image input unit 1402, the display unit 1403, and other signal control circuits.
[0117]
FIG. 14B illustrates a video camera, which includes a main body 1405, a display portion 1406, an audio input portion 1407, operation switches 1408, a battery 1409, an image receiving portion 1410, and the like. The present invention can be applied to the display portion 1406 and other signal control circuits.
[0118]
FIG. 14C illustrates a mobile computer, which includes a main body 1411, a camera unit 1412, an image receiving unit 1413, an operation switch 1414, a display unit 1415, and the like. The present invention can be applied to the display portion 1415 and other signal control circuits.
[0119]
FIG. 14D illustrates a goggle type display including a main body 1416, a display portion 1417, an arm portion 1418, and the like. The present invention can be applied to the display portion 1417 and other signal control circuits.
[0120]
FIG. 14E shows a player that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 1419, a display portion 1420, a speaker portion 1421, a recording medium 1422, an operation switch 1423, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can enjoy music, movies, games, and the Internet. The present invention can be applied to the display portion 1420 and other signal control circuits.
[0121]
FIG. 14F illustrates a digital camera, which includes a main body 1424, a display portion 1425, an eyepiece portion 1426, operation switches 1427, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 1425 and other signal control circuits.
[0122]
FIG. 15A illustrates a front type projector, which includes a projection device 1501, a screen 1502, and the like. The present invention can be applied to a liquid crystal display device 1514 constituting a part of the projection device 1501 and other signal control circuits.
[0123]
FIG. 15B shows a rear projector, which includes a main body 1503, a projection device 1504, a mirror 1505, a screen 1506, and the like. The present invention can be applied to the liquid crystal display device 1514 constituting a part of the projection device 1504 and other signal control circuits.
[0124]
Note that FIG. 15C is a diagram illustrating an example of the structure of the projection devices 1501 and 1504 in FIGS. 15A and 15B. The projection devices 1501 and 1504 include a light source optical system 1507, mirrors 1508 and 1510 to 1512, a dichroic mirror 1509, a prism 1513, a liquid crystal display device 1514, a phase difference plate 1515, and a projection optical system 1516. The projection optical system 1516 is configured by an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0125]
FIG. 15D illustrates an example of the structure of the light source optical system 1507 in FIG. In this embodiment, the light source optical system 1807 includes a reflector 1518, a light source 1519, lens arrays 1520 and 1521, a polarization conversion element 1522, and a condenser lens 1523. Note that the light source optical system illustrated in FIG. 15D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0126]
However, the projector shown in FIG. 15 shows a case where a transmissive liquid crystal display device is used, and an application example of a reflective electro-optical device is not shown.
[0127]
FIG. 16A illustrates a mobile phone, which includes a display panel 1601, an operation panel 1602, a connection portion 1603, a sensor built-in display 1604, an audio output portion 1605, operation keys 1606, a power switch 1607, an audio input portion 1608, and an antenna 1609. Etc. The present invention can be applied to the sensor built-in display 1604, the audio output unit 1605, the audio input unit 1608, and other signal control circuits.
[0128]
FIG. 16B illustrates a portable book (electronic book), which includes a main body 1611, a display portion 1612, a storage medium 1613, operation switches 1614, an antenna 1615, and the like. The present invention can be applied to the display portion 1612, the storage medium 1613, and other signal circuits.
[0129]
FIG. 16C illustrates a display, which includes a main body 1916, a support base 1917, a display portion 1918, and the like. The present invention can be applied to the display portion 1918. The liquid crystal display device of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0130]
As described above, the application range of the present invention is extremely wide and can be applied to various electronic devices.
[0131]
【The invention's effect】
According to the present invention, the number of steps in manufacturing the TFT is reduced, and a device for channel doping is not required, so that cost reduction can be realized. In addition, by performing doping treatment before crystallization, the crystal structure formed by crystallization can be prevented from being destroyed at the time of doping, so that the crystal structure of the crystalline semiconductor layer is improved and high-speed image processing is performed. And high-speed communication.
[0132]
By adding a catalytic element that promotes crystallization of the amorphous silicon film continuously after the formation of the amorphous silicon film, surface contamination can be prevented and a highly uniform crystalline silicon film can be formed. it can. Furthermore, since the B doping is continuously performed after the amorphous silicon film is formed, the crystal structure of the channel formation region is prevented from being destroyed, so that the threshold voltage can be controlled with good reproducibility. Moreover, productivity can be improved by adding a catalyst element and B simultaneously.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a TFT according to a first embodiment.
FIG. 2 is a device diagram of the first embodiment.
FIG. 3 is a cross-sectional view of the apparatus according to the first embodiment.
4 is a cross-sectional view of a TFT according to Example 1. FIG.
FIG. 5 is a cross-sectional view of a TFT according to the first embodiment.
6 is a cross-sectional view of a TFT according to Example 1. FIG.
7 is a cross-sectional view of TFT in Example 1. FIG.
8 is a cross-sectional view of a TFT according to Example 1. FIG.
9 is a cross-sectional view of an active matrix liquid crystal display device according to Embodiment 3. FIG.
10 is a top view of a pixel portion of an active matrix substrate manufactured in Embodiment 1. FIG.
11 is a cross-sectional view of TFT in Example 5. FIG.
12 is a cross-sectional view of TFT in Example 5. FIG.
13 is a cross-sectional view of TFT in Example 5. FIG.
14 is a diagram showing various semiconductor devices of Example 7. FIG.
15 is a view showing various semiconductor devices of Example 7. FIG.
16 shows various semiconductor devices of Example 7. FIG.
FIG. 17 is a device diagram of the third embodiment.
18 is a diagram of a cathode used for adding Ni and B. FIG.
19 is a cross-sectional view of TFT in Example 4. FIG.
20 is a cross-sectional view of TFT in Example 6. FIG.

Claims (28)

A first step of forming an amorphous semiconductor film on a substrate;
A second step of discharging a plurality of kinds of elements contained in the cathode by sputtering and adding to the amorphous semiconductor film by discharge of an inert gas under reduced pressure in a reaction chamber provided with a cathode;
Have a third step of forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film after the second step,
Among the plurality of types of elements contained in the cathode, one type is a catalytic element that promotes crystallization of the amorphous semiconductor film, and the other type is an impurity element that imparts p-type to the amorphous semiconductor film. There is provided a method for manufacturing a semiconductor device. A first step of forming an insulating film on the substrate and an amorphous semiconductor film on the insulating film;
A second step of discharging a plurality of kinds of elements contained in the cathode by sputtering and adding to the amorphous semiconductor film by discharge of an inert gas under reduced pressure in a reaction chamber provided with a cathode;
Have a third step of obtaining a crystalline semiconductor film by crystallizing the amorphous semiconductor film after the second step,
Among the plurality of types of elements contained in the cathode, one type is a catalytic element that promotes crystallization of the amorphous semiconductor film, and the other type is an impurity element that imparts p-type to the amorphous semiconductor film. There is provided a method for manufacturing a semiconductor device. According to claim 1 or claim 2, wherein the first step to the third step, without exposing the substrate to air, a method for manufacturing a semiconductor device, which comprises carrying out successively under reduced pressure. A first step of forming an amorphous semiconductor film on a substrate in a first reaction chamber;
A catalytic element for promoting crystallization of the amorphous semiconductor film and an element for imparting p-type by sputtering the cathode by discharge of an inert gas under reduced pressure in a second reaction chamber equipped with a cathode A second step of simultaneously adding to the amorphous semiconductor film;
And a third step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the second step. A first step of forming an insulating film on a substrate and an amorphous semiconductor film on the insulating film in a first reaction chamber;
A catalytic element for promoting crystallization of the amorphous semiconductor film and an element for imparting p-type by sputtering the cathode by discharge of an inert gas under reduced pressure in a second reaction chamber equipped with a cathode A second step of simultaneously adding to the amorphous semiconductor film;
And a third step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the second step. A first step of forming an amorphous semiconductor film on a substrate in a first reaction chamber;
In the second reaction chamber equipped with a cathode, the amorphous material contained in the cathode is obtained by sputtering the cathode by discharge with a mixed gas of an inert gas and a gas containing a periodic group 13 element under reduced pressure. A second step of simultaneously adding to the amorphous semiconductor film a catalyst element that promotes crystallization of the crystalline semiconductor film and the group 13 element of the periodic table;
And a third step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the second step. A first step of forming an insulating film on a substrate and an amorphous semiconductor film on the insulating film in a first reaction chamber;
In the second reaction chamber equipped with a cathode, the amorphous material contained in the cathode is obtained by sputtering the cathode by discharge with a mixed gas of an inert gas and a gas containing a periodic group 13 element under reduced pressure. A second step of simultaneously adding to the amorphous semiconductor film a catalyst element that promotes crystallization of the crystalline semiconductor film and the group 13 element of the periodic table;
And a third step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the second step. In any one of claims 4 to 7, production of the first step and the second step, a semiconductor device which is characterized in that the substrate without being exposed to the atmosphere, continuously under vacuum Method. A first step of forming an amorphous semiconductor film in the first reaction chamber;
A catalyst that promotes crystallization of the amorphous semiconductor film among the elements contained in the first cathode by discharge of an inert gas under reduced pressure in a second reaction chamber provided with the first cathode. A second step of releasing the element by sputtering and adding it to the amorphous semiconductor film;
After the second step, among the elements contained in the second cathode by discharge of an inert gas under reduced pressure in a third reaction chamber provided with the second cathode, the amorphous semiconductor A third step of releasing an element imparting p-type to the film by sputtering and adding the element to the amorphous semiconductor film;
And a fourth step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the third step. A first step of forming an amorphous semiconductor film in the first reaction chamber;
Among the elements contained in the first cathode by an inert gas discharge under reduced pressure in the second reaction chamber provided with the first cathode, an element imparting p-type to the amorphous semiconductor film A second step of releasing by sputtering and adding to the amorphous semiconductor film;
After the second step, among the elements contained in the second cathode by discharge of an inert gas under reduced pressure in a third reaction chamber provided with the second cathode, the amorphous semiconductor A third step of releasing a catalytic element that promotes crystallization of the film by sputtering and adding to the amorphous semiconductor film;
And a fourth step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the third step. A first step of forming an insulating film on a substrate in the first reaction chamber and an amorphous semiconductor film on the insulating film;
A catalyst that promotes crystallization of the amorphous semiconductor film among the elements contained in the first cathode by discharge of an inert gas under reduced pressure in a second reaction chamber provided with the first cathode. A second step of releasing the element by sputtering and adding it to the amorphous semiconductor film;
Among the elements contained in the second cathode by an inert gas discharge under reduced pressure in the third reaction chamber provided with the second cathode, an element imparting p-type to the amorphous semiconductor film A third step of releasing the material by sputtering and adding the amorphous semiconductor film to the amorphous semiconductor film;
And a fourth step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the third step. A first step of forming an insulating film on a substrate and an amorphous semiconductor film on the insulating film in a first reaction chamber;
Among the elements contained in the first cathode by an inert gas discharge under reduced pressure in the second reaction chamber provided with the first cathode, an element imparting p-type to the amorphous semiconductor film A second step of releasing the material by sputtering and adding the amorphous semiconductor film to the amorphous semiconductor film;
Catalyst that promotes crystallization of amorphous semiconductor film among elements contained in second cathode by discharge of inert gas under reduced pressure in third reaction chamber provided with second cathode A third step of releasing the element by sputtering and adding it to the amorphous semiconductor film;
And a fourth step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the third step. A first step of forming an amorphous semiconductor film in the first reaction chamber;
A catalytic element for promoting crystallization of the amorphous semiconductor film and an element for imparting p-type by sputtering the cathode by discharge of an inert gas under reduced pressure in a second reaction chamber equipped with a cathode A second step of simultaneously adding to the amorphous semiconductor film;
A third step of crystallizing the amorphous semiconductor film after the second step to form a crystalline semiconductor film;
A fourth step of patterning the crystalline semiconductor film to form a semiconductor film divided into islands;
A fifth step of forming an insulating film on the island-divided semiconductor film;
And a sixth step of gettering the catalytic element in the semiconductor film divided into islands by performing a heat treatment after the fifth step. A first step of forming an amorphous semiconductor film in the first reaction chamber;
Catalyst that promotes crystallization of amorphous semiconductor film among elements contained in first cathode by discharge of inert gas under reduced pressure in second reaction chamber equipped with first cathode A second step of releasing the element by sputtering and adding it to the amorphous semiconductor film;
After the second step, among the elements contained in the second cathode by the discharge of an inert gas under reduced pressure in the second reaction chamber provided with the second cathode, the amorphous semiconductor A third step of releasing an element imparting p-type to the film by sputtering and adding the element to the amorphous semiconductor film;
A fourth step of crystallizing the amorphous semiconductor film after the third step to form a crystalline semiconductor film;
A fifth step of patterning the crystalline semiconductor film to form a semiconductor film divided into islands;
A sixth step of forming an insulating film on the island-divided semiconductor film;
And a seventh step of performing gettering of the catalytic element in the semiconductor film divided into islands by performing heat treatment after the sixth step. A first step of forming an amorphous semiconductor film in the first reaction chamber;
Among the elements contained in the first cathode by an inert gas discharge under reduced pressure in the second reaction chamber provided with the first cathode, an element imparting p-type to the amorphous semiconductor film A second step of releasing by sputtering and adding to the amorphous semiconductor film;
After the second step, among the elements contained in the second cathode by discharge of an inert gas under reduced pressure in a third reaction chamber provided with the second cathode, the amorphous semiconductor A third step of releasing a catalytic element that promotes crystallization of the film by sputtering and adding to the amorphous semiconductor film;
A fourth step of crystallizing the amorphous semiconductor film after the third step to form a crystalline semiconductor film;
A fifth step of patterning the crystalline semiconductor film to form a semiconductor film divided into islands;
A sixth step of forming an insulating film on the island-divided semiconductor film;
And a seventh step of gettering the catalytic element in the semiconductor film divided into islands by performing a heat treatment after the sixth step. In any one of claims 9 to 15, wherein the first step to the third step, the method for manufacturing a semiconductor device, which comprises carrying out successively under reduced pressure. The catalyst element according to any one of claims 4 to 7 , and 9 to 15 , wherein the catalyst element is selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. A method for manufacturing a semiconductor device, using one or more kinds of elements. The impurity element imparting the p-type according to any one of claims 4 to 7 and claim 9 to claim 15 is one or more selected from B, Al, and Ga. A method for manufacturing a semiconductor device. Claims 4 to 7, in any one of claims 9 to 15, a method of crystallizing the amorphous semiconductor film, the method carried out by heating by thermal conduction or radiation, the irradiation of Les Za light performing a method, or a method for manufacturing a semiconductor device, characterized in that both in combination is one selected from a method carried out simultaneously or sequentially. Claims 4 to 7, in any one of claims 9 to 15, wherein the inert gas and wherein the He, Ar, Kr, Ne, that is one or more selected from _{N 2} A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 1, wherein hydrogen is added to the inert gas according to any one of claims 1, 2, 4 to 7 , and 9 to 15 . A first reaction chamber for forming an amorphous semiconductor film;
A second reaction chamber having a cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film and an impurity element for imparting p-type conductivity,
The first reaction chamber and the second reaction chamber are connected so as to be able to move without exposing the substrate to the atmosphere,
An apparatus for introducing an inert gas is connected to the second reaction chamber. A first reaction chamber for forming an amorphous semiconductor film;
A second reaction chamber comprising a first cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film;
A third reaction chamber provided with a second cathode containing an impurity element imparting p-type to the semiconductor,
The first reaction chamber to the third reaction chamber are connected so that the substrate can be moved without being exposed to the atmosphere,
Wherein the second reaction chamber to a third reaction chamber a semiconductor manufacturing apparatus characterized by being connected to means for introducing an inert gas. A first reaction chamber for forming an amorphous semiconductor film;
A second reaction chamber comprising a cathode containing a catalyst element for promoting crystallization of the amorphous semiconductor film and an impurity element for imparting p-type conductivity;
A third reaction chamber for performing heat treatment,
Between said first reaction chamber to the third reaction chamber is connected so as to be able to move without being exposed to the atmosphere of the substrate,
An apparatus for introducing an inert gas is connected to the second reaction chamber. A first reaction chamber for forming an amorphous semiconductor film;
A second reaction chamber comprising a first cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film;
A third reaction chamber provided with a second cathode containing an impurity element imparting p-type to the semiconductor;
A fourth reaction chamber for performing heat treatment,
The first reaction chamber to the fourth reaction chamber are connected so that the substrate can be moved without being exposed to the atmosphere,
Wherein the second reaction chamber to a third reaction chamber a semiconductor manufacturing apparatus characterized by being connected to means for introducing an inert gas. A first reaction chamber for forming an amorphous semiconductor film;
A second reaction chamber having a cathode and an anode capable of holding the substrate on the side facing the cathode;
The first reaction chamber and the second reaction chamber are connected so as to be able to move without exposing the substrate to the atmosphere,
A means for introducing an inert gas is connected to the second reaction chamber,
A semiconductor manufacturing apparatus, wherein a target made of a catalytic element for promoting crystallization of an amorphous semiconductor film and a target made of an impurity element for imparting p-type to the semiconductor are arranged on the cathode. A first reaction chamber for forming an amorphous semiconductor film;
A second reaction chamber having a cathode and an anode capable of holding the substrate on the side facing the cathode;
The first reaction chamber and the second reaction chamber are connected so as to be able to move without exposing the substrate to the atmosphere,
A means for introducing an inert gas is connected to the second reaction chamber,
The semiconductor manufacturing apparatus, wherein the cathode has a surface made of a catalytic element for promoting crystallization of an amorphous semiconductor film, and a target made of an impurity element imparting p-type to the semiconductor is disposed. A first reaction chamber for forming an amorphous semiconductor film;
A second reaction chamber having a cathode and an anode capable of holding the substrate on the side facing the cathode;
The first reaction chamber and the second reaction chamber are connected so as to be able to move without exposing the substrate to the atmosphere,
A means for introducing an inert gas is connected to the second reaction chamber,
The semiconductor manufacturing apparatus, wherein the cathode has a surface made of an impurity element imparting p-type to the semiconductor, and a target made of a catalytic element for promoting crystallization of the amorphous semiconductor film is arranged.

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