JP4057502B2 - Digital pulse width conversion circuit - Google Patents

Description

  The present invention relates to a circuit technology for interconverting between a digital value and a pulse width, and in particular, converts a plurality of input signals in parallel from a digital value to a pulse width or from a pulse width to a digital value with low power consumption. The present invention relates to a digital / pulse width conversion circuit and a pulse width / digital conversion circuit.

  Conventionally, as a digital pulse width conversion circuit that converts a digital input value into a pulse having a time width proportional to the digital input value, the count value output by a counter operated by a clock is compared with the digital input value. It is widely known that the pulse output falls at the timing when both coincide (see, for example, Patent Document 1).

  For example, FIG. 13 is a diagram showing an example of a conventional digital pulse width conversion circuit (see FIG. 1 of Patent Document 1). The conventional digital pulse width conversion circuit shown in FIG. 13 includes a strobe detection circuit 101, a latch circuit 102, a counter 103, a digital comparator 104, and a JK flip-flop 105.

  When the strobe signal NOT (STB) is input, the strobe detection circuit 101 outputs timing enable signals E1 and E2 at the subsequent rising edge of the clock CLK. The timing enable signal E1 becomes L level at the next rising edge of the clock. On the other hand, the timing enable signal E2 is always at the H level while the reset signal NOT (reset) is at the H level.

The latch circuit 102 latches 16-bit digital data D _{0 to} D ₁₅ input from the outside, and outputs the latched data as latch data Q _{0 to} Q ₁₅ . Then, 16-bit counter 103 counts the clock CLK, and outputs the count value C ₀ -C _15. Further, the counter 103 outputs a count-out signal CO when the count value becomes FFFF.

Digital comparator 104 compares the latched data Q ₀ to Q ₁₅ and count value C ₀ -C _15, until the count value C ₀ -C ₁₅ exceeds latched data Q ₀ to Q _15, JK flip-flop outputs H level to 105, when the count value C ₀ -C ₁₅ exceeds the latched data Q ₀ to Q _15, inverts the output values to the L level.

  In the JK flip-flop 105, at the beginning of the processing cycle, the output signal of the digital comparator 104 is input to the input terminal J, and the output Q holds the H level. Further, at the rising timing of the first clock CLK after the output signal of the digital comparator 104 is inverted to the L level, the JK flip-flop 105 inverts the output Q to the L level. When the count out signal C.O. is input, the JK flip-flop 105 returns the output Q to the H level.

With such a configuration, a pulse having a time width proportional to the values of the digital data D _{0 to} D ₁₅ is output to the output Q of the JK flip-flop 105.

  On the other hand, the pulse width / digital conversion circuit has been widely used in integration type AD converters (see, for example, Patent Documents 2 and 3 and Non-Patent Document 1).

  FIG. 14 is a block diagram of a conventional pulse width / digital conversion circuit used in the integrating AD converter.

The conventional pulse width / digital conversion circuit 201 has a simple configuration including an AND gate circuit 202 and a counter 203. The AND gate circuit 202 receives a pulse width modulated input pulse PW and a clock CLK. The AND gate circuit 202 outputs to the counter 203 a gate signal g that is the logical product of the input pulse PW and the clock CLK. The counter 203 counts the rising edges of the input gate signal g and outputs the counted value as an m-bit digital output D = {D ₀ ,..., D _m−1 }.

With this configuration, the AND gate circuit 202 is enabled when the input pulse PW is at the H level, and the AND gate circuit 202 is disabled when the input pulse PW is at the L level. While the AND gate circuit 202 is valid, the clock CLK is output as the gate signal g. The counter 203 counts the clock output as the gate signal g. Thereby, a count value proportional to the width of the input pulse PW is obtained as a digital output D = {D ₀ ,..., D _m−1 }.
JP-A-4-2222 Japanese Patent Application Laid-Open No. 8-204466 JP-A-62-265820 Suzuki Hachiji and Yoshida Masaaki, “Introduction to Pulsed Digital Circuits”, first edition, Japan, Nikkan Kogyo Shimbun, July 26, 2001, p. 225-p. 232 Takashi Morie, Atsushi Iwata, “Image Recognition Integrated System Learning from Brain Functions”, IEICE Technical Report, CAS2002-37, VLD2002-51, DSP2002-77, June 2002

In recent years, the present inventors have devised a pulse width arithmetic circuit element (hereinafter referred to as “PWM pixel circuit”) that performs an operation using a pulse width (see, for example, Non-Patent Document 2). When a large-scale integrated circuit is configured using such elements, the PWM pixel circuit array 305 is configured by arranging the PWM pixel circuits 304 in an array as shown in FIG. Then, the data obtained by the calculation in each PWM pixel circuit array 305 is pulse width data PW = {PW ₀ ,..., PW _{n−1 in} parallel in order from the smallest column number according to the pulse output trigger XRST. } Is output. Here, n represents the number of rows of the PWM pixel circuit array 305. In the example of FIG. 15, n = 16. Usually, the degree of integration is further increased, and n is about several tens to several hundreds.

In the input part of such a PWM pixel circuit, in order to convert each digital input signal inputted in parallel with an external digital value into a pulse width PW = {PWin ₀ ,..., PWin _n-1 }, A pulse width conversion circuit is used. In addition, when data output as pulse width data PW = {PW ₀ ,..., PW _n-1 } from the PWM pixel circuit array 305 is input to a normal digital circuit, a pulse width / digital conversion circuit is used. The

  However, when the above conventional digital / pulse width conversion circuit or pulse width / digital conversion circuit is used for a large-scale PWM pixel circuit array, each digital / pulse width conversion circuit or each pulse width / digital conversion circuit There is a problem that the total power consumption becomes considerably large.

  That is, when performing pulse width modulation of a large number of digital input values in parallel, a plurality of conventional digital pulse width conversion circuits shown in FIG. In contrast, each digital input value may be input. Then, by extracting the pulse output from each digital pulse width conversion circuit, parallel pulse width modulation becomes possible.

  In this case, however, the switching operation by the clock is frequently performed in each digital pulse width conversion circuit. Therefore, if the driving power of all the digital pulse width conversion circuits is summed up, a considerably large amount of power is consumed. Therefore, it is difficult to use a large number of digital input values in a pulse width modulation in parallel in a device such as a portable device that requires low power consumption.

  Further, when the pulse width / digital conversion circuit 201 as shown in FIG. 14 is used for each of a large number of pulses output from the PWM pixel circuit in each row, the large number of counters 203 perform a switching operation in parallel. It will be. Therefore, for example, even when the counter 203 is configured by CMOS, the charge / discharge power consumption when the counter 203 charges / discharges the load capacity during switching increases. This increase in charge / discharge power consumption becomes more significant as the number n of rows of the PWM pixel circuit array is larger.

  In addition, since many counters 203 operate in parallel, the switching noise of the counter 203 increases. Therefore, noise countermeasures for the entire circuit are required.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit technique for performing mutual conversion between a digital value and a pulse width, which operates with low power consumption and generates less noise from the circuit. That is, a digital / pulse width conversion circuit that converts a plurality of digital input values into a pulse width in parallel and a pulse width / digital conversion circuit that converts a plurality of input pulses into a digital value in parallel are provided.

  A first configuration of a digital pulse width conversion circuit according to the present invention includes a counter that counts clocks and outputs the count value as a digital signal, an input value that is input from the outside as a digital value, and the count value. In comparison, an output pulse having a time width from a predetermined time point to a time point when the input value matches the count value, or a value obtained by subtracting the input value from a predetermined maximum count value matches the count value. Pulse generation means for generating an output pulse having a time width from the time point until the count value reaches the maximum count value, and has a plurality of the pulse generation means and each of the pulse generation means The means is characterized in that an input value inputted to each is compared with a common count value outputted by one counter.

  According to this configuration, each pulse generation means outputs an output pulse until a point when the input value and the count value input to each other match, or a value obtained by subtracting the input value from a predetermined maximum count value and the count value. An output pulse having a time width from when the counts coincide with each other until the count value reaches the maximum count value is output, and when both coincide, the output pulse is lowered. Thereby, an output pulse having a time width specified by the input value is generated.

  Here, each pulse generation means uses the count value generated by one counter as the count value to be compared with the input value. As a result, the counter need only drive the wiring for outputting the count value to each pulse generating means. For this reason, it is possible to significantly reduce the power consumption as compared with the case where each pulse generating means is provided with a counter.

  Further, by using one counter, it is possible to reduce the circuit layout area as compared with the case where each pulse generating means is provided with a counter. Therefore, the circuit can be miniaturized.

  According to a second configuration of the digital pulse width conversion circuit of the present invention, in the first configuration, each of the pulse generation means includes a pulse width register that latches the input value input from the outside, and the pulse width A timing trigger generation circuit that compares each bit of the input value latched by the register with each bit of the count value output by the counter and generates a trigger when the two completely match, and the timing trigger generation And an output pulse inversion circuit that inverts the truth value of the output pulse when the circuit generates a trigger.

  According to this configuration, first, an input value input from the outside is latched in the pulse width register. Then, the output pulse inverting circuit starts outputting the output pulse. The pulse width register latches the input value and outputs it to the timing trigger generation circuit. The timing trigger generation circuit compares the count value output by the counter with the output value of the pulse width register, and generates a trigger at a timing at which both coincide completely. Then, the output pulse inversion circuit inverts the output pulse and falls when the trigger is output from the timing trigger generation circuit. Thereby, each pulse generation means can generate a pulse having a time width proportional to the value specified by the input value.

  According to a third configuration of the digital pulse width conversion circuit of the present invention, in the first configuration, each of the pulse generation means latches a reference value that is a digital value representing a rising timing of the output pulse. A value register, an addition circuit that outputs an addition value of the reference value and the input value that is a digital value input from the outside, a pulse width register that latches an output value of the addition circuit, and the reference value register A switching circuit for switching and outputting either the latched digital value or the digital value latched by the pulse width register, each bit of the digital value output from the switching circuit, and each count value output by the counter A timing trigger generation circuit that generates a trigger when the two match completely, and the timing trigger generation circuit An output pulse inversion circuit that inverts the truth value of the output pulse when a trigger occurs, and the switching circuit is configured to output the reference when the output pulse output by the output pulse inversion circuit is a false value. The digital value latched by the value register is output, and when the output pulse output from the output pulse inverting circuit is a true value, switching is performed so that the digital value latched by the pulse width register is output. .

  According to this configuration, first, a digital value (hereinafter referred to as “initial value”) representing the rising timing of the output pulse is latched in the reference value register. The adder circuit adds the input value input from the outside and the initial value, and the added value is latched in the pulse width register. In this state, the output pulse inversion circuit does not output a pulse. Therefore, the switching circuit outputs the initial value latched in the reference value register to the timing trigger generation circuit.

  The timing trigger generation circuit compares the count value output by the counter with the output value of the reference value register, and generates a trigger at a timing at which both coincide completely. Then, the output pulse inverting circuit inverts the output pulse when the trigger is output from the timing trigger generating circuit and starts up. When the output pulse rises, the switching circuit switches so as to output the added value latched in the pulse width register to the timing trigger generation circuit.

  The timing trigger generation circuit compares the count value output by the counter with the output value of the pulse width register, and generates a trigger at a timing at which both coincide completely. Then, the output pulse inversion circuit inverts the output pulse and falls when the trigger is output from the timing trigger generation circuit. Thereby, each pulse generation means can generate a pulse having a time width proportional to the value specified by the input value.

  In this way, by using the same circuit to switch the rise and fall of the output pulse, it is possible to generate a pulse with a time width that is directly proportional to the input value without being affected by the circuit delay. Become.

  Here, as the initial value, a common initial value may be used for each pulse generation unit, or a different initial value may be used for each pulse generation unit.

  A first configuration of the pulse width / digital conversion circuit according to the present invention includes a counter that counts a clock and outputs the count value as a digital signal, and a counter that outputs the counter at the end of an input pulse input from the outside. A terminal latch circuit that latches a numerical value, and has a plurality of the terminal latch circuits, and each terminal latch circuit inputs a common count value output by one counter. And latching at the end of each input pulse.

  According to this configuration, while the input pulse is being input, the counter counts the clock and continues to output the count value as a digital value. At the end of each input pulse, a termination latch circuit corresponding to the input pulse latches the output value of the counter. Accordingly, a digital value proportional to the pulse width of each input pulse can be obtained by referring to the output of each termination latch circuit after a predetermined time has elapsed.

  Here, each termination latch circuit uses the count value output by the common counter as the count value latched at the end of the input pulse. The counter only switches the output value against the parasitic capacitance of the wiring for outputting the count value to each terminal latch circuit, and power consumption during driving is small. For this reason, it is possible to significantly reduce power consumption as compared with a case in which a counter is provided for each termination latch circuit.

  Further, by using one counter, it is possible to suppress noise generated when switching the output of the counter. Therefore, an error occurring at the time of pulse width digital conversion by adding jitter and noise to the pulse width can be minimized.

  Further, since each termination latch circuit latches the output value of the common counter, there is no variation in the timing of switching the count value for each input pulse. Therefore, it is possible to prevent variations in timing error between input pulses due to jitter at the time of switching of the counter.

  According to a second configuration of the pulse width / digital conversion circuit of the present invention, in the first configuration, a start-end latch circuit that latches a count value output by the counter at a start end of the input pulse, and a termination latch circuit. A subtracting circuit that calculates and outputs a difference between the digital output value and the digital output value of the start end latch circuit is provided corresponding to each end latch circuit.

  According to this configuration, the subtraction circuit subtracts the counter value latched at the start of the input pulse by the start end latch circuit from the counter value latched at the end of the input pulse by the end latch circuit, and outputs the subtraction value. Therefore, a digital value that is directly proportional to the pulse width of each input pulse can be obtained as the output of each subtraction circuit.

  Further, since the pulse timing is measured at the start and end, the pulse width digital conversion can be performed correctly even when there is a timing shift between the input pulses.

  As described above, according to the first configuration of the digital pulse width conversion circuit of the present invention, each pulse generation unit uses a count value generated by one counter, so that a large number of pulses can be obtained. Can be provided in parallel, a digital pulse width conversion circuit with extremely low power consumption can be provided. At the same time, the layout area of the circuit can be reduced, and the circuit can be reduced in size.

  In addition, according to the second configuration of the digital pulse width conversion circuit of the present invention, each pulse generation means can generate a digital pulse capable of generating a pulse having a time width proportional to the value specified by the input value. A pulse width conversion circuit can be provided.

  Further, according to the third configuration of the digital pulse width conversion circuit of the present invention, each pulse generating means can generate a pulse having a time width that is directly proportional to the input value without being affected by the circuit delay. It becomes possible. Therefore, a digital pulse width conversion circuit with high conversion accuracy can be provided.

  In addition, according to the first configuration of the pulse width / digital conversion circuit according to the present invention, each termination circuit uses a count value generated by one counter, so that a large number of input pulses are input, Even when pulse width digital conversion is simultaneously performed on these, power consumption can be kept low. In particular, when used at the output interface of a pulse width arithmetic circuit in which the number of input pulses is several tens or more, power consumption can be significantly reduced as compared with the case of using a conventional circuit.

  In addition, since each termination circuit uses a count value generated by one counter, the circuit layout area can be reduced at the same time, and the circuit can be downsized. As described above, since the circuit according to the present invention has power saving and area saving, it is suitable for use in an internal circuit of an LSI used for a portable device.

  Further, since each termination circuit uses a count value generated by one counter, the influence of the switching noise of the counter can be minimized. Therefore, it is possible to suppress jitter / noise errors that occur during pulse width digital conversion.

  In addition, it is possible to prevent the timing error between the input pulses from varying due to jitter at the time of switching of the counter. Therefore, it becomes easy to correct the jitter inherent to the counter caused by the tolerance at the time of manufacturing the counter.

  According to the second configuration of the pulse width / digital conversion circuit of the present invention, a digital value directly proportional to the pulse width of each input pulse can be obtained as the output of each subtraction circuit. Therefore, it is possible to provide a pulse width / digital conversion circuit capable of performing pulse width digital conversion that is directly proportional to the pulse width of input pulses input in parallel. Further, even when there is a variation in the start edge of each input pulse, it is possible to correctly perform pulse width digital conversion.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

1 is a block diagram showing the configuration of a digital pulse width conversion circuit according to a first embodiment of the present invention. The digital pulse width conversion circuit 1 according to this embodiment includes a plurality of pulse generation circuits 2-0 to 2- (n-1) and one counter 3 arranged in parallel. The data input terminal Din of the pulse generating circuit 2-0~2- (n-1), each of the digital input values of m bits x ₀ ~x _n-1 are inputted. Then, from the pulse output terminal Pout of the pulse generating circuit 2-0~2- (n-1), pulse PW ₀ ~PW _n-1 of the digital input value x ₀ ~x time width proportional to _n-1 Is output.

  The counter 3 counts the clock clock input from the outside and outputs it as an m-bit count value. The counter value output from the counter 3 is commonly input to the counter value input terminals CNT of the pulse generation circuits 2-0 to 2- (n-1).

  FIG. 2 is a block diagram showing the configuration of each pulse generation circuit of FIG. The pulse generation circuit 2-i (i∈ {0, 1,..., N−1}) includes a pulse width register 12, a timing trigger generation circuit 14, and an output pulse inversion circuit 15.

Pulse width register 12 latches the rising of the input value x _i update input renew an m-bit digital value input from the outside, and outputs the value to the output node. The timing trigger generation circuit 14 compares each bit of the m-bit digital value output from the pulse width register 12 with each bit of the m-bit count value output from the counter 3, and the two match completely. When trigger occurs.

The timing trigger generation circuit 14 includes m EXOR gates 16-0 to 16- (m-1) and one NOR gate 17. An output bit from the pulse width register 12 is input to one of the inputs of each EXOR gate 16-0 to 16- (m-1), and an output bit from the counter 3 is input to the other input. The The outputs P _{0 to} P _m−1 of the EXOR gates 16-0 to 16- (m−1) are input to the NOR gate 17. The NOR gate 17 outputs an inverted output of the logical sum of the outputs P _{0 to} P _m−1 of the EXOR gates 16-0 to 16-(m−1) to the output pulse inversion circuit 15.

That is, when each digital input value x _i (i∈ {0, 1,..., N−1}) and the counter output value CNT are expressed by (Equation 1) and (Equation 2), the timing trigger generation circuit 14 The output T _i is expressed as (Equation 3). Here, it is assumed that x _i is not 0.

（数３）より、タイミングトリガ発生回路１４の出力T_iはデジタル入力値ｘ_iとカウンタの出力値CNTが、総てのビットにおいて一致したときに１となることが分かる。

(Equation 3) shows that the output T _i of the timing trigger generation circuit 14 becomes 1 when the digital input value x _i matches the output value CNT of the counter in all bits.

Output pulse inverting circuit 15, when the timing trigger generation circuit 14 has generated the trigger, to reverse the truth value of the output pulse PW _i. The output pulse inverting circuit 15 is configured by a T flip-flop (hereinafter referred to as “T-FF”). An output value from the NOR gate 17 is input to the trigger input terminal T of the output pulse inverting circuit 15. Further, from the output terminal Q of the output pulse inversion circuit 15, a pulse PW _i is output.

  The operation of the digital pulse width conversion circuit according to this embodiment configured as described above will be described below with reference to the timing chart of FIG.

First, in the initial state immediately after the power is turned on, it is assumed that all the count values CNT of the counter 3 are at the H level and the input value x _i is 0. In this state, at time t ₀ , the reset input reset input to the counter 3 and the pulse width register 12 is made valid (L level). As a result, all count values CNT of the counter 3 are reset to zero. The pulse width register 12 resets all stored values to 0 when the reset signal reset is set to L level. Then, the count value CNT of the counter 3 matches the output value of the pulse width register 12, and the output T _i of the timing trigger generation circuit 14 is inverted from the L level to the H level. Therefore, the output Pout _i of the output pulse inverting circuit 15 is inverted to H level, and a pulse starts to be output to the output Pout _i .

Next, at time t ₁ , an input value x _i (X _i ≠ (0, 0,..., 0)) is input from the external circuit to each pulse generation circuit 2-i. At this time, since the reset signal reset input to the pulse width register 12 is L level, all outputs of the pulse width register 12 remain zero.

Then, at time t _2, the the reset input reset is disabled (H level), the update signal renew is inverted from L level to H level. The update signal renew is input to the clock CLK input node of each pulse width register 12, and when the update signal renew is inverted to H level, the pulse width register 12 latches the value of the input value x _i at that time. . Accordingly, the output value of the pulse width register 12 is the input value x _i. On the other hand, since the count value CNT of the counter 3 is still 0, the output of the pulse width register 12 and the count value CNT of the counter 3 do not match, and the output T of the timing trigger generation circuit 14 is inverted from H level to L level. The counter 3 starts counting the clock clock when the reset signal reset is inverted from the L level to the H level. At this time, the pulse width register 12 continues to output the latched sum value x _i.

The counter 3 counts up with the clock clock, and the count value CNT of the counter 3 coincides with x _i that is the output value of the switching circuit 13 at time t ₃ . At this time, the output value T of the timing trigger generation circuit 14 is inverted from the L level to the H level. As a result, the output Pout _i of the output pulse inverting circuit 15 is inverted from the H level to the L level. As a result, the width of the pulse PW _i of the output Pout _i of the output pulse inverting circuit 15 is determined. Since this pulse width is proportional to the digital input value x _i , digital pulse width conversion is performed.

Further, at time t ₄ when the time t ₃ has elapsed one clock, the counter 3 is the output value x _i and mismatch count CNT of the counter 3 counts up switching circuit 13, the output T of the timing trigger generation circuit 14 _i is inverted from H level to L level.

The counter 3 continues counting until it counts up. During this time, since the count value CNT of the counter 3 and the input value x _i do not match, the output T _i of the timing trigger generation circuit 14 holds the L level, and the output of the output pulse inversion circuit 15 also holds the L level. Is done. When the counter 3 counts up, the count values of the counter 3 are all 0, and one cycle is completed. Subsequently, the same cycle is repeated.

As described above, each pulse generation circuit 2-i (i = 0,..., N-1) outputs an output pulse PW _i having a time width proportional to the value of the input value x _i . (However, this time width is strictly offset by 2 clocks during the period when the reset signal is L. This can be dealt with by subtracting 2 from x _{i in} advance.) pulse generating circuits 2-i, using the count value CNT output from the common counter 3, and compares the digital input value x _i. Therefore, the power consumption is extremely small as compared with the case where all the pulse generation circuits 2-i are provided with counters.

  That is, when all the pulse generation circuits 2-i are provided with counters, at least one of the switching elements in each counter is switched every clock. Therefore, for example, when a CMOS is used as the switching element, a through current and a charge / discharge current to the load flow along with the switching. Therefore, the power consumption of the entire digital pulse width conversion circuit is increased.

  On the other hand, when one counter 3 is driven and each pulse generation circuit 2-i switches pulses by referring to the output value of the common counter 3 as in the present embodiment, There are few through currents and charge / discharge currents to the load caused by switching of the switching elements, and power consumption is also small. Therefore, the power consumption of the digital pulse width conversion circuit 1 can be reduced.

  Further, since the counter 3 is shared, the circuit layout area is reduced, and the digital pulse width conversion circuit 1 can be downsized.

  FIG. 4 is a block diagram showing the configuration of the digital pulse width conversion circuit according to the second embodiment of the present invention.

In FIG. 4, the digital pulse width conversion circuit 1 ′ according to the second embodiment includes a plurality of pulse generation circuits 2-0 ′ to 2- (n−1) ′ arranged in parallel and one counter 3. The data input terminal Din of the pulse generating circuit 2-0~2- (n-1), each of the digital input values of m bits x ₀ ~x _n-1 are inputted. Then, from the pulse output terminal Pout of the pulse generating circuit 2-0'~2- (n-1) ', a pulse PW ₀ ~PW _n-1 that is proportional to the digital input value x ₀ ~x _n-1 Is output.

  The counter 3 counts the clock clock input from the outside and outputs it as an m-bit count value. This clock clock is also input in common to the clock input terminals clk of the pulse generation circuits 2-0 'to 2- (n-1)'. Further, the count value output from the counter 3 is commonly input to the counter value input terminals CNT of the pulse generation circuits 2-0 'to 2- (n-1)'.

Further, the m-bit reference value _xb is commonly input to the reference value input terminals Db of the pulse generation circuits 2-0 ′ to 2- (n−1) ′. This reference value _xb is a value that specifies the rising timing of the output pulses PW _{0 to} PW _n−1 .

  FIG. 5 is a block diagram showing the configuration of each pulse generation circuit of FIG. The pulse generation circuit 2-i ′ (i∈ {0, 1,..., N−1}) includes a reference value register 10, an addition / subtraction circuit 11, a pulse width register 12, a switching circuit 13, a timing trigger generation circuit 14, and an output. It has a pulse inversion circuit 15 '.

Reference value register 10 latches the reference value x _b, and outputs the value of the reference value x _b was latched. The addition / subtraction circuit 11 outputs an addition value x _i + x _b between the reference value x _b and an input value x _i which is a digital value input from the outside. The pulse width register 12 latches the output value (addition value x _i + x _b ) of the addition / subtraction circuit 11 at the rising edge of the update input renew.

When the output pulse PW _i output from the output pulse inverting circuit 15 ′ is a false value (L level), the switching circuit 13 outputs the digital value _xb latched by the reference value register 10, and the output pulse inverting circuit 15 ′. When the output pulse PW _i output from is a true value (H level), switching is performed so that the digital value x _i + x _b latched by the pulse width register 12 is output.

The timing trigger generation circuit 14 ′ compares each bit of the digital value output from the switching circuit 13 with each bit of the count value CNT output from the counter 3, and generates a trigger when the two match completely. To do. The timing trigger generation circuit 14 ′ is composed of m EXOR gates 16-0 to 16-(m−1) and one NOR gate 17. An output bit from the switching circuit 13 is input to one of the inputs of each EXOR gate 16-0 to 16- (m-1), and an output bit from the counter 3 is input to the other input. . The outputs P _{0 to} P _m−1 of the EXOR gates 16-0 to 16- (m−1) are input to the NOR gate 17. The NOR gate 17 outputs an inverted output of the logical sum of the outputs P _{0 to} P _m−1 of the EXOR gates 16-0 to 16- (m−1) to the output pulse inversion circuit 15 ′.

That is, each digital input value x _i (i∈ {0, 1,..., N−1}), each reference value x _b , and the output value CNT of the counter are expressed by (Equation 1), (Equation 4), (Equation 2). When the output value Pout of the output pulse inversion circuit 15 ′ is at the L level (Equation 5), the output T _i of the timing trigger generation circuit 14 is at the H level. Is expressed as (Equation 6).

Output pulse inverting circuit 15 'includes a timing trigger generation circuit 14' when occurs the trigger reverses the truth value of the output pulse PW _i. The output pulse inverting circuit 15 ′ is composed of a T-FF. The output value from the NOR gate 17 is input to the trigger input terminal T of the output pulse inverting circuit 15 ′. Further, from the output terminal Q of the output pulse inversion circuit 15 ', the output pulse PW _i is output.

  The operation of the digital pulse width conversion circuit according to this embodiment configured as described above will be described below with reference to the timing chart of FIG.

First, at time t ₁ , an input value x _i and a reference value x _b are input from an external circuit to each pulse generation circuit 2-i. Then, update signal renew is input to the clock input node CLK reset input node of the counter 3 at time t ₂ R and the reference value register 10 and the pulse width register 12 of each pulse generator circuit 2-i. Reference value register 10 and the pulse width register 12, the update signal renew is input at the rising time, respectively, to latch the value of the reference value x _b and the input value x _i of that time. The reference value register 10 outputs the latched reference value _xb , and the pulse width register 12 outputs the latched addition value x _i + _xb . On the other hand, at time t _1, the output of the output pulse inverting circuit is the L level, the switching circuit 13 outputs the value x _b input from the reference value register 10. The counter 3 resets the count value CNT to 0 and starts counting at the rising edge of the update signal renew.

Next, the counter 3 counts up, and the count value CNT of the counter 3 coincides with the reference value _xb that is the output value of the switching circuit 13 at time t ₃ . At this time, the output T _i of the timing trigger generation circuit 14 ′ is inverted to the H level. Thus, the output Pout of the output pulse inversion circuit 15 'is inverted from L level to H level, the output of the output pulse PW _i is started.

At time t _4, the output Pout of the output pulse inversion circuit 15 'Invert the H level, the switched input of the switching circuit 13, so outputs a value x _{b +} x _i input from the pulse width register 12 . Along with this, the output values of the EXOR gates 16-0 to 16- (m−1) also change. However, if x _i ≠ 0, the output values of the EXOR gates 16-0 to 16- (m−1) It will never be zero. Accordingly, the output T _i of the timing trigger generation circuit 14 ′ is inverted to the L level.

Further counter 3 is counted up at time t _5, the count value CNT of the counter 3 is coincident with the addition value x _{b +} x _i is an output value of the switching circuit 13. At this time, the output T _i of the timing trigger generation circuit 14 ′ is inverted to the H level. Thus, the output Pout of the output pulse inversion circuit 15 'is inverted from H level to L level, the output of the output pulse PW _i is stopped. Thus, the digital output pulses PW _i input value proportional to the time width in x _i is generated, the digital pulse width conversion is performed.

At time t ₆ , when the output of the output pulse inverting circuit 15 ′ is inverted to L level, the input of the switching circuit 13 is switched, and the switching circuit 13 outputs the value _xb input from the reference value register 10. . Along with this, the output values of the EXOR gates 16-0 to 16- (m−1) also change. However, if x _i ≠ 0, the output values of the EXOR gates 16-0 to 16- (m−1) It will never be zero. Accordingly, the output T _i of the timing trigger generation circuit 14 ′ is inverted to the L level.

The counter 3 continues counting until it counts up. During this time, since the counter value and the output value _xb of the switching circuit do not match, the output of the output pulse inverting circuit 15 ′ is held at the L level. When the counter 3 counts up, the counting is stopped and one cycle is completed. After counting up, the counter 3 maintains the output values (all at H level) at the time of counting up until the reset input node R is inverted to H level again.

As described above, each pulse generation circuit 2-i outputs an output pulse PW _i having a time width proportional to the value of the input value x _i . In this case, the pulse generating circuits 2-i, using the count value output from the common counter 3, and compares the reference value x _b or the sum x _{b +} x _i. Therefore, as in the first embodiment, the power consumption of the digital pulse width conversion circuit 1 can be reduced because the power consumption is extremely small compared to the case where all the pulse generation circuits 2-i are provided with counters. .

  Further, since the counter 3 is shared, the circuit layout area is reduced, and the digital pulse width conversion circuit 1 can be downsized.

In the present embodiment, the reference value register 10, the pulse width register 12, and with a switching circuit 13, the timing of the rise and fall of the output pulse PW _i, using a common timing trigger generation circuit 14 ' With the configuration in which it is generated, the pulse width of the output pulse PW _i can be accurately proportional to the input value x _i without being affected by circuit delay.

In the present embodiment, the configuration example is shown in which the rising points of the output pulses in the pulse generation circuits 2-0 ′ to 2- (n−1) ′ are aligned by the reference value _xb. In other words, the configuration may be such that the falling edge of the output pulse is matched. In this case, adding and subtracting circuit 11 configured to output a subtracted value x _b -x _i of an input value x _i from the reference value x _b is a digital value input from the outside is subtracted. Further, the switching circuit 13 outputs the digital value _xb latched by the reference value register 10 when the output pulse PW _i output from the output pulse inverting circuit 15 ′ is a true value (H level), and the output pulse inverting circuit When the output pulse PW _i output by 15 ′ is a false value (L level), the pulse width register 12 may be switched to output the digital value x _b −x _i latched.

Incidentally, without providing a subtraction circuit 11 to each pulse generating circuit 2-i, as a digital input signal x _i, may be given the result of the addition or subtraction from the reference value x _b the original input values.

  FIG. 7 is a block diagram showing the configuration of the pulse width / digital conversion circuit according to the third embodiment of the present invention.

The pulse width / digital conversion circuit 21 according to the third embodiment includes a counter 22 and n (n> 2) termination latch circuits 23-0 to 23- (n-1). The pulse width / digital conversion circuit 21 receives a clock CLK, a pulse output trigger XRST, and n input pulses PW _{0 to} PW _n−1 from the outside. Further, a power supply voltage V _DD and a substrate voltage V _SS are applied.

A pulse train having a constant cycle is input to the clock CLK. Input pulses PW _{0 to} PW _n−1 are pulses for inputting data as pulse width information, and are output from each PWM pixel circuit 304 as shown in FIG. 15, for example. The pulse output trigger XRST is a trigger for instructing output start of the input pulses PW _{0 to} PW _n−1 . The pulse output trigger XRST outputs an inverted pulse having a time width corresponding to the clock cycle in a cycle M times the cycle of the clock CLK (M ≧ 2 ^m ).

The counter 22 counts the clock CLK input from the outside and outputs the count values CNT _{0 to} CNT _m-1 as m-bit digital signals. Each termination latch circuit 23-i (i∈ {0, 1,..., N−1}) has count values CNT _{0 to} CNT _m−1 output by the counter 22 at the termination of the input pulse PW _i input from the outside. Latch. Each termination latch circuits 23-i, respectively, and outputs the latched count value CNT ₀ to CNT _m-1 digital output m bit D _{i, 0} to D _i, as _m-1.

FIG. 8 is a block diagram showing the internal configuration of the termination latch circuit of FIG.
The termination latch circuit 23-i (iε {0, 1,..., N−1}) is configured by m latches 24-0 to 24- (m−1) and one inverter 25. .

Input pulse PW _i input to the terminal latch circuit 23-i is level inverted by the inverter 25 is input to the clock input terminal clk of each latch 24-0~24- (m-1). The count values CNT _{0 to} CNT _m−1 of the counter 22 are input to the data input terminals D of the latches 24-0 to 24- (m−1), respectively. The pulse output trigger XRST is input to the reset input terminal NOT (R) of each latch 24-0-24- (m-1). Data output from the output terminals Q of the latches 24-0 to 24- (m-1) is output to the outside as _m- bit digital output data D _i = {D _{i, 0 to} D _{i, m-1} }. Is done.

  Each of the latch circuits 24-0 to 24- (m-1) uses a synchronous D flip-flop with an asynchronous reset input as shown in FIG.

  The operation of the pulse width / digital conversion circuit according to this embodiment configured as described above will be described below.

  FIG. 10 is a time chart illustrating changes in signal levels of the pulse width / digital conversion circuit according to the third embodiment.

A pulse having a width T / 2 is continuously input to the clock CLK at a constant period T. Pulse output trigger XRST at time t _1, and outputs the inverted pulse width T. Thus, the output of each latch 24-0~24- (m-1) is reset, the digital output data D _i is all 0 reset.

Then, the output of each input pulse PW _i (i∈ {0, 1,..., N−1}) is started from the rising time (time t ₂ ) of the pulse output trigger XRST. At the same time, the counter 22 starts counting the clock CLK. The counter 22 increases the count value by 1 at the rising edge of the clock CLK.

The input pulse PW _i is generated by a PWM pixel circuit 304 as shown in FIG. 15, for example. At this time, each PWM pixel circuit 304 starts outputting each input pulse PW _i from the rising point (time t ₂ ) of the pulse output trigger XRST, thereby synchronizing the input pulse PW _i with the start of counting of the counter 22. Can be output.

At time t _3, the input pulse PW _i is inverted from H level to L level. As a result, the level of the output NOT (PW _i ) of the inverter 25 rises from the L level to the H level. Each latch 24-j (jε {0, 1,..., M−1}) has a count value CNT _j input to the data input terminal D at the rising edge of the output NOT (PW _i ) of the inverter 25. The level is latched and output from the data output terminal Q.

Thus, each terminal latch circuits 23-i (i∈ {0,1, ..., n-1}) , the input pulse PW _i fall count value CNT of the counter 22 at the time of ⁽ⁱ⁾ = {CNT ^{( i)} ₀ , CNT ⁽ⁱ⁾ ₁ ,..., CNT ⁽ⁱ⁾ _m−1 } are latched. The count value CNT ⁽ⁱ⁾ is a value proportional to the pulse width of the input pulse PW _i.

When at least 2 ^m · T has elapsed since the counter 22 started counting, the digital output values of all the termination latch circuits 23-0 to 23- (n−1) are determined (of course, before that) In some cases). Therefore, after this fixed time point, the digital value proportional to the pulse width of each input pulse PW _{0 to} PW _n-1 is obtained by taking out the digital output value of each termination latch circuit 23-0 to 23- (n-1). Obtainable. That is, the pulse width digital conversion is completed.

In this way, each terminal latch circuit 23-i (iε {0, 1,..., N−1}) latches the count value CNT output from the common counter 22 at the terminal of the input pulse PW _i . Therefore, the counter 22 only switches the output value (count value CNT) against the parasitic capacitance of the wiring for outputting the count value CNT to each terminal latch circuit 23-i. Power consumption is small. Therefore, it is possible to significantly reduce the power consumption as compared with the case where the conventional pulse width digital conversion is used.

As a result of actual evaluation by computer simulation, when 80 input pulses PW _{0 to} PW ₇₉ are converted into digital pulse width in parallel, a conventional pulse width / digital conversion circuit as shown in FIG. 14 is used as a termination latch circuit. When used, it was estimated that 226mW of power would be consumed. On the other hand, when the pulse width / digital conversion circuit 21 according to the present embodiment is used, the power consumption when the same input pulse is subjected to pulse width digital conversion is 6.6 mW. Therefore, it was found that the power consumption can be reduced to about 1/50.

  Further, by using one counter 22, switching noise generated when the counter 22 is switched can be reduced. Therefore, the SN ratio of the circuit is improved. Therefore, jitter errors that occur during pulse width digital conversion due to jitter noise added to the pulse width can be minimized. Thereby, it can also be used for high-speed pulse width digital conversion.

The timing of the termination latch circuits 23-0~23- (n-1), so to latch the output value CNT of the common counter 22, the switching of the count value CNT for each input pulse PW ₀ ~PW _n-1 Variation does not occur. Therefore, it is possible to prevent the timing error between the input pulses PW _{0 to} PW _{n−1 from} being varied due to jitter at the time of switching of the counter 22.

  The pulse width / digital conversion circuit of the fourth embodiment is the same as the pulse width / digital conversion circuit 21 of the third embodiment shown in FIG. Replace with the circuit shown in.

  11, the configuration of the termination latch circuit 23-i (i∈ {0, 1,..., N−1}), the latches 24-0 to 24- (m−1), and the inverter 25 is the same as that in FIG. Therefore, the description is omitted. In addition to these, the pulse width / digital conversion circuit according to the present embodiment further includes a start-end latch circuit 30-i (i∈ {0, 1,..., N-1}) and a subtraction circuit 31-i. It is characterized by being.

Start latch circuit 30-i is the start (rising edge) of the input pulse PW _i, latches the count value CNT outputted from the counter 22. The subtraction circuit 31-i calculates the digital output value S _i = {S _{i of the start end} latch circuit 30-i from the digital output value E _i = {E _{i, 0 to} E _{i, m-1} } of the termination latch circuit 23- _{i. , 0 to} S _{i, m−1} } is calculated and output as a digital output value D _i = {D _{i, 0 to} D _{i, m−1} }.

Similarly to the termination latch circuit 23-i, the start end latch circuit 30-i corresponds to each of the bits CNT _{0 to} CNT _m−1 of the _m- bit count value, and latches 32-0 to 32- (m−1). ). These latches 32-0 to 32- (m-1) are constituted by the synchronous D flip-flops with the asynchronous reset input shown in FIG. 9, similarly to the latches 24-0 to 24- (m-1). ing.

However, to the clock terminal clk of the latch 32-0~32- (m-1) of the start latch circuit 30-i, without passing through the inverter 25, the input pulse PW _i is directly input. Therefore, the latch 32-0~32- (m-1) latches the count value CNT of the counter 22 at the time of rise of the input pulse PW _i.

  The operation of the pulse width / digital conversion circuit according to this embodiment configured as described above will be described below.

  FIG. 12 is a time chart illustrating changes in signal levels of the pulse width / digital conversion circuit according to the fourth embodiment.

As in the case of the third embodiment, pulses having a width T / 2 are continuously input to the clock CLK in the same manner as in the third embodiment. Pulse output trigger XRST at time t _1, and outputs the inverted pulse width T. As a result, the outputs of the latches 24-0 to 24- (m-1) and 32-0 to 32- (m-1) are reset, and the digital output data E _i and S _i are all reset to zero.

The counter 22 starts counting the clock CLK from the rise time (time t ₂ ) of the pulse output trigger XRST. The counter 22 increases the count value by 1 at the rising edge of the clock CLK.

At an appropriate time t ₄ after time t ₂ , the output of the input pulse PW _i (i∈ {0, 1,..., N−1}) is started. Due to the rise of the input pulse PW _i at time t _3, the latch 32-j (j∈ {0, 1,..., M−1}) of the start end latch circuit 30-i latches the output CNT _{j of the} counter 22. This is output from the data output terminal Q as a digital output value S _i = {S _{i, 0 to} S _{i, m-1} }.

At time t _4, the input pulse PW _i is inverted from H level to L level. As a result, the level of the output NOT (PW _i ) of the inverter 5 rises from the L level to the H level. Each latch 24-j (jε {0, 1,..., M−1}) has a count value CNT _j input to the data input terminal D at the rising edge of the output NOT (PW _i ) of the inverter 25. The level is latched and output from the data output terminal Q as a digital output value E _i = {E _{i, 0 to} E _{i, m-1} }.

The subtraction circuit 31-i calculates the digital output value S _i = {S _{i of the start end} latch circuit 30-i from the digital output value E _i = {E _{i, 0 to} E _{i, m-1} } of the termination latch circuit 23- _{i. , 0 to} S _{i, m−1} } is calculated and output as a digital output value D _i = {D _{i, 0 to} D _{i, m−1} }. Therefore, after time t ₃ , the digital output value D _i = {D _{i, 0 to} D _{i, m−1} } is a value that is directly proportional to the pulse width of the input pulse PW _i .

When at least 2 ^m · T has elapsed since the counter 22 started counting, all the terminal latch circuits 23-0 to 23- (n−1) and the subtracting circuits 31-0 to 31- (n− The digital output value of 1) is determined (of course, it may be determined before that). Therefore, after this fixed time point, the digital value D _i proportional to the pulse width of each input pulse PW _{0 to} PW _n-1 is obtained by taking out the digital output value of each subtraction circuit 31-0 to 31- (n-1). = {D _{i, 0 to} D _{i, m-1} } can be obtained. That is, the pulse width digital conversion is completed.

As described above, in this embodiment, the count value of the counter 22 at the start and end of each input pulse is latched, and the difference between the two is calculated to obtain a digital output value, whereby the rising edge of each input pulse PW _i is obtained. Need not be synchronized. Moreover, it is not necessary to count start timing of the rising and the counter 22 for each input pulse PW _i also synchronized.

  Therefore, it is possible to use the pulse width / digital conversion circuit according to this embodiment even in a circuit in which a modulation pulse is input asynchronously, such as a communication circuit.

The digital output values S _i and E _i may be directly output to the outside without preparing the subtracting circuit 31-i, and the subtraction may be performed by an externally prepared subtracter.

It is a block diagram showing the structure of the digital pulse width conversion circuit which concerns on Example 1 of this invention. FIG. 2 is a block diagram illustrating a configuration of each pulse generation circuit in FIG. 1. It is a timing chart showing the operation of the digital pulse width conversion circuit according to the first embodiment of the present invention. It is a block diagram showing the structure of the digital pulse width conversion circuit which concerns on Example 2 of this invention. FIG. 5 is a block diagram illustrating a configuration of each pulse generation circuit in FIG. 4. It is a timing chart showing operation | movement of the digital pulse width conversion circuit which concerns on Example 2 of this invention. It is a block diagram showing the structure of the pulse width and digital conversion circuit which concerns on Example 3 of this invention. FIG. 8 is a block diagram illustrating an internal configuration of a termination latch circuit in FIG. 7. FIG. 9 is a block diagram illustrating an internal configuration of the latch circuit of FIG. 8. 12 is a time chart illustrating changes in signal levels of a pulse width / digital conversion circuit according to a third embodiment. It is a block diagram showing the structure of the termination | terminus latch circuit of the pulse width / digital conversion circuit which concerns on Example 4 of this invention, a starting-end latch circuit, and a subtraction circuit. 10 is a time chart illustrating changes in signal levels of a pulse width / digital conversion circuit according to a fourth embodiment. It is a figure which shows an example of the conventional digital pulse width conversion circuit. It is a block diagram of a conventional pulse width / digital conversion circuit used in an integral type AD converter. It is a figure showing the structure of a PWM pixel circuit array.

Explanation of symbols

1, 1 'Digital pulse width conversion circuit 2-0 to 2- (n-1), 2-0' to 2- (n-1) 'Pulse generation circuit 3 Counter 10 Reference value register 11 Addition / subtraction circuit 12 Pulse width Register 13 Switching circuit 14, 14 'Timing trigger generation circuit 15, 15' Output pulse inversion circuit 16-0 to 16- (m-1) EXOR gate 17 NOR gate 21 Pulse width / digital conversion circuit 22 Counter 23-0 to 23 -(N-1) Termination latch circuit 24-0-24- (m-1) Latch 25 Inverter 30-0-30- (n-1) Start end latch circuit 31-0-31- (n-1) Subtraction circuit 32-0-32- (m-1) Latch

Claims (1)

A counter that counts the clock and outputs the count value as a digital signal;
An input value input as a digital value from the outside and the count value are compared, and an output pulse having a time width from a predetermined time point to a time point when the input value and the count value match, or a predetermined maximum count value A pulse generation means for generating an output pulse having a time width from a time point when the value obtained by subtracting the input value matches the count value to a time point when the count value reaches the maximum count value;
With
A plurality of the pulse generation means, each of the pulse generation means is for comparing an input value input to each with a common count value output by one counter ,
Each of the pulse generation means includes
A reference value register that latches a reference value that is a digital value indicating the rising timing of the output pulse;
An adder circuit that outputs an added value of the reference value and the input value that is a digital value input from the outside;
A pulse width register for latching the output value of the adder circuit;
A switching circuit that switches and outputs either the digital value latched by the reference value register or the digital value latched by the pulse width register;
A timing trigger generation circuit that compares each bit of the digital value output from the switching circuit with each bit of the count value output by the counter and generates a trigger when they completely match;
An output pulse inversion circuit that inverts the truth value of the output pulse when the timing trigger generation circuit generates a trigger;
With
The switching circuit outputs a digital value latched by the reference value register when the output pulse output from the output pulse inverting circuit is a false value, and when the output pulse output from the output pulse inverting circuit is a true value. Is switched so as to output a digital value latched by the pulse width register .

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