JP4060960B2 - Cache storage - Google Patents

Description

[0001]
(table of contents)
TECHNICAL FIELD OF THE INVENTION
Conventional technology
Problems to be solved by the invention
Means for solving the problem
BEST MODE FOR CARRYING OUT THE INVENTION
(A) Aspect description of the present invention (FIGS. 1 to 8)
(B) Description of one embodiment (FIGS. 9 to 20)
The invention's effect
[0002]
BACKGROUND OF THE INVENTION
The present invention relates to a cache storage device provided in a high-performance electronic computer, and more particularly to a cache storage device including a vector processing function for realizing a high-throughput operation.
The cache storage device is a high-speed, small-capacity temporary storage device for realizing high-speed processing based on the locality of various data referred to when executing processing by executing a program.
[0003]
On the other hand, the vector processing method realizes high-speed processing by combining a large number of data into vector processing data and performing the same operation (vector operation) on the data.
[0004]
[Prior art]
Conventionally, there is a vector processing method as a data processing method that enables high-speed data processing.
Early vector processing devices had an instruction system based on operations between memory and memory for vector processing data stored in a main memory (memory). Due to the delay associated with the operation, there is a problem that the delay time from the issue of the instruction to the actual start of the operation is long.
[0005]
Therefore, in the current vector processing device, there is a load / store method in which vector processing data is read from the main storage device to the vector register, the vector processing is performed between the register and the register, and the processing result is written back to the main storage device. It has become mainstream.
On the other hand, a cache storage device is used to perform a scalar operation (scalar processing), which is a general-purpose operation other than vector operations, at high speed.
[0006]
Here, the cache storage device is a high-speed, small-capacity temporary storage device that can hold various data (instruction data, operands, etc.) necessary for the operation, and is intended to shorten the access time to the main storage device. is there.
Therefore, if data that can be processed in parallel among the data to be processed is subjected to vector processing and scalar processing is performed on other data, the processing speed can be further increased. Therefore, a scalar having a cache storage device can be obtained. More preferably, the processing device and the vector processing device are used in combination.
[0007]
Conventionally, a scalar processing device and a vector processing device are used in combination as follows.
(1) The scalar processing device and the vector processing device each access the main storage device independently. The vector processing device stores the vector processing data read from the main storage device in the vector register, and directly exchanges the vector processing data with the vector register.
(2) The vector processing device accesses the main storage device via the cache storage device for the scalar processing device. Here, access to the main storage device is performed by the cache storage device, and the vector processing device stores vector processing data read from the main storage device by the cache storage device in the vector register, and a vector is transferred to and from this vector register. Exchange processing data.
[0008]
[Problems to be solved by the invention]
However, in the method (1), since the data transfer path for the scalar processing device and the data transfer path for the vector processing device are multiplexed as the data transfer path from the main storage device, the data transfer There is a problem that the number of physical signal lines used as paths increases and it becomes difficult to integrate the scalar processing device and the vector processing device on one chip.
[0009]
In the method (2), when vector processing is performed on vector processing data not in a continuous area, the vector processing data may be sparsely expanded on the cache storage device. Since the storage rate of effective data in the apparatus is significantly reduced, there is a problem that the efficiency of scalar processing is greatly reduced. Even when a conventional high-speed scalar processor alone performs a calculation corresponding to vector processing, the cache storage device should be used effectively in the same manner for vector processing data not arranged in a continuous area. I can't.
[0010]
Further, in both cases (1) and (2), two types of storage devices, a cache storage device and a vector register, are separately required, and the area occupied by these storage devices and their peripheral devices increases. Also, there is a problem that integration of the scalar processing device and the vector processing device becomes difficult.
The present invention has been devised in view of such problems, so that the scalar processing device and the vector processing device can be integrated on one chip without reducing the storage rate of valid data in the cache storage device. It is an object of the present invention to provide a cache storage device.
[0011]
[Means for Solving the Problems]
For this reason, the cache storage device of the present invention includes a scalar processing device that processes one or a pair of data with one instruction, a vector processing device that performs the same operation on a data set consisting of multiple elements with one instruction, and various types. A cache storage device interposed between a main storage device for storing data and having a storage unit for copying and storing the data stored in the main storage device, the storage unit comprising: Stores scalar processing data for the scalar processing device and has a function as a vector register for storing vector processing data for the vector processing device, The Vector register area Starting point information indicating the starting point of the vector register, an interleave factor indicating the arrangement interval of elements forming the area of the vector register, length information indicating the length of the vector register, type information or valid information of the vector register Control bit indicating Allocation information As A table to be held is further provided, the crossbar switch is regularly switched sequentially based on the allocation information with reference to the table, and the arrangement of the areas used as the vector registers is regularly distributed in the storage unit. The control unit is configured to control to store the vector processing data in the area of the vector register allocated and distributed to the storage unit (claim 1).
[0012]
This In this case, the vector register area may be dynamically allocated in the storage unit. 2 ).
[0013]
An area other than the area allocated as the vector register in the storage unit can be allocated as an area for storing the scalar processing data. 3 ).
Furthermore, transmission and reception of vector processing data is performed between the vector register and the vector processing device in the storage unit (claim). 4 ).
[0014]
Further, when the processing by the vector processing device using the vector register is finished, the control unit may release an area allocated as the vector register in the storage unit (claim). 5 ).
Specifically, when the processing by the vector processing device using the vector register ends, the control unit invalidates the allocation information held in the table, so that the storage unit stores the vector register as the vector register. The allocated space may be freed (claims) 6 ).
[0015]
DETAILED DESCRIPTION OF THE INVENTION
(A) Aspect description of the present invention
First, aspects of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an aspect of the configuration of the cache storage device of the present invention.
[0016]
As shown in FIG. 1, the cache storage device 1A of the present invention executes a single instruction (scalar processing instruction) and processes one or a pair of data and a group of arithmetic units (vector processing unit; Vector Pipeline) 3 and a main storage device 9 for storing various data.
FIG. 1 shows an example in which the cache storage device 1 </ b> A and the arithmetic unit group 3 are integrated on one chip 1.
Although not shown in FIG. 1, a lower-level cache storage device (secondary cache storage device, tertiary cache storage device, etc.) may be interposed between the cache storage device 1A and the main storage device 9. Good.
[0017]
As shown in FIG. 1, the cache storage device 1A includes a data memory (storage unit; N-way Set-associative Cache Data Array) 2, a vector access control device (control unit) 4, a mapping table 5, and an external access. A control device (External Data-Array Access Controller) 7 and an interface unit 8 are provided.
[0018]
Here, the core is a data network 2, an arithmetic unit group 3, a mapping table 5, a vector access control device 4, a data network 2 and an arithmetic unit group 3.
The computing unit group 3 includes a plurality of computing units 3a. The computing unit 3a is used to execute one instruction (vector processing instruction) and perform the same computation on a data set (vector processing data) composed of multiple elements. ) To perform vector processing (vector operation).
[0019]
The data memory 2 is composed of a plurality of banks 2a, and copies and stores the data stored in the main storage device 9. In the cache storage device 1A shown in FIG. 1, a data memory 2 having one read port and one write port per bank 2a is used. However, a data memory including a bank having a large number of ports may be used. .
[0020]
The data memory 2 has a function of storing data (scalar processing data) required when the scalar processing device 10 performs processing, and data (vector) required when the arithmetic unit group 3 performs processing. It has a function as a virtual vector register (hereinafter simply referred to as a vector register) for storing (processing data).
[0021]
In other words, the data memory 2 is configured as a data memory also serving as a cache, in which a vector register used for vector processing and a cache used for scalar processing are integrated.
Here, for example, as shown in FIG. 2, the vector register is allocated on the management unit (line) of the bank 2a of the data memory 2 by the interleaving method using the way and the line.
[0022]
Here, FIG. 2 shows a vector register virtually allocated on the bank 2a having the number of ways 5 and the number of lines 8. FIG. 2 shows an element (calculation element) as an example of the vector register. Shown are a vector register VR0 with five elements consisting of VR0-0, VR0-1,..., VR0-4, and a vector register VR1 with four elements consisting of elements VR1-0, VR1-1,. Has been. In the following, the vector register may be expressed as VR, V, VVR.
[0023]
Further, the mapping table 5 holds mapping information (allocation information) for designating the position of an area functioning as a vector register (hereinafter referred to as a vector register area) in the bank 2a of the data memory 2.
Here, the mapping information is described for each vector register, for example. In this case, the mapping information is composed of information as shown in the following (1) to (4). Such information can be expressed by 32 to 64 bits per entry.
(1) Start point information [way-line]
This is information indicating the starting point of each vector register area. For example, in the example shown in FIG. 2, in the case of the vector register VR0, [0-0] indicating the position of the element VR0-0 corresponds to the start point information, and in the case of the vector register VR1, the element VR1-0 is stored. [1-3] indicating the position corresponds to the starting point information.
(2) Interleave factor (incremental information) [way-line]
This is information indicating the arrangement interval of the elements forming the area of each vector register. In both the vector registers VR0 and VR1, the arrangement interval [1-1] of each element corresponds to the interleave factor.
(3) Length information
Information indicating the length of each vector register. In the case of the vector register VR0, [5] corresponds to length information, and in the case of the vector register VR1, [4] corresponds to length information. .
(4) Control bit
This is information indicating the type information [Precision] of each vector register, valid information, and the like. The type information indicates what precision information is stored, and the valid information indicates whether the mapping information is valid.
[0024]
Here, when performing vector processing, a processor (not shown) of the scalar processing device 10 writes mapping information about the vector register to the mapping table 5 in accordance with the number of vector registers necessary for calculation. It has become.
If the mapping table 5 corresponding to each vector register is managed dynamically and flexibly, the vector register can be dynamically and flexibly allocated in the data memory 2.
[0025]
Further, the vector access control device 4 refers to the mapping table 5 and, based on the mapping information, allocates a region used as a vector register to the data memory 2 in a distributed manner, and distributes and assigns to the data memory 2 Control is performed so that the vector processing data is stored in the vector register area.
[0026]
In the data memory 2, an area other than the area assigned as the vector register is assigned as an area for storing scalar processing data.
Further, the vector access control device 4 invalidates the mapping information held in the mapping table 5 when the processing by the arithmetic unit group 3 using the vector register is finished (specifically, the valid information is turned off). By doing so, the area allocated as the vector register in the data memory 2 is released.
[0027]
The vector access control device 4 exists in a coupling network that couples the data memory 2 and the computing unit group 3, and transmits and receives vector processing data between the vector register in the data memory 2 and the computing unit group 3. In order to be able to do this, it also has a function of dynamically switching the connection network to generate a flow of vector processing data between the data memory 2 and each arithmetic unit 3a.
[0028]
At this time, the vector access control device 4 dynamically switches the coupling of the crossbar switches (or multistage switches) [that is, using the mapping information, for example, the crossbar switch is switched to switch the arithmetic unit 3 a and the data memory 2. The flow of vector processing data is efficiently generated.
Here, the crossbar coupling is one of a method of connecting M input ports and N output ports. For example, M horizontal lines and N vertical lines are crossed in a grid pattern, and M It can be considered that a switch is arranged at each of the × N lattice points. The input port reaches the output port via one switch.
[0029]
In addition, multistage coupling connects such circuit switches in multiple stages, and an input port reaches an output port via a plurality of switches.
When executing a certain operation, on the input side of the arithmetic unit group 3, M input ports are connected to the read port of the bank 2a of the data memory 2 (that is, if the number of ways is 5, M = 5), N Are connected to the input ports of the respective arithmetic units 3a.
[0030]
Here, when the calculation of V1 + V2 → V3 is executed (see FIG. 4), the start points of V1 and V2 are respectively way-1 and way-4 as shown in FIG. And way-1 / way-4. Since the next element of V1 / V2 is in way-2 and way-0, the next connection is way-2 / way-0.
[0031]
Similarly, the third element is read by connection with way-3 / way-1, and the fourth element is read by way-4 / way-2. Although not shown in FIG. 5, the fifth is read by way-0 / way-3, and then the sixth element returns to the connection with way-1 / way-4.
As described above, since the arrangement of the vector register areas is regular, the connection between the arithmetic unit 3a and the read port and the write port of the data memory 2 can be controlled by regularly switching the switches. .
[0032]
The vector access control device 4 has a scalar operand / mask register 6 for storing constants and other operands necessary for vector processing.
Further, the external access control device 7 controls access to the main storage device 9, and the interface unit 8 sends and receives commands and data to and from the scalar processing device 10.
[0033]
With the above-described configuration, the cache storage device 1A according to the present invention performs operations as described below. 6 to 8 are flowcharts for explaining the vector calculation process.
First, when valid information is not stored in the mapping table 5 of the cache storage device 1A, the scalar processing device 10 performs a scalar operation. At this time, the cache storage device 1A performs the same operation as that of a normal cache.
[0034]
On the other hand, when performing vector processing, the mapping table 5 is set by a processor (not shown) of the scalar processing device 10.
Here, the mapping table 5 is set in such a manner that the processor of the scalar processing device 10 writes the mapping information about the operand vector register in the mapping table 5 of the cache storage device 1A in accordance with the number of vector registers required for the operation. [Step S1 in FIG. 6 (refer to Steps A1 to A8 in FIG. 7 for details)].
[0035]
When a vector operation instruction is issued by the processor of the scalar processing device 10, the vector access control device 4 processes this vector operation instruction in the cache storage device 1A.
Specifically, the vector access control device 4 refers to the set mapping table 5 and distributes and stores vector processing data in the data memory 2 based on the mapping information about the vector register of the operand specified by the instruction. On the other hand, the computing unit 3a of the computing unit group 3 and the vector register area of the data memory 2 are sequentially connected in accordance with the mapping information.
[0036]
Subsequently, in the arithmetic unit group 3, an operation is actually performed with reference to the vector processing data stored in the vector register, and the operation result is written back to the bank 2a (step S2 in FIG. 6).
Here, as an example of a typical vector operation, a case of performing a DAXPY operation (double-precision AX + Y operation) as shown in FIGS. 3 and 4 will be described. As shown in FIG. 5, four virtual vectors are used. Registers VR0 'to VR3' are used.
[0037]
Here, each vector register is arranged so that each element increases by one in both the way direction and the line direction. That is, the interleave factor is [1-1].
As shown in FIG. 5, the vector register VR0 ′ is composed of elements VR0-0, VR0-1,..., VR0-3, and the vector register VR1 ′ is composed of elements VR1-0, VR1-1,. The vector register VR2 'is composed of elements VR2-0, VR2-1, ..., VR2-3, and the vector register VR3' is composed of elements VR3-0, VR3-1, ..., VR3-3.
[0038]
In the first load instruction (LV), vector processing data to be stored in the vector register VR0 ′ is read from the main storage device 9. Here, when valid data is already cached in the area of the vector register VR0 ′, the data is invalidated or written back to the main storage device 9 as necessary at this point. Alternatively, when the mapping information for the vector register is set, the vector register area is scanned, and when it is detected that valid data has already been cached in the area, the data is invalidated or main memory is stored. Write back to the device 9 may be performed.
[0039]
Similarly, after executing the multiplication instruction (MULTSV), the load instruction (LV), the addition instruction (ADDV), and the store instruction (SV), the vector processing ends.
If it is not necessary to continue the vector processing, the mapping information in the mapping table 5 is invalidated when the processing is completed, and the area allocated as the vector register is released [Step S3 in FIG. 6 (Details). (See Steps B1 to B4 in FIG. 8)].
[0040]
The released area is used again as a cache for storing scalar processing data.
As described above, according to the cache storage device 1A of the present invention, the area used as the vector register is distributed and allocated to the data memory 2, and control is performed so that vector processing data is stored in the area of the vector register. Therefore, it is possible to reduce the amount of hardware without reducing the storage rate of valid data in the cache storage device 1A. As a result, the scalar processing device 10 and the arithmetic unit group 3 can be integrated on one chip. it can.
[0041]
In addition, since the crossover switch (or multistage switch) coupling is dynamically switched to efficiently generate the vector processing data flow, the bank 2a of the data memory 2 does not need to be multiported and integrated. Can be made easier.
Furthermore, since the vector register area can be dynamically allocated in the data memory 2, it is possible to perform parallel processing and chaining of the arithmetic unit group 3 and (2) described in the prior art. Compared with the method, when performing the scalar processing, the data arrangement can be adjusted so that the hit rate of the cache at the specific address does not decrease.
[0042]
Further, compared with the method (1) described in the prior art, it is not necessary to provide a dedicated interface, so that the amount of hardware can be reduced.
Further, with respect to the cache coherence control provided in the scalar processing apparatus 10, according to the method of the present invention, it is not necessary to provide an additional path for bypassing data, and integration can be facilitated.
[0043]
It should be noted that the flexibility of the allocation of the vector register area in the data memory 2 is linked to the following characteristics by analysis by the compiler.
That is, by making the interleave value relatively prime with the number of ways and the number of lines, it is possible to cope with data having a long vector length. In this case, however, the possibility of structural hazards increases, and the number of pipelines that can be operated simultaneously decreases.
[0044]
Further, it is possible to cope with a recursion operation by shifting the starting point of each vector register area.
Furthermore, if the tag bit is expanded, pipeline flow control can be realized.
(B) Description of one embodiment
Embodiments of the present invention will be described below with reference to the drawings.
[0045]
FIG. 9 is a block diagram showing the configuration of the cache storage device according to the embodiment of the present invention.
As shown in FIG. 9, the cache storage device 11 includes, for example, an integer unit (scalar processing unit) 20 for executing a scalar processing instruction, an arithmetic unit group (vector processing unit; Vector Pipeline) 13, and It is interposed between the main storage device 23 for storing various data.
[0046]
FIG. 9 shows an example in which the cache storage device 11, the arithmetic unit group 13, and the integer unit 20 are integrated on one chip 22.
The integer unit 20 is provided with integer registers (Integer Registers) 21.
As shown in FIG. 9, the cache storage device 11 includes a data cache (storage unit; 8-way Set-associative Data Cache) 12, a vector access control device (control unit; VCC) 14, an instruction cache (Instruction Cache). ) 18 and Address Translation / Load Store Unit 19.
[0047]
Here, the computing unit group 13 is composed of a plurality of computing units 13a, similar to the computing unit group 3 (see FIG. 1) described above, and using these computing units 13a, for example, vector processing instructions for SPARC [vector computation; Specifically, FP (Floating Point) addition instruction (FP Add), FP multiplication instruction (FP Mul.), FP division instruction (FP Div.), Graphics instruction (Graphics), mask instruction (Mask), etc.) Thus, vector processing is performed.
[0048]
The instruction cache 18 is for copying and storing instruction data stored in the main storage device 23. The data cache 12 is similar to the data memory 2 (see FIG. 1) described above, and includes a plurality of banks 12a. The data stored in the main storage device 23 is copied and stored.
The data cache 12 has a function of storing data (scalar processing data) required when the integer unit 20 performs processing, and data (vector processing) required when the computing unit group 13 performs processing. Data), and has a function as a virtual vector register.
[0049]
This vector register is also allocated on the management unit (line) of the bank 12a of the data cache 12 by an interleaving method using ways and lines, as in the data memory 2 described above.
Note that, for the instruction cache 18 and the data cache 12, specifications that can be realized with the current technology are shown in FIG.
[0050]
Further, the vector access control device 14 controls the arithmetic unit group 13 and the data cache 12 when performing vector processing, and includes a mapping table 15, a mask register 16, and a scalar operand storage unit 17. ing.
Here, the mapping table 15 holds mapping information (allocation information) for designating the position of an area functioning as a vector register (hereinafter referred to as a vector register area) in the bank 12a of the data cache 12. . Specific examples of the mapping table 15 and the vector register will be described later.
[0051]
That is, the vector access control device 14 refers to the mapping table 15 and allocates the area used as the vector register to the data cache 12 based on the mapping information. Control is performed so that the vector processing data is stored in the vector register area.
[0052]
In the data cache 12, an area other than the area assigned as the vector register is assigned as an area for storing scalar processing data.
The vector access control device 14 treats the vector register allocation status as a visible register from a SPARC instruction set to be described later. That is, as will be described later, information to be stored in the mapping table 15 is defined as a coprocessor register (% c0 to% c29 shown in FIG. 12), and is directly handled on the instruction set as a visible register. ing.
[0053]
The mask register 16 is for designating a part of the elements in the vector data to be subjected to the mask operation (% c30 and% c31 shown in FIG. 12 are used as mask registers). The scalar operand storage unit 17 stores a constant (scalar operand; C1 in the example shown in FIG. 3) necessary for vector processing.
Further, the address translation / load / store unit 19 receives requests from the vector access control device 14 and the instruction cache 18 and controls access to the main storage device 23.
[0054]
Here, specific examples of the mapping table 15 and the vector register described above will be described.
(1) First specific example
It is assumed that there is a data cache 12 in which the number of ways is 8 and the number of sets (the number of lines per way) is 8, and each line can store 8 operation elements (for example, double-precision floating point data).
[0055]
The data on the data cache 12 is specified by three addresses: a way number (x), a line number (y), and an in-line position (z), which will be represented as Ax-yz below.
Here, when the virtual vector register is VRn and each vector register VRn has 64 operation elements VRn-m, each operation element VRn-m is stored in the memory for 8 lines.
[0056]
As an example, a case where three virtual vector registers are defined will be described. As shown in FIG. 13, a mapping table 15 for creating physical address information from each vector register has valid information [valid (Yes) / invalid (No)], start point information (start point), increment information (increment, increment interval), length (number of elements), and type information.
[0057]
Here, the triplet values of the start point, increment, and increment interval correspond to the three-dimensional addresses of way, line, and offset, respectively, and the increment interval is set to each address for every number of elements. Indicates whether to add an increment.
Information about the data type as shown as type information may not be placed in the mapping table 15 as shown in FIG.
[0058]
Then, assuming that the start point (Sx, Sy, Sz), the increment (Ix, Iy, Iz), and the increment interval (Dx, Dy, Dz), the nth element of the vector register corresponds to the following address.
A [Sx ＋ Ix ^* (n / Dx), Sy + Iy ^* (n / Dy), Sz + Iz ^* (n / Dz)] (1)
However, the division in the expression (1) is performed by rounding down the fractional part by integer division, and the calculation result is obtained by taking the remainder in the number of ways, the number of lines, and the number of elements in the line, respectively.
[0059]
At this time, each operation element of the vector register VR0 in the mapping table 15 shown in FIG. 13 is as shown in FIG. Further, each operation element of the vector register VR1 and each operation element of the vector register VR2 are as shown in FIGS. 14 (b) and 14 (c), respectively.
Accordingly, the areas of the vector registers VR0, VR1, VR2 on the data cache 12 are as shown in FIG. Taking the vector register VR0 as an example, the correspondence between each area (VR0a-VR0h) and the elements stored therein is as shown in FIG.
(2) Second specific example
In the first specific example described above, the case where the calculation elements adjacent to each other in the vector register are distributed, that is, the case where the calculation elements VR0-0 and VR0-1 are in the areas VR0a and VR0b, respectively, has been described. They can also be placed in the same area.
[0060]
In this case, the mapping table 15 is as shown in FIG.
In this example, the area of the vector register VR0 on the data cache 12 is the same as in the case of the first specific example described above, but the correspondence between each area and the arithmetic elements stored therein is different (FIG. 18). , See FIG.
(3) Third specific example
In the first and second specific examples described above, the mapping table 15 stores information for sequentially calculating the address information on the data cache 12 of each calculation element. You may store (refer FIG. 20).
[0061]
In this case, the size of the mapping table 15 can be reduced by calculating the offset in the area from the operation element number in the virtual vector register.
For example, if the nth arithmetic element is the (n mod 8) th of the area (n / 8), or conversely, the n th arithmetic element is the n / 8 th of the area (n mod 8), the first specific example The mapping table 15 can be expressed as shown in FIG.
[0062]
Although this method increases the size of the mapping table 15 in accordance with the length of the vector data, there is an advantage that more flexible mapping is possible.
With the above-described configuration, the cache storage device 11 according to the embodiment of the present invention performs the same operation as the above-described operation in the cache storage device 1A (see FIGS. 6 to 8).
[0063]
In particular, in the following, focusing on coprocessor instructions and FP instructions in the SPARC instruction set, it will be described that the SPARC instruction set and virtual vector processing can be naturally integrated.
(1) Instruction flow
The integer unit 20 fetches from the instruction cache 18 all instructions (All Instructions) including FP instructions (FP Instructions) and vector processing instructions (VP Instructions).
[0064]
Here, the vector processing instruction is realized by using a coprocessor instruction in the SPARC instruction set.
In addition, an integer operation instruction that can be independently processed by the integer unit 20 is processed by the integer unit 20. The FP instruction and the vector processing instruction are sent from the integer unit 20 to the vector access controller 14 by using the same path (memory store path; indicated by MSP in FIG. 9) as the store to the data cache 12. At this time, if necessary, the effective address is calculated at the execution stage in the integer unit 20.
[0065]
At this time, it is only necessary to add a few signal lines for distinguishing instructions and data to the memory store path between the integer unit 20 and the vector access controller 14.
Then, the instruction sent to the vector access control device 14 is internally decoded and then processed according to its type.
(2) Scalar operand and vector operand
The FP register used for storing operands of the FP instruction is also used for storing scalar operands in some VP instructions.
[0066]
Here, the FP instruction is processed using an arithmetic pipeline for vector processing.
The operand of the VP instruction directly points to the entry of the mapping table 15 or the mask register 16.
The same applies to the operand of the operation instruction, but actually, the calculation is performed on the virtual vector register described in the entry.
[0067]
In the SPARC instruction set, the register size used as the operand of the load / store instruction for the coprocessor is assumed to be 32 bits or 64 bits. However, the method in which the entry of the mapping table 15 is the direct operand is contrary to this assumption. do not do.
In other words, the coprocessor instruction format of SPARC (Version 8) is as shown in FIG. 11, and a general coprocessor register basically handles a single word and in some cases handles a double word. However, as described above, the information to be stored in the mapping table 15 can be expressed by 32 bits on this simple architecture.
[0068]
Therefore, the information to be stored in the mapping table 15 is defined as a coprocessor register as shown in FIG. 12, and can be directly handled on the instruction set as a visible register.
This is because the mapping table 15 indicating the allocation status of the vector register corresponds to the coprocessor register [% c0 to% c29 shown in FIG. 12 corresponds to the coprocessor register. Here, each% cn (n = 0 to 31) is a 32-bit register. ] Indicates that it is directly visible from the software on the instruction set.
[0069]
That is, each of the coprocessor registers (% c0 to% c29 shown in FIG. 12) stores the mapping information of VVR0 to VVR29. For example, when defining VVR0, the mapping information of VVR0 can be written to% c0. That's fine.
That is, the mapping table 15 is set by writing a value to the coprocessor register, and reading the value from the coprocessor register to extract the current mapping information.
[0070]
The example shown in FIG. 12 is an example, but after that, some instructions for manipulating the contents of the virtual vector register in the CPop instruction (coprocessor instruction) [ordinary vector operation instructions (vector load instructions) , Vector store instructions, vector addition / multiplication / subtraction / division instructions, graphics instructions, etc.)] can be sufficiently included in the SPARC instruction set.
[0071]
That is, the SPARC (Version 8) CPop instruction (coprocessor instruction) has a field for storing information indicating the type of operation. If a normal vector operation instruction is defined using this field, It can fit in the SPARC instruction set.
The cache storage device 11 according to the embodiment of the present invention can obtain the same advantages as those of the cache storage device 1A described above.
[0072]
【The invention's effect】
As described above in detail, according to the cache storage device of the present invention, the area used as the vector register is distributed and allocated to the storage unit, and the vector processing data is stored in the area of the distributed and allocated vector register. Therefore, it is possible to reduce the amount of hardware without lowering the storage rate of valid data in the cache storage device. As a result, the scalar processing device and the vector processing device are integrated on one chip. There is an advantage that can be 3-6 ).
[0073]
In addition, since the vector register area can be dynamically allocated in the storage unit, parallel processing and chaining can be performed in the vector processing device, and a cache of a specific address can be used when performing scalar processing. There is an advantage that the data arrangement can be adjusted so that the hit rate does not decrease. 2 ).
[Brief description of the drawings]
FIG. 1 is a block diagram showing an aspect of a configuration of a cache storage device of the present invention.
FIG. 2 is a diagram for explaining a virtual vector register in the present invention.
FIG. 3 is a diagram for explaining an example of vector calculation;
FIG. 4 is a diagram for explaining an example of vector calculation;
FIG. 5 is a diagram for explaining a virtual vector register in the present invention.
FIG. 6 is a flowchart for illustrating a procedure of vector operation processing in the cache storage device of the present invention.
FIG. 7 is a flowchart for showing a procedure of vector operation processing in the cache storage device of the present invention;
FIG. 8 is a flowchart for illustrating a procedure of vector operation processing in the cache storage device of the present invention.
FIG. 9 is a block diagram showing a configuration of a cache storage device according to an embodiment of the present invention.
FIG. 10 is a diagram for explaining an instruction cache and a data cache;
FIG. 11 is a diagram illustrating a SPARC coprocessor instruction format;
FIG. 12 is a diagram for explaining a coprocessor register;
FIG. 13 is a diagram for describing a first specific example of a mapping table and a vector register;
FIGS. 14A to 14C are diagrams for explaining a first specific example of a mapping table and a vector register. FIG.
FIG. 15 is a diagram for describing a first specific example of a mapping table and a vector register;
FIG. 16 is a diagram for describing a first specific example of a mapping table and a vector register;
FIG. 17 is a diagram for describing a second specific example of a mapping table and a vector register;
FIG. 18 is a diagram for describing a second specific example of a mapping table and a vector register;
FIG. 19 is a diagram for describing a second specific example of a mapping table and a vector register;
FIG. 20 is a diagram for explaining a third specific example of the mapping table and the vector register;
[Explanation of symbols]
1 chip
1A Cache storage device
2 Data memory (storage unit)
2a bank
3 arithmetic unit group (vector processing unit)
3a arithmetic unit
4. Vector access control device (control unit)
5 Mapping table
6 Scalar operand / mask register
7 External access control device
8 Interface section
9 Main memory
10 SCARA processing equipment
11 Cache storage device
12 Data cache (storage unit)
12a bank
13 arithmetic unit group (vector processing device)
13a arithmetic unit
14 Vector access control device (control unit)
15 Mapping table
16 Mask register
17 Scalar operand storage
18 Instruction cache
19 Address conversion / load / store section
20 integer unit (scalar processor)
21 Integer register
22 chips
23 Main memory

Claims (6)

Between a scalar processing device that processes one or a pair of data with one instruction and a vector processing device that performs the same operation on a data set consisting of multiple elements with one instruction, and a main storage device that stores various data A cache storage device having a storage unit for interpolating and storing the data stored in the main storage device;
The storage unit stores scalar processing data for the scalar processing device and has a function as a vector register for storing vector processing data for the vector processing device,
Start point information indicating the start point of the area of the vector register, an interleave factor indicating an arrangement interval of elements forming the area of the vector register, length information indicating the length of the vector register, and the type of the vector register further comprising a table for holding the control bit indicating information or valid information as assignment information,
Based on the allocation information with reference to the table, the crossbar switches are regularly switched sequentially, and the allocation of the areas used as the vector registers is regularly distributed and allocated to the storage unit, and distributed to the storage unit A cache storage device comprising a control unit that controls to store the vector processing data in the area of the vector register allocated in this manner.  The cache storage device according to claim 1, wherein an area of the vector register is dynamically allocated in the storage unit.  3. The cache storage device according to claim 1, wherein an area other than the area assigned as the vector register in the storage unit is assigned as an area for storing the scalar processing data.  4. The cache storage device according to claim 1, wherein vector processing data is transmitted and received between the vector register and the vector processing device in the storage unit. 5.  5. When the processing by the vector processing device using the vector register is completed, the control unit releases the area allocated as the vector register in the storage unit. The cache storage device according to item 1.  When the processing by the vector processing device using the vector register is finished, the control unit invalidates the allocation information held in the table, thereby reducing the area allocated as the vector register in the storage unit. The cache storage device according to claim 1, wherein the cache storage device is released.

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