JP4061413B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention, N ^- mainly active layer surface P ⁺ N impurity density of the low surface-type semiconductor device of high breakdown voltage, such as ^- N ⁺ planar diode, a method of manufacturing a semiconductor device such as a transistor.
[0002]
[Prior art]
Conventionally, as a semiconductor device of this type, for example, when manufacturing a P ⁺ N ^- N ⁺ planar diode for high breakdown voltage, each manufacturing process as shown in the side sectional view of the main part in FIGS. Follow the procedure. 2A relates to the epitaxial growth process, FIG. 2B relates to the mask formation process, FIG. 2C relates to the polysilicon film formation process, and FIG. 2D relates to the anode formation and wiring pattern. relates to the formation process, FIG. (e) is related to the electrode forming step, FIG. (f) relates to path Tsu Shibeishon _SiO 2 -CVD film forming step.
[0003]
Here, first, as an epitaxial growth step shown in FIG. 2A, a low concentration N ⁻ with an impurity concentration of 1 × 10 ¹³ cm ⁻³ is formed on an N ⁺ type silicon substrate 1 with an impurity concentration of 1 × 10 ¹⁸ cm ^−3. After epitaxially growing the type epitaxial layer 2 to a thickness of about 50 μm, a SiO ₂ film 3 is formed to a thickness of about 3000 Å by thermal oxidation on the back surface of the N ⁺ type silicon substrate 1 and the entire surface of the N ⁻ type epitaxial layer 2 surface. . The SiO ₂ film 3 formed on the back surface of the N ⁺ type silicon substrate 1 is schematically shown.
[0004]
Next, as a mask formation step shown in FIG. 2B, an anode pattern is formed on the SiO ₂ film 3 on the surface of the N ⁻ -type epitaxial layer 2 by a general photolithography method, and then a hydrofluoric acid-based etching solution is used. By forming an opening in the SiO ₂ film 3, the SiO ₂ film 31 exposing the local portion of the N ⁻ type epitaxial layer 2 is formed.
[0005]
Further, as the polysilicon film forming step shown in FIG. 2C, P ⁺ doped with B ₂ H ₆ (diborane) as a P-type gas on the exposed portion of the N ⁻ -type epitaxial layer 2 and the SiO ₂ film 31 is used. A type polysilicon film 4 is grown.
[0006]
Subsequently, as an anode formation and wiring pattern formation step shown in FIG. 2D, the N ⁻ type epitaxial layer 2 is subjected to a high temperature heat treatment at a temperature of about 1100 ° C. with the P ⁺ type polysilicon film 4 formed. in after forming the anode layer 5 by performing a P-type thermal diffusion, the P ⁺ -type wires of the polysilicon film 4 is patterned by photolithography, the patterned P ⁺ -type by etching the P ⁺ -type polysilicon film 4 Polysilicon 41 is formed.
[0007]
In addition, as an electrode forming step shown in FIG. 2E, an aluminum film is formed on the entire front and back surfaces by vapor deposition or sputtering, and the anode electrode 6 is formed by patterning the aluminum film on the surface by photolithography and etching. As for the back surface, a cathode electrode 7 made of an aluminum film is formed.
[0008]
Further, as a passivation SiO ₂ -CVD film forming step shown in FIG. 2 (f), the SiO ₂ film was formed on the entire surface by the CVD method, and then the photolithography and the SiO ₂ -CVD film were etched and patterned. A SiO ₂ -CVD film 8 is formed.
[0009]
Here, the manufacturing process in the case of manufacturing a P ⁺ N ^- N ⁺ planar type diode for high withstand voltage has been described, but the N ⁺ type silicon substrate 1 here is used as a drain layer and an anode region (anode layer 5). , Anode electrode 6) and cathode region (cathode electrode 7) are replaced with a gate region and a drain region, a P ⁺ N ^- N ⁺ planar transistor for high breakdown voltage can be manufactured in the same procedure.
[0010]
[Problems to be solved by the invention]
In the case of the manufacturing method of the P ⁺ N ^- N ⁺ planar diode for high breakdown voltage described above, the SiO ₂ film itself is contaminated during the manufacturing process, or the SiO ₂ film is contaminated by a subsequent process. there the surface charge density interface determined by the impurity concentration for increasing the impurity density of the receiving surface of the epitaxial layer the influence of impurities (surface charge density) is apparent, the set epitaxial layer between the epitaxial layer and the SiO ₂ film there is greater, hindered device operation to greatly extend the depletion layer is necessary for obtaining a high breakdown voltage, high breakdown voltage as a result there is a problem that not be obtained. In other words, if there is such contamination, the breakdown voltage determined by the impurity concentration cannot be obtained even if the theoretical value of the PN junction is calculated in consideration of the device structure necessary to obtain a high breakdown voltage, and a high breakdown voltage can be obtained. It was difficult.
[0011]
The present invention has been made to solve such problems, and its technical problem is a method for manufacturing a semiconductor device capable of stably ensuring high withstand voltage characteristics even in the presence of impurity contamination during the manufacturing process. Is to provide.
[0012]
[Means for Solving the Problems]
According to the present invention, an insulating film forming step of low concentration of the epitaxial layer in a high concentration silicon substrate surface in the one conductivity type to form the epitaxial layer surface insulating film provided, and patterning the insulating film In a diode manufacturing method including an anode region forming step for forming an anode region of reverse conductivity type and a cathode region forming step for forming a cathode region on the back surface of the silicon substrate, a passive bay is formed after the anode region forming step. A diode manufacturing method including an ionized gas irradiation step of irradiating at least the surface of the insulating film with an ionized gas ionized by plasma before the formation film forming step is obtained.
[0013]
In this diode manufacturing method, in the ionized gas irradiation process, positive ions or negative ions are generated depending on the plasma state, and the surface charge density of the silicon substrate is controlled to be low and high withstand voltage. Further, the ionizing gas irradiation step is preferably an argon ion irradiation step in which argon is used as the ionizing gas and irradiated with argon ions.
[0014]
On the other hand, according to the present invention, low concentration of the epitaxial layer is provided on the high concentration silicon substrate surface in the one conductivity type, an insulating film forming step of forming an insulating film on the epitaxial layer surface, patterning the insulating film In the method of manufacturing a transistor, the method includes: a source and gate region forming step for forming the one conductivity type source region and a reverse conductivity type gate region; and a drain region forming step for forming a drain region on the back surface of the silicon substrate. A transistor manufacturing method including an ionized gas irradiation step of irradiating at least the surface of the insulating film with an ionized gas ionized by plasma after the source region and gate region forming step and before the passivation film forming step is obtained. .
[0015]
In this transistor manufacturing method, in the ionized gas irradiation process, positive ions or negative ions are generated depending on the plasma state, and the surface charge density of the epitaxial layer is controlled to be low and high withstand voltage. Furthermore, the ionized gas irradiation step is preferably an argon ion irradiation step using ionized gas and argon in the case of positive ion generation , for example .
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the method for manufacturing a semiconductor device of the present invention will be described in detail with reference to the drawings.
[0017]
First, the outline of the semiconductor device manufacturing method of the present invention will be briefly described. Method of manufacturing a semiconductor device, together with the anode region of the opposite conductivity type is formed on the low concentration of the epitaxial layer surface of 10 ¹³ extent of one conductivity type as the semiconductor device, the cathode region is formed on the back surface of the silicon substrate and P ⁺ N ^- N ⁺ planar diode or or together with the source region and the opposite conductivity type of the gate region of the one conductivity type on the surface of the one conductivity type 10 ¹³ extent of the low concentration of the epitaxial layer is formed, a silicon For example, the present invention is applied to a P ⁺ N ^- N ⁺ planar transistor in which a drain region is formed on the back surface of a substrate.
[0018]
That is, in the manufacturing method of the diode, an insulating film forming step of forming an insulating film on the surface of the epitaxial layer of low concentration of one conductivity type, an anode region formed to form the anode region of the opposite conductivity type by patterning the insulating film In addition to the existing manufacturing procedure including the step and the cathode region forming step of forming the cathode region on the back surface of the silicon substrate , at least on the surface of the insulating film after the anode region forming step and before the passivation film forming step. An ionized gas irradiation process is performed in which an ionized gas ionized by plasma is irradiated.
[0019]
On the other hand, in the method for producing a transistor, the insulating film forming step of forming an insulating film on the surface of the low concentration of the epitaxial layer of 10 ¹³ extent of one conductivity type, the source of one conductivity type by patterning the insulating film on the surface thereof In addition to the existing manufacturing procedure including a source and gate region forming step for forming a region and a reverse conductivity type gate region, and a drain region forming step for forming a drain region on the back surface of the silicon substrate, a source region and gate region forming step An ionized gas irradiation process is performed to irradiate at least the surface of the insulating film with an ionized gas ionized by plasma after the passivation film forming process.
[0020]
However, in any semiconductor device, in the ionized gas irradiation process, positive ions or negative ions are generated depending on the plasma state, and the surface charge density of the low-concentration epitaxial layer is low and the breakdown voltage is high. To control the surface charge density. Furthermore, the ionized gas irradiation process is preferably an argon ion irradiation process in which, for example, argon is used as the ionized gas and argon ions are irradiated. That is, in one form of the manufacturing method of this semiconductor device, the surface of the semiconductor device manufactured in the existing manufacturing process is irradiated with argon ions, so that the interface between SiO ₂ and the oxide film and the N ⁻ low-concentration epitaxial layer is obtained. The surface charge density is reduced, and high breakdown voltage characteristics can be secured stably even if there is impurity contamination during the manufacturing process.
[0021]
FIG. 1 is a side sectional view of an essential part for explaining a manufacturing process of a P ⁺ N ⁻ N ⁺ diode according to an embodiment of the present invention. FIG. 1 (a) shows an epitaxial growth process. FIG. 4B relates to the mask formation process, FIG. 4C relates to the polysilicon film formation process, FIG. 4D relates to the anode formation and wiring pattern formation process, and FIG. (F) relates to the argon ion irradiation process, and (g) relates to a partially enlarged view of the local region E including the silicon interface in FIG. (F). FIG (h) relates to path Tsu Shibeishon _SiO 2 -CVD film forming step.
[0022]
Here, first as an epitaxial growth process shown in FIG. 1 (a), the impurity concentration impurity concentration of 1 × ¹⁰ 13 ^{cm -3} on the ^{N +} -type silicon substrate 1 of 1 × ¹⁰ 18 ^{cm -3} low concentration N ^- After epitaxially growing the type epitaxial layer 2 to a thickness of about 50 μm, a SiO ₂ film 3 is formed to a thickness of about 3000 Å by thermal oxidation on the back surface of the N ⁺ type silicon substrate 1 and the entire surface of the N ⁻ type epitaxial layer 2 surface. . In this epitaxial growth step, a series of insulating films are formed in which an N ⁻ low-concentration epitaxial layer is provided on the surface of an N ⁺ -type silicon substrate 1 of one conductivity type, and an SiO ₂ film 3 is formed as an insulating film on the surface. It can be regarded as a process. Also here, the SiO ₂ film 3 formed on the back surface of the N ⁺ -type silicon substrate 1 is schematically shown.
[0023]
Next, as a mask formation step shown in FIG. 1B, an anode pattern is formed on the SiO ₂ film 3 on the surface of the N ⁻ -type epitaxial layer 2 by a general photolithography method, and then a hydrofluoric acid-based etching solution is used. By forming an opening in the SiO ₂ film 3, the SiO ₂ film 31 exposing the local portion of the N ⁻ type epitaxial layer 2 is formed.
[0024]
Furthermore, as a polysilicon film forming step shown in FIG. 1C, P ⁺ doped with B ₂ H ₆ (diborane) as a P-type gas on the exposed portion of the N ⁻ -type epitaxial layer 2 and the SiO ₂ film 31. A type polysilicon film 4 is grown.
[0025]
Subsequently, as the anode formation and wiring pattern formation step shown in FIG. 1D, the N ⁻ type epitaxial layer 2 is subjected to a high temperature heat treatment at a temperature of about 1100 ° C. with the P ⁺ type polysilicon film 4 formed. in after forming the anode layer 5 by performing a P-type thermal diffusion, the P ⁺ -type wires of the polysilicon film 4 is patterned using photolithography, patterned P ⁺ -type by etching the P ⁺ -type polysilicon film 4 Polysilicon 41 is formed.
[0026]
The steps from the mask formation process up to this point to the anode formation and wiring pattern formation processes are performed by patterning the SiO ₂ film 3 on the surface of the N ⁺ type silicon substrate 1 which is one conductivity type, and the P type which is the opposite conductivity type. It can be regarded as an anode region forming step for forming the anode region.
[0027]
Further, as the electrode forming step shown in FIG. 1E, an aluminum film is formed on the entire front and back surfaces by vapor deposition or sputtering, and the anode electrode 6 is formed by patterning the aluminum film on the surface by photolithography and etching. As for the back surface, a cathode electrode 7 made of an aluminum film is formed. This electrode forming step can be regarded as a cathode region forming step for forming a cathode region on the back surface of the N ⁺ type silicon substrate 1. The anode region forming step described above can also be considered to include up step leading to the electrode forming step.
[0028]
Incidentally, the above process is the same procedure as the conventional case demonstrated in FIG. 2 (a)-(e).
[0029]
Furthermore, as an argon ion irradiation step shown in FIG. 1 (f), Ar gas, which is an inert gas having a relatively large atomic radius and mass, is introduced into the plasma generator, and plasma is generated with the substrate holder lower electrode as a negative potential. It is generated, and Ar ⁺ ions 9 irradiates toward the substrate side by ionised a r atom. As a result, the surfaces of the anode region (anode electrode 6) and the insulating film (SiO ₂ film 31) are irradiated with Ar ⁺ ions 9 ionized by plasma.
[0030]
FIG. 1G shows a partially enlarged local region E including the silicon interface between the N ⁻ type epitaxial layer 2 and the SiO ₂ film 31 in FIG. Such level generation at the interface of the epitaxial layer may be caused by SiO ₂ defects generated due to poor bonding between the epitaxial layer and oxygen at the time of forming the SiO ₂ film 31 or by contamination in the manufacturing process. The surface charge density Qss rises due to the generation of new levels at the epitaxial layer interface. As the surface charge density Qss rises, donor impurities are apparently generated, and in the N ⁻ type epitaxial layer 2, a new epitaxial layer 21 to which this is added is generated.
[0031]
N ^- type epitaxial layer 2 itself is towards the donor impurity is lower layers of impurity density over than the acceptor impurity, in the epitaxial layer surface 21 plus donor impurity due to surface charge density which is newly generated, N ^- The apparent impurity density is much higher than that of the type epitaxial layer 2. Since the impurity density increases at the interface of this epitaxial layer , the depletion layer is difficult to spread in this state, and a high breakdown voltage cannot be obtained.
[0032]
Therefore, when Ar ⁺ ions 9 having a positive charge are irradiated, Ar ⁺ ions 9 collide with the surface of the SiO ₂ film 31 to form a charge 32 of the SiO ₂ ⁺ film having a positive charge. Here, charge exchange is performed in such a manner that the kinetic energy of the Ar ⁺ ions 9 is transferred to the Ar atoms 91 after the collision, and the SiO ₂ film 31 is transferred to the charges 32 of the SiO ₂ ⁺ film after the collision. SiO ₂ ⁺ film of the charge 32 positively charged by this charge exchange has reach the interface between the epitaxial layer interface 2 1 diffuses into the epitaxial layer interface direction. When _SiO ^{2 +} film of the charge 32 to the epitaxial layer interface 21 arrive as a result, both of the charges between the _SiO ^{2 +} film of the charge 32 and the epitaxial layer interface 21 which donor impurity is visible apparently increased positively charged Are combined, and the charge 32 side of the SiO ₂ ⁺ film is positive and the epitaxial layer interface 21 side is negative, so that the charge is apparently reduced.
[0033]
By such a reaction, the surface charge density of SiO ₂ and the oxide film can be reduced to reduce the apparently generated donor impurities at the epitaxial layer interface 21, and the N ⁻ type epitaxial layer 2 can be maintained in a low impurity density state. Can be controlled. As here generation conditions of example Ar ⁺ ions 9, because of the use of relatively atomic radius and a large mass Ar gas, Ar atoms 91 do not enter the interior of the SiO ₂ film 31, SiO ₂ film 31 adhered to in the lower Damage to the surface of the N ⁻ type epitaxial layer 2 can be controlled.
[0034]
Incidentally, if such a technique is applied, even if the target is other than the N ⁺ type silicon substrate 1 described here, the surface charge density Qss of the silicon substrate is reduced by generating positive ions or negative ions depending on the plasma state. In addition, the surface charge density Qss can be controlled to achieve a high breakdown voltage. Specifically, depending on whether the silicon substrate is an N-type semiconductor or a P-type semiconductor, if you want to generate positive ions, use an inert gas such as He, Ne, Ar, etc. to generate negative ions In order to achieve this, plasma is generated by introducing halogen groups such as F, Cl, Br, and I, and atoms and molecules such as O and O ₂ , and the ion irradiation energy and dose can be appropriately given.
[0035]
Finally, path Tsu Shibeishon _SiO 2 -CVD film forming step shown in FIG. 1 (h), to form a SiO ₂ film on the entire surface by etching of photolithography and _SiO 2 -CVD film from by CVD, A patterned SiO ₂ -CVD film 8 is formed. As mentioned above, the passivation SiO ₂ -The CVD film forming step is preferably after the argon ion irradiation step. That is, the argon ion irradiation step is performed after the anode region forming step and the passivation SiO _2. -It is desirable to implement in the process between CVD film formation processes.
[0036]
Here, the manufacturing process in the case of manufacturing a P ⁺ N ⁻ N ⁺ planar type diode for high breakdown voltage has been described here, but the N ⁺ type silicon substrate 1 here is used as a drain layer and an anode region (anode layer 5). , Anode electrode 6) and cathode region (cathode electrode 7) are replaced with a gate region and a drain region, a P ⁺ N ^- N ⁺ planar transistor for high breakdown voltage can be manufactured in the same procedure.
[0037]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, a depletion layer spreads as compared with a P ⁺ N ^- N ⁺ planar type diode or transistor as a semiconductor device in which a low-concentration epitaxial layer becomes an active layer. Since the oxide film is formed on the surface of the device region, and the ionized gas irradiation process is performed to irradiate the ionized gas ionized by plasma to the epitaxial layer interface through the oxide film, the surface charge density at the epitaxial layer interface is reduced. An effect of helping the spread of a depletion layer necessary for obtaining a high breakdown voltage after being reduced is obtained, and an increase in contamination in the manufacturing process is prevented and a high breakdown voltage characteristic is stably secured. In particular, since positive ions or negative ions are generated according to the plasma state in the ionized gas irradiation process, the surface charge density is controlled so that the charge density at the interface of the epitaxial layer is low and the breakdown voltage is high. The surface charge density at the interface between the SiO ₂ and oxide film and the N ^- low-concentration epitaxial layer can be reduced while the surface charge density is freely controlled according to the conditions and the type of introduced gas. When manufacturing various semiconductor devices using an epitaxial layer having a concentration as an active layer, a high breakdown voltage can be stably obtained even if there is impurity contamination during the manufacturing process.
[Brief description of the drawings]
FIG. 1 is a side cross-sectional view of a main part shown to explain a manufacturing process of a P ⁺ N ⁻ N ⁺ diode according to an embodiment of the present invention , ( a) relates to an epitaxial growth process , ( b) (C) relates to a polysilicon film formation process , ( d) relates to an anode formation and wiring pattern formation process , ( e) relates to an electrode formation process , and ( f) relates to argon. ( G) relates to a partially enlarged view of the local region E including the silicon interface in ( f) . (H) relates to path Tsu Shibeishon _SiO 2 -CVD film forming step.
FIGS. 2A and 2B are side cross-sectional views of the main part shown to explain a manufacturing process of a conventional P ⁺ N ⁻ N ⁺ planar type diode, wherein FIG. 2A relates to an epitaxial growth process, and FIG. relates, (c) is related to the polysilicon film forming step, (d) is related to the anode formation and wiring pattern forming step, (e) is related to the electrode formation step, (f) the path Tsu Shibeishon _SiO 2 -CVD The present invention relates to a film forming process.
[Explanation of symbols]
1 N ⁺ type silicon substrate 2 N ⁻ type epitaxial layer 3, 31 SiO ₂ film 4, 41 P ⁺ type polysilicon film 5 Anode layer 6 Anode electrode 7 Cathode electrode 8 SiO ₂ -CVD film 9 Ar ⁺ ion 21 Epitaxial layer interface 32 SiO ₂ ⁺ Charge of membrane 91 Ar atom

Claims (6)

An insulating film forming step of the high concentration low concentration of the epitaxial layer on the surface of the silicon substrate to form an insulating film on the epitaxial layer surface provided with one conductivity type, an anode region of the opposite conductivity type by patterning the insulating film In a diode manufacturing method including an anode region forming step for forming a cathode region and a cathode region forming step for forming a cathode region on the back surface of the silicon substrate, after the anode region forming step and before the passivation film forming step A method for manufacturing a diode, comprising: an ionizing gas irradiation step of irradiating at least a surface of the insulating film with an ionized gas ionized by plasma. 2. The method of manufacturing a diode according to claim 1, wherein in the ionized gas irradiation step, positive ions or negative ions are generated according to the state of the plasma so that the surface charge density of the epitaxial layer is low and the diode has a high breakdown voltage. A method for producing a diode, characterized in that the step of controlling the irradiation with ionized gas is performed .  3. The diode manufacturing method according to claim 1, wherein the ionized gas irradiation step is an argon ion irradiation step of irradiating argon ions as the ionized gas. An insulating film forming step of the high concentration low concentration of the epitaxial layer on the surface of the silicon substrate to form an insulating film on the epitaxial layer surface provided with one conductivity type, the source of the one conductivity type by patterning the insulating film A source and gate region forming step for forming a region and a gate region of opposite conductivity type; and a drain region forming step for forming a drain region on the back surface of the silicon substrate. A transistor manufacturing method comprising: an ionizing gas irradiation step of irradiating at least a surface of the insulating film with an ionized gas ionized by plasma after the forming step and before the passivation film forming step . 5. The method of manufacturing a transistor according to claim 4, wherein in the ionized gas irradiation step, positive ions or negative ions are generated according to the plasma state so that the surface charge density of the epitaxial layer is low and the breakdown voltage is high. method for producing a transistor, which is a step of controlling the surface charge density.  6. The method of manufacturing a transistor according to claim 4, wherein the ionized gas irradiation step is an argon ion irradiation step of irradiating argon ions as the ionized gas.

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