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JP4066911B2 - Semiconductor device manufacturing method and semiconductor element mounting structure forming method - Google Patents
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JP4066911B2 - Semiconductor device manufacturing method and semiconductor element mounting structure forming method - Google Patents

Semiconductor device manufacturing method and semiconductor element mounting structure forming method Download PDF

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JP4066911B2
JP4066911B2 JP2003278077A JP2003278077A JP4066911B2 JP 4066911 B2 JP4066911 B2 JP 4066911B2 JP 2003278077 A JP2003278077 A JP 2003278077A JP 2003278077 A JP2003278077 A JP 2003278077A JP 4066911 B2 JP4066911 B2 JP 4066911B2
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semiconductor element
semiconductor
resin adhesive
electrodes
semiconductor device
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JP2005045043A (en
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義之 和田
忠彦 境
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

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Description

本発明は、半導体素子を重ねた積層構造に樹脂接着材を介して補強部材を結合して成る半導体装置の製造方法および半導体素子実装構造の形成方法に関するものである。 The present invention relates to a method of forming a manufacturing method and a semiconductor device mounting structure of the binding to adult Ru semiconductors device reinforcing member via a resin adhesive to the laminated structure of repeated semiconductor device.

下面にバンプが形成されたバンプ付きの半導体素子を実装する形態として、バンプ付きのパッケージ基板やバンプ付きのマザーチップなどの上に半導体素子を重ねて積層構造の半導体装置とする方法が知られている(例えば特許文献1)。近年半導体素子の薄型化が急速に進行しており、上述のような構成の半導体装置に薄型の半導体素子を用いる場合には、半導体素子の破損を防止するため半導体素子を上面から封止樹脂して保護する方法が用いられる。
特開平11−214419号公報
As a form of mounting a bumped semiconductor element having a bump formed on the lower surface, a method of stacking a semiconductor element on a bumped package substrate, a bumped mother chip or the like to form a semiconductor device having a laminated structure is known. (For example, Patent Document 1). In recent years, thinning of semiconductor elements has been progressing rapidly, and when thin semiconductor elements are used in a semiconductor device having the above-described configuration, the semiconductor elements are sealed from the upper surface in order to prevent damage to the semiconductor elements. The protection method is used.
JP 11-214419 A

しかしながら上述のように半導体素子を上面から樹脂封止する方法においては、下層のパッケージ基板やマザーチップに反り変形を生じやすく、完成した半導体装置をマザーボードに実装する際にバンプの浮きなどの接合不具合を生じる場合があり、実装信頼性の確保が困難であった。特にマザーチップとして薄型の半導体素子を採用した場合には、この傾向が顕著であった。   However, in the method of sealing the semiconductor element from the upper surface as described above, the lower package substrate and the mother chip are likely to be warped and deformed. In some cases, it was difficult to ensure mounting reliability. This tendency was particularly remarkable when a thin semiconductor element was used as the mother chip.

そこで本発明は、実装信頼性の高い半導体装置の製造方法および半導体素子実装構造の形成方法を提供することを目的とする。 The present invention aims to provide a method of forming a manufacturing method and a semiconductor device mounting structure of the high have semi conductor device mounting reliability.

本発明の半導体装置の製造方法は、一方の面に第1の電極が複数形成され他方の面に第2の電極が複数形成された第1の半導体素子と一方の面に第3の電極が複数形成された半導体素子とを重ねて積層構造とし、第1の半導体素子1の前記他方の面と第2の半導体素子の前記一方の面とを対向させて前記第3の電極を前記第2の電極に接続するとともに、前記第1の半導体素子の他方の面および前記第2の半導体素子の他方の面に樹脂接着材を介して一体の補強部材を結合した構成の半導体装置を製造する半導体装置の製造方法であって、前記積層構造と結合される前記補強部材に前記樹脂接着材を塗布し、前記樹脂接着材が塗布された前記補強部材上に前記積層構造を搭載し、次いで前記補強部材および積層構造を一体化した結合体を加熱して前記樹脂接着材を熱硬化させるものである。 Method of manufacturing a semi-conductor device of the present invention, the third electrode to the first semiconductor element and one surface of the second electrode has a plurality of formed on a surface of the first electrode is formed with a plurality of other on one surface A plurality of semiconductor elements are stacked to form a stacked structure, and the third electrode is disposed in the first semiconductor element 1 with the other surface of the first semiconductor element 1 facing the one surface of the second semiconductor element. And a semiconductor device having a configuration in which an integral reinforcing member is coupled to the other surface of the first semiconductor element and the other surface of the second semiconductor element via a resin adhesive. A method of manufacturing a semiconductor device, wherein the resin adhesive is applied to the reinforcing member coupled to the laminated structure, the laminated structure is mounted on the reinforcing member to which the resin adhesive is applied, and then the Heating the combined body of reinforcing member and laminated structure It is intended to thermally cure the resin adhesive Te.

本発明の半導体素子実装構造の形成方法は、一方の面に第1の電極が複数形成され他方の面に第2の電極が複数形成された第1の半導体素子1を接続用電極が複数形成された基板に実装して前記第1の電極を前記接続用電極に電気的に接続し、一方の面に第3の電極が複数形成された第2の半導体素子を前記第1の半導体素子の上方に重ねて実装して成る積層構造を有し、前記第1の半導体素子の他方の面および前記第2の半導体素子の他方の面に樹脂接着材を介して一体の補強部材を結合した構成の半導体素子実装構造を形成する半導体素子実装構造の形成方法であって、前記第1の半導体素子を前記基板に実装し、前記第1の半導体素子の裏面に樹脂接着材を塗布し、前記第1の半導体素子の樹脂塗布面に前記第2の半導体素子を搭載し、前記第2の半導体素子の上面に樹脂接着材を塗布し、前記第2の半導体素子の樹脂塗布面に前記補強部材を搭載し、次いで前記基板を加熱して前記樹脂接着材を熱硬化させるものである。 Method of forming a semi-conductor element mounting structure of the present invention, first the first semiconductor element 1 connection electrodes plurality electrodes has a second electrode formed in plural on the other surface formed with a plurality of on one surface The first semiconductor element is mounted on the formed substrate to electrically connect the first electrode to the connection electrode, and a second semiconductor element having a plurality of third electrodes formed on one surface. And an integrated reinforcing member is coupled to the other surface of the first semiconductor element and the other surface of the second semiconductor element via a resin adhesive. A semiconductor element mounting structure forming method for forming a semiconductor element mounting structure having a configuration, wherein the first semiconductor element is mounted on the substrate, and a resin adhesive is applied to a back surface of the first semiconductor element, The second semiconductor element is mounted on the resin-coated surface of the first semiconductor element. A resin adhesive is applied to the upper surface of the second semiconductor element, the reinforcing member is mounted on the resin application surface of the second semiconductor element, and then the substrate is heated to thermally cure the resin adhesive It is.

本発明によれば、第1の半導体素子1と第2の半導体素子とを重ねた積層構造において、第1の半導体素子1の他方の面および第2の半導体素子の他方の面に樹脂接着材を介して一体の補強部材を結合する構成を採用することにより、薄型の半導体素子を用いる場合にあっても、補強部材によって半導体素子を外力から保護するとともに半導体素子の反り変形を抑制して、実装信頼性の高い半導体装置の製造方法および半導体素子実装構造の形成方法を実現することができる。 According to the present invention, the resin adhesive is applied to the other surface of the first semiconductor element 1 and the other surface of the second semiconductor element in the stacked structure in which the first semiconductor element 1 and the second semiconductor element are stacked. By adopting a configuration in which the integral reinforcing member is coupled through the thin member, even when a thin semiconductor element is used, the reinforcing member protects the semiconductor element from external force and suppresses warping deformation of the semiconductor element. method of forming a manufacturing method and a semiconductor device mounting structure of the high have semi conductor device mounting reliability can be realized.

(実施の形態1)
図1、図2は本発明の実施の形態1の半導体装置の製造方法の工程説明図、図3は本発明の一実施の形態の半導体装置の部分断面図である。
(Embodiment 1)
1 and 2 are process explanatory views of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 3 is a partial cross-sectional view of the semiconductor device according to one embodiment of the present invention.

図1(a)において、第1の半導体素子1の回路形成面1a(一方の面)には、第1の電極2が複数形成されており、裏面1b(他方の面)には第2の電極3a、3bがそれぞれ複数形成されている。第1の半導体素子1は、厚みが100μm以下の薄型の半導体素子である。第2の電極3aは、第1の半導体素子1を貫通して回路形成面1a側に形成された回路電極に電気的に接続されている。   In FIG. 1A, a plurality of first electrodes 2 are formed on the circuit forming surface 1a (one surface) of the first semiconductor element 1, and the second surface is formed on the back surface 1b (the other surface). A plurality of electrodes 3a and 3b are formed. The first semiconductor element 1 is a thin semiconductor element having a thickness of 100 μm or less. The second electrode 3a penetrates the first semiconductor element 1 and is electrically connected to a circuit electrode formed on the circuit forming surface 1a side.

第1の半導体素子1には、図1(b)に示すように、回路形成面4a(一方の面)にバンプ5(第3の電極)が複数形成された第2の半導体素子4が、第1の半導体素子1の裏面1bと第2の半導体素子4の回路形成面4aとを対向させて、搭載ヘッド6によって搭載される。第2の半導体素子4は、第1の半導体素子1と同様に厚みが100μm以下の薄型の半導体素子であり、バンプ5を第2の電極3a、3bと接続することにより、第1の半導体素子1に実装される。これにより、図1(c)に示すように、第1の半導体素子1と第2の半導体素子4とを重ねた積層構造7が形成される。第2の半導体素子4の実装方法としては、超音波接合、熱圧着のいずれを用いてもよい。   As shown in FIG. 1B, the first semiconductor element 1 includes a second semiconductor element 4 in which a plurality of bumps 5 (third electrodes) are formed on a circuit formation surface 4a (one surface). The first semiconductor element 1 is mounted by the mounting head 6 with the back surface 1b of the first semiconductor element 1 and the circuit forming surface 4a of the second semiconductor element 4 facing each other. Similar to the first semiconductor element 1, the second semiconductor element 4 is a thin semiconductor element having a thickness of 100 μm or less. By connecting the bumps 5 to the second electrodes 3a and 3b, the first semiconductor element 4 is formed. 1 is implemented. Thereby, as shown in FIG.1 (c), the laminated structure 7 which piled up the 1st semiconductor element 1 and the 2nd semiconductor element 4 is formed. As a mounting method of the second semiconductor element 4, either ultrasonic bonding or thermocompression bonding may be used.

この後、図1(d)に示すように、積層構造7と結合されるバンパ部材8の上面に、ディスペンサ10によって樹脂接着材9が塗布される。バンパ部材8は、積層構造7と結合されることによって、薄型の第1の半導体素子1,第2の半導体素子4の変形を防止する補強部材としての機能を有するものである。材質としてはセラミックや樹脂または金属のいずれでもよく、積層構造7の変形を防止するのに必要な剛性を確保するのに必要十分な厚さに加工されたものが用いられる。なお、高剛性という点でセラミックまたは金属が望ましい。   Thereafter, as shown in FIG. 1 (d), a resin adhesive 9 is applied by a dispenser 10 on the upper surface of the bumper member 8 coupled to the laminated structure 7. The bumper member 8 has a function as a reinforcing member that prevents deformation of the thin first semiconductor element 1 and the second semiconductor element 4 by being coupled to the laminated structure 7. The material may be ceramic, resin, or metal, and a material processed to have a thickness necessary and sufficient to ensure the rigidity necessary to prevent deformation of the laminated structure 7 is used. Note that ceramic or metal is desirable in terms of high rigidity.

樹脂接着材9はエポキシ樹脂などを主剤とする樹脂成分に、無機物もしくは樹脂よりなる粒子状のフィラー成分を含有させた組成となっている。樹脂成分としては、熱硬化性樹脂、熱可塑性樹脂のいずれを用いてもよい。ここでフィラー成分は、樹脂接着材9が接着層を形成した状態において接着層に所望の特性(弾性率)を付与するためのフィラー本来の機能以外に、半導体素子2とバンパ部材8との間に介在して接着層の厚みを所定厚みに確保するスペーサとしての機能をも併せ有している。   The resin adhesive 9 has a composition in which a particulate filler component made of an inorganic substance or a resin is contained in a resin component mainly composed of an epoxy resin or the like. As the resin component, either a thermosetting resin or a thermoplastic resin may be used. Here, the filler component has a function between the semiconductor element 2 and the bumper member 8 in addition to the original function of the filler for imparting a desired characteristic (elastic modulus) to the adhesive layer in a state where the resin adhesive 9 forms the adhesive layer. It also has a function as a spacer that intervenes in and secures the thickness of the adhesive layer to a predetermined thickness.

このため樹脂接着材9には、以下に説明する第1フィラーおよび第2フィラーの2種類のフィラーを、合計の含有率が30重量%以下となるような含有率で含有させるようにしている。先ず上述のスペーサとしての機能を果たす第1フィラー9aは、半導体装置において接着層の目標とする厚みt(図2(b)、図3参照)と略等しい寸法の直径dを有する粒子であり、直径dは樹脂接着材9中に含まれるフィラー中の最大径となっている。すなわち、第1フィラー9aは樹脂接着材9中に含まれるフィラーの最大径であり且つ接着層の所定厚みと略等しい寸法の直径dを有する。そして第1フィラー9a以外の第2フィラー9bは、直径が第1フィラー9bの直径dよりも小さいフィラーの集合であり、フィラー本来の機能に適した粒径分布のものが選定される。   For this reason, the resin adhesive 9 contains two kinds of fillers, a first filler and a second filler, which will be described below, at a content such that the total content is 30% by weight or less. First, the first filler 9a that functions as the spacer described above is a particle having a diameter d that is approximately equal to the target thickness t (see FIGS. 2B and 3) of the adhesive layer in the semiconductor device. The diameter d is the maximum diameter in the filler contained in the resin adhesive 9. That is, the first filler 9a has a diameter d that is the maximum diameter of the filler contained in the resin adhesive 9 and that is approximately equal to the predetermined thickness of the adhesive layer. The second filler 9b other than the first filler 9a is a set of fillers having a diameter smaller than the diameter d of the first filler 9b, and is selected to have a particle size distribution suitable for the original function of the filler.

次に、図2(a)に示すように、接着材塗布後のバンパ部材8上に、積層構造7が搭載される。このとき、図1(c)に示す状態の積層構造7を反転して、第1の半導体素子1の裏面1b、第2の半導体素子4の裏面4bを樹脂接着材9に向けた姿勢で搭載する。そして図2(b)に示すように、バンパ部材8および積層構造7を一体化した結合体を加熱して樹脂接着材9を熱硬化させることにより、回路形成面1a(一方の面)に第1の電極
2が複数形成され裏面1b(他方の面)に第2の電極3a,3bが複数形成された第1の半導体素子1と、回路形成面(一方の面)にバンプ5(第3の電極)が複数形成された第2の半導体素子4とを重ねて積層構造とした半導体装置11が完成する。
Next, as shown in FIG. 2A, the laminated structure 7 is mounted on the bumper member 8 after application of the adhesive. At this time, the stacked structure 7 in the state shown in FIG. 1C is reversed and mounted so that the back surface 1 b of the first semiconductor element 1 and the back surface 4 b of the second semiconductor element 4 face the resin adhesive 9. To do. Then, as shown in FIG. 2 (b), by heating the combined body in which the bumper member 8 and the laminated structure 7 are integrated to thermally cure the resin adhesive 9, the circuit forming surface 1a (one surface) is A first semiconductor element 1 in which a plurality of one electrodes 2 are formed and a plurality of second electrodes 3a and 3b are formed on a back surface 1b (the other surface), and a bump 5 (third surface) on a circuit forming surface (one surface). The semiconductor device 11 having a stacked structure is completed by overlapping the second semiconductor element 4 having a plurality of electrodes).

そしてこの半導体装置11は、第1の半導体素子1の裏面1bと第2の半導体素子4の回路形成面4aとを対向させて、バンプ5を第2の電極3a,3bに接続するとともに、第1の半導体素子1の裏面1bおよび第2の半導体素子の裏面4bに樹脂接着材9を介して一体のバンパ部材8を結合した構成となっている。   The semiconductor device 11 connects the bumps 5 to the second electrodes 3a and 3b with the back surface 1b of the first semiconductor element 1 and the circuit forming surface 4a of the second semiconductor element 4 facing each other, The integrated bumper member 8 is coupled to the back surface 1b of the first semiconductor element 1 and the back surface 4b of the second semiconductor element via the resin adhesive 9.

積層構造7とバンパ部材8の結合に際し、前述のような第1フィラー9aを含む樹脂接着材9を介して半導体素子2をバンパ部材8に搭載して所定の加圧力でバンパ8に対して押圧すると、図3に示すように、樹脂接着材9中のフィラーのうち最大径の第1フィラー9aは、半導体素子4の裏面に接触するとともにバンパ部材8にも接触した状態で挟まれる。これにより、接着層の厚みtは第1フィラー9aの直径dに等しくなる。   When the laminated structure 7 and the bumper member 8 are coupled, the semiconductor element 2 is mounted on the bumper member 8 through the resin adhesive 9 including the first filler 9a as described above and pressed against the bumper 8 with a predetermined pressure. Then, as shown in FIG. 3, the first filler 9 a having the maximum diameter among the fillers in the resin adhesive 9 is sandwiched between the back surface of the semiconductor element 4 and the bumper member 8. Thereby, the thickness t of the adhesive layer becomes equal to the diameter d of the first filler 9a.

このようにして形成された半導体装置11をバンプ付き部品として使用する場合には、図2(c)に示すように、第1の電極2にボール移載ヘッド13により半田ボール12を搭載し、次いで図2(d)に示すように、リフロー工程において半導体装置11を加熱することにより半田ボール12が溶融し、第1の電極2上に半田バンプ12aが形成される。   When the semiconductor device 11 formed in this way is used as a bumped part, as shown in FIG. 2C, the solder ball 12 is mounted on the first electrode 2 by the ball transfer head 13, Next, as shown in FIG. 2 (d), the solder ball 12 is melted by heating the semiconductor device 11 in the reflow process, and a solder bump 12 a is formed on the first electrode 2.

このようにして形成された半導体装置11は、半導体素子を2層積層した構造であることから高密度実装が可能になるとともに、積層構造の形成に薄型の第1の半導体素子1、第2の半導体素子4を用いていることから、半導体装置11としての厚みを極力薄くすることが可能となっている。そして、撓みやすく破損しやすい薄型の半導体素子より成る積層構造をバンパ部材8によって補強する構成を採用していることから、積層構造を外力から有効に保護することができる。   Since the semiconductor device 11 formed in this way has a structure in which two layers of semiconductor elements are stacked, it can be mounted at a high density, and the first semiconductor element 1 and the second thin film are formed to form a stacked structure. Since the semiconductor element 4 is used, the thickness of the semiconductor device 11 can be reduced as much as possible. And since the structure which reinforces the laminated structure which consists of a thin semiconductor element which is easy to bend and breaks with the bumper member 8, a laminated structure can be effectively protected from external force.

このバンプ付きの半導体装置11を半田バンプ12aを介して基板に実装して成る実装構造において、実装後に基板に何らかの外力により撓み変形が発生した場合には、第1の半導体素子1、第2の半導体素子4はいずれも薄くて撓みやすく、しかも樹脂接着材9は変形しやすいことから、基板の撓み変形に対して第1の半導体素子1、第2の半導体素子4および樹脂接着材9が追従して変形する。したがって、基板の撓み変形によって半田バンプ12aの接合部に生じる応力を低減して、実装後の信頼性を向上させることができる。   In the mounting structure in which the semiconductor device 11 with bumps is mounted on the substrate via the solder bumps 12a, when the substrate is deformed by some external force after mounting, the first semiconductor element 1 and the second semiconductor element 11 Since the semiconductor elements 4 are all thin and flexible, and the resin adhesive 9 is easily deformed, the first semiconductor element 1, the second semiconductor element 4 and the resin adhesive 9 follow the deformation of the substrate. And deform. Therefore, it is possible to reduce the stress generated in the joint portion of the solder bump 12a due to the bending deformation of the substrate, and to improve the reliability after mounting.

(実施の形態2)
図4、図5は本発明の実施の形態2の半導体装置の製造方法の工程説明図である。本実施の形態は、実施の形態1に示す構成の半導体装置11を製造するに際し、個片状態の第1の半導体素子1を対象とする替わりに、第1の半導体素子1が多数組み込まれた半導体ウェハを対象とするものである。図4(a)において、半導体ウェハ101の回路形成面101a(第1の面)には、第1の電極102が複数形成されており、裏面101bには第2の電極103a、103bがそれぞれ複数形成されている。半導体ウェハ101は、厚みが100μm以下の薄型の半導体素子が作り込まれた半導体ウェハである。第2の電極103aは、半導体ウェハ101を貫通して回路形成面101a側に形成された回路電極に電気的に接続されている。
(Embodiment 2)
4 and 5 are process explanatory views of the method of manufacturing the semiconductor device according to the second embodiment of the present invention. In the present embodiment, when the semiconductor device 11 having the configuration shown in the first embodiment is manufactured, a large number of the first semiconductor elements 1 are incorporated in place of the first semiconductor element 1 in the individual state. It is intended for semiconductor wafers. In FIG. 4A, a plurality of first electrodes 102 are formed on the circuit forming surface 101a (first surface) of the semiconductor wafer 101, and a plurality of second electrodes 103a and 103b are formed on the back surface 101b. Is formed. The semiconductor wafer 101 is a semiconductor wafer in which a thin semiconductor element having a thickness of 100 μm or less is formed. The second electrode 103a penetrates the semiconductor wafer 101 and is electrically connected to a circuit electrode formed on the circuit forming surface 101a side.

半導体ウェハ101には、図4(b)に示すように、回路形成面4aにバンプ5(第3の電極)が複数形成された第2の半導体素子4が、半導体ウェハ101の裏面101bと第2の半導体素子4の回路形成面4aとを対向させて、搭載ヘッド6によって搭載される
。第2の半導体素子4は、半導体ウェハ101と同様に厚みが100μm以下の薄型の半導体素子であり、バンプ5を第2の電極103a、103bと接続することにより、半導体ウェハ101の各半導体素子に実装される。これにより、図4(c)に示すように、半導体ウェハ101と第2の半導体素子4とを重ねたウェハ状態の積層構造107が形成される。
As shown in FIG. 4B, the second semiconductor element 4 having a plurality of bumps 5 (third electrodes) formed on the circuit formation surface 4 a is formed on the semiconductor wafer 101 with the back surface 101 b of the semiconductor wafer 101 and the second semiconductor element 101. The semiconductor head 4 is mounted by the mounting head 6 so as to face the circuit forming surface 4 a of the semiconductor element 4. Similar to the semiconductor wafer 101, the second semiconductor element 4 is a thin semiconductor element having a thickness of 100 μm or less. By connecting the bump 5 to the second electrodes 103a and 103b, the second semiconductor element 4 is connected to each semiconductor element of the semiconductor wafer 101. Implemented. As a result, as shown in FIG. 4C, a laminated structure 107 in a wafer state in which the semiconductor wafer 101 and the second semiconductor element 4 are overlaid is formed.

この後、図1(d)に示すように、積層構造107と結合されるバンパ部材108の上面に、ディスペンサ10によって実施の形態1に示す樹脂接着材9が塗布される。なお、樹脂接着材9を塗布する替わりに、同様組成の樹脂接着材を薄膜状に成形した樹脂シートをバンパ部材108に貼付ける方法を用いてもよい。   Thereafter, as shown in FIG. 1 (d), the resin adhesive 9 shown in the first embodiment is applied to the upper surface of the bumper member 108 coupled to the laminated structure 107 by the dispenser 10. Instead of applying the resin adhesive 9, a method may be used in which a resin sheet obtained by forming a resin adhesive having the same composition into a thin film is attached to the bumper member.

次に、図5(a)に示すように、接着剤塗布後のバンパ部材8上に、積層構造107が搭載される。このとき、図4(c)に示す状態の積層構造107を反転して、半導体ウェハ101の裏面101b、第2の半導体素子4の裏面4bを樹脂接着材9に向けた姿勢で搭載する。そして図2(b)に示すように、バンパ部材108および積層構造107を加熱して樹脂接着材9を熱硬化させることにより、半導体装置111が完成する。このとき、第1の半導体素子4とバンパ部材108との間の隙間は実施の形態1と同様に樹脂接着材9中の第1フィラー9aによっての所定の厚みtに保たれる。   Next, as shown in FIG. 5A, the laminated structure 107 is mounted on the bumper member 8 after application of the adhesive. At this time, the laminated structure 107 in the state shown in FIG. 4C is reversed and mounted so that the back surface 101b of the semiconductor wafer 101 and the back surface 4b of the second semiconductor element 4 face the resin adhesive 9. Then, as shown in FIG. 2B, the bumper member 108 and the laminated structure 107 are heated to thermally cure the resin adhesive 9, thereby completing the semiconductor device 111. At this time, the gap between the first semiconductor element 4 and the bumper member 108 is maintained at a predetermined thickness t by the first filler 9a in the resin adhesive 9 as in the first embodiment.

この後、半導体装置111はダイシング工程に送られ、図5(c)に示すように、半導体装置111をブレード17によって半導体素子の個片毎に切断することにより、図5(d)に示すように、一方の面に第1の電極が複数形成され他方の面に第2の電極が複数形成された第1の半導体素子1と一方の面に第3の電極が複数形成された第2の半導体素子とを重ねて積層構造とした半導体装置111aが完成する。そしてこのようにして形成された半導体装置111aをバンプ付き部品として使用する場合には、実施の形態1の図2(c)、(d)に示すバンプ形成工程を経ることにより、第1の電極2上に半田バンプが形成される。   Thereafter, the semiconductor device 111 is sent to a dicing process, and as shown in FIG. 5C, the semiconductor device 111 is cut into individual pieces of semiconductor elements by the blade 17 as shown in FIG. In addition, a first semiconductor element 1 having a plurality of first electrodes formed on one surface and a plurality of second electrodes formed on the other surface and a second semiconductor device having a plurality of third electrodes formed on one surface A semiconductor device 111a having a stacked structure in which semiconductor elements are stacked is completed. When the semiconductor device 111a formed in this way is used as a component with bumps, the first electrode is obtained through the bump formation step shown in FIGS. 2C and 2D of the first embodiment. Solder bumps are formed on 2.

(実施の形態3)
図6、図7は本発明の実施の形態3の半導体実装構造における実装過程の工程説明図である。本実施の形態3は、実施の形態1に示す半導体装置11を基板に実装した実装構造と同一構成の実装構造を、個片状態の半導体素子を基板に直接実装することによって実現するものである。
(Embodiment 3)
6 and 7 are process explanatory diagrams of the mounting process in the semiconductor mounting structure according to the third embodiment of the present invention. In the third embodiment, a mounting structure having the same configuration as the mounting structure in which the semiconductor device 11 shown in the first embodiment is mounted on a substrate is realized by directly mounting individual semiconductor elements on the substrate. .

図6(a)において、基板15の上面には、複数の接続用電極16が形成されている。基板15には、実施の形態に示すものと同様の第1の半導体素子1が実装される。第1の半導体素子1の回路形成面1a(第1の面)には、第1の電極2が複数形成されており、裏面1bには第2の電極3a、第2の電極3bがそれぞれ複数形成されており、さらに第1の電極2には半田バンプ14が形成されている。第1の半導体素子1は、厚みが100μm以下の薄型の半導体素子である。第2の電極3aは、第1の半導体素子1を貫通して回路形成面1a側に形成された回路電極に電気的に接続されている。   In FIG. 6A, a plurality of connection electrodes 16 are formed on the upper surface of the substrate 15. A first semiconductor element 1 similar to that shown in the embodiment is mounted on the substrate 15. A plurality of first electrodes 2 are formed on the circuit formation surface 1a (first surface) of the first semiconductor element 1, and a plurality of second electrodes 3a and a plurality of second electrodes 3b are formed on the back surface 1b. In addition, solder bumps 14 are formed on the first electrode 2. The first semiconductor element 1 is a thin semiconductor element having a thickness of 100 μm or less. The second electrode 3a penetrates the first semiconductor element 1 and is electrically connected to a circuit electrode formed on the circuit forming surface 1a side.

図6(b)に示すように、半田バンプ14は接続用電極16と接合され、次いで図6(c)に示すように、第1の半導体素子1の裏面1bには、樹脂接着材9がディスペンサ10によって塗布される。次いで、図6(d)に示すように、第1の半導体素子1の樹脂塗布面には、回路形成面にバンプ5(第3の電極)が複数形成された第2の半導体素子4が搭載され、図7(a)に示すように、バンプ5を第2の電極3a、3bに接続する。   As shown in FIG. 6B, the solder bumps 14 are joined to the connection electrodes 16, and then, as shown in FIG. 6C, the resin adhesive 9 is applied to the back surface 1b of the first semiconductor element 1. It is applied by the dispenser 10. Next, as shown in FIG. 6D, the second semiconductor element 4 having a plurality of bumps 5 (third electrodes) formed on the circuit forming surface is mounted on the resin-coated surface of the first semiconductor element 1. Then, as shown in FIG. 7A, the bump 5 is connected to the second electrodes 3a and 3b.

図7(b)この後、第2の半導体素子4の上面を覆って、樹脂接着材9がディスペンサ10により塗布され、次いで図7(c)に示すように、樹脂接着材9の塗布面にはバンパ
部材8が搭載される。そして基板15を加熱して樹脂接着材9を熱硬化させることにより、図7(d)に示すように、半導体素子実装構造が完成する。このとき、第1の半導体素子4とバンパ部材8との間の隙間は、実施の形態1と同様に樹脂接着材9中の第1フィラー9aによって所定の厚みtに保たれる。
7B, after that, the resin adhesive 9 is applied by the dispenser 10 so as to cover the upper surface of the second semiconductor element 4, and then on the application surface of the resin adhesive 9 as shown in FIG. 7C. The bumper member 8 is mounted. Then, by heating the substrate 15 and thermosetting the resin adhesive 9, the semiconductor element mounting structure is completed as shown in FIG. At this time, the gap between the first semiconductor element 4 and the bumper member 8 is maintained at a predetermined thickness t by the first filler 9a in the resin adhesive 9 as in the first embodiment.

この半導体素子実装構造は、回路形成面1a(一方の面)に第1の電極2が複数形成され裏面1b(他方の面)に第2の電極3a,3bが複数形成された第1の半導体素子1を、接続用電極16が複数形成された基板15に実装して第1の電極2をバンプ14を介して接続用電極15に電気的に接続し、回路形成面4a(一方の面)にバンプ5(第3の電極)が複数形成された第2の半導体素子を第1の半導体素子1の上方に重ねて実装して成る積層構造となっている。   This semiconductor element mounting structure is a first semiconductor in which a plurality of first electrodes 2 are formed on a circuit forming surface 1a (one surface) and a plurality of second electrodes 3a, 3b are formed on a back surface 1b (the other surface). The element 1 is mounted on a substrate 15 on which a plurality of connection electrodes 16 are formed, and the first electrode 2 is electrically connected to the connection electrodes 15 via the bumps 14 to form a circuit forming surface 4a (one surface). The second semiconductor element having a plurality of bumps 5 (third electrodes) formed thereon is stacked on the first semiconductor element 1 and mounted.

この半導体素子実装構造において、第1の半導体素子1の他方の面および第2の半導体素子4の他方の面に、樹脂接着材9を介して一体の補強部材8を結合した形態となっており、実施の形態1において説明したように、実装後の熱サイクル過程における応力を低減して、実装信頼性を向上させることができる。   In this semiconductor element mounting structure, an integral reinforcing member 8 is coupled to the other surface of the first semiconductor element 1 and the other surface of the second semiconductor element 4 via a resin adhesive 9. As described in the first embodiment, the mounting reliability can be improved by reducing the stress in the thermal cycle process after mounting.

本発明の半導体装置の製造方法および半導体素子実装構造の形成方法は、薄型の半導体素子を用いる場合にあっても補強部材によって半導体素子を外力から保護するとともに半導体素子の反り変形を抑制して、実装信頼性の高い半導体装置および半導体素子実装構造を実現することができるという利点を有し、半導体素子を重ねた積層構造に樹脂接着材を介して補強部材を結合して成る半導体装置および半導体素子実装構造において有用である。 Method of forming a manufacturing method and a semiconductor device mounting structure of the semi-conductor device of the present invention, by suppressing the warping deformation of the semiconductor device to protect the semiconductor element from external force by the reinforcing member in cases of using a thin semiconductor element A semiconductor device and a semiconductor having an advantage that a semiconductor device and a semiconductor element mounting structure with high mounting reliability can be realized, and a reinforcing member is bonded to a laminated structure in which semiconductor elements are stacked via a resin adhesive This is useful in an element mounting structure.

本発明の実施の形態1の半導体装置の製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor device of Embodiment 1 of this invention 本発明の実施の形態1の半導体装置の製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor device of Embodiment 1 of this invention 本発明の一実施の形態の半導体装置の部分断面図The fragmentary sectional view of the semiconductor device of one embodiment of the present invention 本発明の実施の形態2の半導体装置の製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor device of Embodiment 2 of this invention 本発明の実施の形態2の半導体装置の製造方法の工程説明図Process explanatory drawing of the manufacturing method of the semiconductor device of Embodiment 2 of this invention 本発明の実施の形態3の半導体実装構造における実装過程の工程説明図Process explanatory drawing of the mounting process in the semiconductor mounting structure of Embodiment 3 of this invention 本発明の実施の形態3の半導体実装構造における実装過程の工程説明図Process explanatory drawing of the mounting process in the semiconductor mounting structure of Embodiment 3 of this invention

符号の説明Explanation of symbols

1、101 第1の半導体素子
2、102 第1の電極
3a、3b、103a、103b 第2の電極
4 第2の半導体素子
5 バンプ
7、107 積層構造
8、108 バンパ部材
9 樹脂接着材
11、111 半導体装置
14 半田バンプ
15 基板
16 接続用電極
DESCRIPTION OF SYMBOLS 1,101 1st semiconductor element 2,102 1st electrode 3a, 3b, 103a, 103b 2nd electrode 4 2nd semiconductor element 5 Bump 7, 107 Laminated structure 8, 108 Bumper member 9 Resin adhesive material 11, 111 Semiconductor Device 14 Solder Bump 15 Substrate 16 Connection Electrode

Claims (2)

一方の面に第1の電極が複数形成され他方の面に第2の電極が複数形成された第1の半導体素子と一方の面に第3の電極が複数形成された半導体素子とを重ねて積層構造とし、第1の半導体素子1の前記他方の面と第2の半導体素子の前記一方の面とを対向させて前記第3の電極を前記第2の電極に接続するとともに、前記第1の半導体素子の他方の面および前記第2の半導体素子の他方の面に樹脂接着材を介して一体の補強部材を結合した構成の半導体装置を製造する半導体装置の製造方法であって、
前記積層構造と結合される前記補強部材に前記樹脂接着材を塗布し、前記樹脂接着材が塗布された前記補強部材上に前記積層構造を搭載し、次いで前記補強部材および積層構造を一体化した結合体を加熱して前記樹脂接着材を熱硬化させることを特徴とする半導体装置の製造方法。
A first semiconductor element in which a plurality of first electrodes are formed on one surface and a plurality of second electrodes are formed on the other surface is overlapped with a semiconductor element in which a plurality of third electrodes are formed on one surface. The third electrode is connected to the second electrode with the other surface of the first semiconductor element 1 and the one surface of the second semiconductor element facing each other, and the first electrode is connected to the second electrode. A semiconductor device manufacturing method for manufacturing a semiconductor device having a configuration in which an integral reinforcing member is coupled to the other surface of the semiconductor element and the other surface of the second semiconductor element via a resin adhesive,
The resin adhesive is applied to the reinforcing member coupled to the laminated structure, the laminated structure is mounted on the reinforcing member to which the resin adhesive is applied, and then the reinforcing member and the laminated structure are integrated. A method for manufacturing a semiconductor device, comprising: heating a bonded body to thermally cure the resin adhesive.
一方の面に第1の電極が複数形成され他方の面に第2の電極が複数形成された第1の半導体素子1を接続用電極が複数形成された基板に実装して前記第1の電極を前記接続用電極に電気的に接続し、一方の面に第3の電極が複数形成された第2の半導体素子を前記第1の半導体素子の上方に重ねて実装して成る積層構造を有し、前記第1の半導体素子の他方の面および前記第2の半導体素子の他方の面に樹脂接着材を介して一体の補強部材を結合した構成の半導体素子実装構造を形成する半導体素子実装構造の形成方法であって、
前記第1の半導体素子を前記基板に実装し、前記第1の半導体素子の裏面に樹脂接着材を塗布し、前記第1の半導体素子の樹脂塗布面に前記第2の半導体素子を搭載し、前記第2の半導体素子の上面に樹脂接着材を塗布し、前記第2の半導体素子の樹脂塗布面に前記補強部材を搭載し、次いで前記基板を加熱して前記樹脂接着材を熱硬化させることを特徴とする半導体素子実装構造の形成方法。
A first semiconductor element 1 having a plurality of first electrodes formed on one surface and a plurality of second electrodes formed on the other surface is mounted on a substrate on which a plurality of connection electrodes are formed, and the first electrode is mounted. Is electrically connected to the connection electrode, and has a stacked structure in which a second semiconductor element having a plurality of third electrodes formed on one surface is mounted over the first semiconductor element. A semiconductor element mounting structure for forming a semiconductor element mounting structure in which an integral reinforcing member is coupled to the other surface of the first semiconductor element and the other surface of the second semiconductor element through a resin adhesive. A forming method of
Mounting the first semiconductor element on the substrate, applying a resin adhesive on the back surface of the first semiconductor element, and mounting the second semiconductor element on the resin-coated surface of the first semiconductor element; Applying a resin adhesive on the upper surface of the second semiconductor element, mounting the reinforcing member on the resin application surface of the second semiconductor element, and then heating the substrate to thermally cure the resin adhesive; A method of forming a semiconductor device mounting structure characterized by the above.
JP2003278077A 2003-07-23 2003-07-23 Semiconductor device manufacturing method and semiconductor element mounting structure forming method Expired - Fee Related JP4066911B2 (en)

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