JP4067422B2 - Data transfer device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer device, and more particularly to a data transfer device that arbitrates data transfer to a plurality of resources.
[0002]
[Prior art]
In some electronic devices, a plurality of resources share data in one storage device and perform pipeline processing. For example, in a digital camera, resources for capturing image data, resources for performing interpolation processing of captured image data, and the like share data in one storage device and perform pipeline processing.
[0003]
When such a plurality of resources share one storage device, a data transfer device that arbitrates access requests to the storage device of each resource and controls data transfer between each resource and the storage device is required. FIG. 11 is a circuit diagram of a conventional data transfer apparatus. As shown in the figure, the data transfer device includes a storage device 101, a transfer arbitration circuit 102, buffers 103a and 103b, registers 104a and 104b, control circuits 105a and 105b, and resources 106a and 106b. The transfer CH0 shown in the figure represents a collection of circuits for transferring the data Dat0 to the resource 106a, and includes a buffer 103a, a register 104a, and a control circuit 105a. The transfer CH1 indicates a collection of circuits for transferring the data Dat1 to the resource 106b, and includes a buffer 103b, a register 104b, and a control circuit 105b.
[0004]
When the transfer arbitration circuit 102 receives the request signals Req0 and Req1 from the control circuits 105a and 105b of the transfer CH0 and CH1, the transfer arbitration circuit 102 determines the priority of the resources 106a and 106b to which the data transfer is to be performed, and the determined resource 106a having the higher priority. , 106b, response signals Ack0, Ack1 are output to the control circuits 105a, 105b. Then, the transfer arbitration circuit 102 outputs the data Dat0 and Dat1 stored in the storage device 101 to the buffers 103a and 103b according to the transfer amounts Trs0 and Trs1 set in the registers 104a and 104b. In addition, there is a round robin as a distribution method that does not concentrate data access on resources with high priority.
[0005]
The buffers 103a and 103b of the transfer CH0 and CH1 temporarily store the data Dat0 and Dat1 transferred from the transfer arbitration circuit 102 and output them to the resources 106a and 106b. The control circuits 105a and 105b output request signals Req0 and Req1 when the free areas of the buffers 103a and 103b become a predetermined size. The registers 104a and 104b store transfer amounts Trs0 and Trs1 when the transfer arbitration circuit 102 performs data transfer at a time.
[0006]
The operation will be described below. FIG. 12 is a timing chart for explaining the operation of the data transfer apparatus of FIG. As illustrated in FIG. 12, when receiving the request signal Req0, the transfer arbitration circuit 102 determines the priority of the resource 106a corresponding to the request signal Req0. If the resource 106a has a higher priority than the other resources 106b, the transfer arbitration circuit 102 returns a response signal Ack0 to the control circuit 105a. Then, the transfer arbitration circuit 102 transfers the data Dat0 to the buffer 103a according to the transfer amount Trs0 (transfer of 16 addresses of the storage device 101 (fixed)) set in the register 104a. As a result, the empty size Siz0 of the buffer 103a is reduced by 16 addresses from '1Ch' to '0Dh' (h: indicating a hexadecimal number) as shown in FIG.
[0007]
By the way, when the data Dat0 and Dat1 stored in the buffers 103a and 103b are emptied, the resources 106a and 106b cannot execute processing, and an error occurs. Therefore, it is necessary to set the transfer amounts Trs0 and Trs1 so that the data Dat0 and Dat1 are always stored in the buffers 103a and 103b.
[0008]
As a device for arbitrating data transfer, there is a device in which a circuit using a bus notifies the arbitration circuit of a transfer amount of data to be transferred (for example, patents). Reference 1).
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-49485 (page 3, FIG. 1)
[0010]
[Problems to be solved by the invention]
However, in order to ensure that data is always stored in the buffer, it is necessary to set a large amount of data transfer, and since the transfer amount is fixed, only a small amount of data is required for the resource. Even when it is not, a large amount of data is transferred to the buffer, and when a large amount of data is required, only a small amount of data is transferred to the buffer.
[0011]
The present invention has been made in view of the above points, and provides a data transfer device that transfers data according to the amount of data required by a resource and improves the transfer efficiency of data from a storage device to a plurality of resources. The purpose is to provide.
[0012]
[Means for Solving the Problems]
In the present invention, in order to solve the above problems, In a data transfer device that arbitrates data transfer, a storage device that stores data shared by a plurality of resources, a transfer arbitration circuit that transfers the data according to a transfer amount indicated by the resource having a high transfer priority, A buffer that is provided for each resource and temporarily stores and outputs the data transferred from the transfer arbitration circuit, a threshold register that sets a threshold value for an area for each buffer, and a transfer amount increase prohibition threshold value are set. An increase prohibition register, a reduction request register in which a transfer amount reduction request threshold is set, and whether or not the free space for each buffer has reached the threshold, the transfer amount is increased or decreased, and the free space for each buffer is When the transfer amount increase prohibition threshold is reached, the transfer amount is prohibited from increasing in the resource having a lower transfer priority, and the transfer is prohibited. When it reaches the reduction request threshold, the transfer amount adjusting circuit for reducing the transfer amount at low the resource of another transfer priority, A data transfer device is provided.
[0013]
According to such a data transfer device, a plurality of resource Every Buff provided in Of Free space is threshold threshold To Set threshold In value Depending on whether or not Place Lalitho To Data to transfer Of transfer Amount Increase or decrease. Also, if the free space for each buffer reaches the transfer amount increase prohibition threshold, increase of the transfer amount in other low transfer priority resources is prohibited, and if the transfer amount reduction request threshold is reached, other The amount of transfer in a resource having a low transfer priority is reduced. Therefore, Without drastically reducing the data transfer efficiency of low priority resources, Memory Place Multiple resource To Day of Of Increase transfer efficiency.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The data transfer apparatus of the present invention is applied to, for example, a digital camera. A resource for capturing image data of a digital camera, a resource for performing interpolation processing of captured image data, and the like share data in one storage device and perform pipeline processing. The data transfer device efficiently transfers data stored in the storage device to a resource having a high priority.
[0017]
FIG. 1 is a circuit diagram of the data transfer apparatus according to the first embodiment. As shown in the figure, the data transfer device includes a storage device 1, a transfer arbitration circuit 2, buffers 3a and 3b, threshold registers 4a and 4b, a transfer amount adjustment circuit 5, and resources 7a and 7b. The transfer CH0 shown in the figure represents a collection of circuits for transferring the data Dat0 to the resource 7a, and includes a buffer 3a, a threshold register 4a, and a control circuit 6a. The transfer CH1 indicates a collection of circuits for transferring the data Dat1 to the resource 7b, and includes a buffer 3b, a threshold register 4b, and a control circuit 6b.
[0018]
The storage device 1 stores data Dat0 and Dat1 shared by the resources 7a and 7b. The storage device 1 is, for example, an SRAM (Static Random Access Memory) or an SDRAM (Synchronous Dynamic Random Access Memory).
[0019]
When the transfer arbitration circuit 2 receives the request signals Req0 and Req1 output from the control circuits 6a and 6b, the transfer arbitration circuit 2 determines the resources 7a and 7b having high priority for data transfer. When the transfer arbitration circuit 2 determines the resources 7a and 7b having high priority, the transfer arbitration circuit 2 outputs response signals Ack0 and Ack1 to the control circuits 6a and 6b of the transfer CH0 and CH1 corresponding to the resources 7a and 7b. The transfer arbitration circuit 2 was stored in the storage device 1 in the buffers 3a and 3b of the transfer CH0 and CH1 that output the response signals Ack0 and Ack1 according to the transfer amounts Trs0 and Trs1 output from the transfer amount adjustment circuit 5. Data Dat0 and Dat1 are output.
[0020]
The transfer amounts Trs0 and Trs1 are transfer amounts of the data Dat0 and Dat1 transferred by the transfer arbitration circuit 2 in response to one request signal Req0 and Req1, and are indicated by the size of the address of the storage device 1. For example, if the value of the transfer amount Trs0 is “8”, the transfer arbitration circuit 2 outputs data Dat0 for eight addresses of the storage device 1 to the buffer 3a in one transfer.
[0021]
In addition, there is a round robin as a distribution method that does not concentrate data access on resources with high priority.
The buffers 3a and 3b are provided in each of the resources 7a and 7b. The buffer 3a temporarily stores the data Dat0 transferred from the transfer arbitration circuit 2 and outputs it to the resource 7a. The buffer 3b temporarily stores the data Dat1 transferred from the transfer arbitration circuit 2, and outputs it to the resource 7b. The buffers 3a and 3b store and output data Dat0 and Dat1 by the FIFO method. The buffers 3a and 3b output empty sizes Siz0 and Siz1 indicating the size of the empty area to the transfer amount adjusting circuit 5 and the control circuits 6a and 6b.
[0022]
In the threshold registers 4a and 4b, thresholds Th0 and Th1 (values relating to the areas of the buffers 3a and 3b) for the transfer amount adjustment circuit 5 to compare with the empty sizes Siz0 and Siz1 of the buffers 3a and 3b are set.
[0023]
The transfer amount adjustment circuit 5 determines whether or not the empty sizes Siz0 and Siz1 are equal to or greater than the threshold values Th0 and Th1 set in the threshold registers 4a and 4b for each of the buffers 3a and 3b, and outputs the determination result to the transfer arbitration circuit 2. The transfer amount Trs0, Trs1 is increased or decreased. Specifically, when the empty size Siz0 of the buffer 3a is equal to or greater than the threshold Th0, the transfer amount adjustment circuit 5 increases the transfer amount Trs0. When the empty size Siz0 of the buffer 3a becomes a value smaller than the threshold value Th0 from a state where the threshold value Th0 is equal to or larger than the threshold value Th0, the transfer amount adjustment circuit 5 reduces the transfer amount Trs0 to a value before the increase. That is, when the empty sizes Siz0 and Siz1 of the buffers 3a and 3b are equal to or greater than the threshold values Th0 and Th1, the transfer amount adjustment circuit 5 increases the transfer amounts Trs1 and Trs1 of the data Dat0 and Dat1 of the transfer arbitration circuit 2, and the buffer 3a. , 3b so that the empty sizes Siz0 and Siz1 become smaller.
[0024]
FIG. 2 is a specific circuit diagram of the transfer amount adjustment circuit of FIG. As shown in the figure, the transfer amount adjustment circuit 5 includes subtraction circuits 11a and 11b, negative detection circuits 12a and 12b, and selection circuits 13a and 13b.
[0025]
A threshold value Th0 and an empty size Siz0 are input to the subtraction circuit 11a. The subtraction circuit 11a subtracts the empty size Siz0 from the threshold Th0 and outputs the result to the negative detection circuit 12a. The threshold value Th1 and the empty size Siz1 are input to the subtraction circuit 11b. Similarly to the subtraction circuit 11a, the subtraction circuit 11b subtracts the empty size Siz1 from the threshold Th1, and outputs the result to the negative detection circuit 12b.
[0026]
The negative detection circuits 12a and 12b detect whether the subtraction results output from the subtraction circuits 11a and 11b are positive or negative and output them to the selection circuits 13a and 13b.
Values “8” and “16” that become the transfer amount Trs0 are input to the selection circuit 13a. The selection circuit 13a selects the input “8” and “16” according to the detection result of the negative detection circuit 12a, and outputs it as the transfer amount Trs0. Specifically, when a negative detection result is output from the negative detection circuit 12a, that is, when the empty size Siz0 of the buffer 3a is greater than or equal to the threshold Th0, the selection circuit 13a outputs '16' as the transfer amount Trs0. . When a positive detection result is output from the negative detection circuit 12a, that is, when the empty size Siz0 of the buffer 3a is smaller than the threshold value Th0, the selection circuit 13a outputs “8” as the transfer amount Trs0.
[0027]
Returning to the description of FIG. The control circuits 6a and 6b output request signals Req0 and Req1 for requesting transfer of the data Dat0 and Dat1 to the transfer arbitration circuit 2. The control circuits 6a and 6b recognize that the data Dat0 and Dat1 are transferred to the buffers 3a and 3b by receiving the response signals Ack0 and Ack1.
[0028]
The control circuits 6a and 6b output request signals Req0 and Req1 according to the sizes of the empty sizes Siz0 and Siz1 of the buffers 3a and 3b. For example, when the empty sizes Siz0 and Siz1 become larger than a predetermined value, request signals Req0 and Req1 are output. Alternatively, the control circuits 6a and 6b may output the request signals Req0 and Req1 at regular intervals.
[0029]
The resources 7a and 7b perform pipeline processing on the shared data Dat0 and Dat1. Data Dat0 and Dat1 stored in the storage device 1 are temporarily stored in the buffers 3a and 3b, and the resources 7a and 7b receive the data Dat0 and Dat1 temporarily stored in the buffers 3a and 3b and perform processing.
[0030]
Hereinafter, the operation of FIG. 1 will be described with reference to a timing chart. In FIG. 1, it is assumed that the transfer priority of the resource 7a is higher than that of the resource 7b. FIG. 3 is a timing chart for explaining the operation of the data transfer apparatus of FIG. “1Ah” (h: indicating a hexadecimal number) of Th0 shown in FIG. 3 indicates a value set in the threshold register 4a. Req0 and Ack0 indicate timing waveforms of the request signal Req0 and the response signal Ack0. “18h”, “19h”,..., “0Eh” of Siz0 indicate changes in the empty size Siz0 of the buffer 3a. Trs0 indicates a change in the transfer amount Trs0 of the data Dat0.
[0031]
As shown in FIG. 3, the buffer 3a outputs the temporarily stored data Dat0 to the resource 7a one by one. Therefore, the empty size Siz0 of the buffer 3a is incremented by 1 as “18h”, “19h”,.
[0032]
The empty size Siz0 of the buffer 3a is output to the transfer amount adjustment circuit 5. The transfer amount adjustment circuit 5 determines whether or not the empty size Siz0 of the buffer 3a is equal to or greater than the threshold value Th0 set in the threshold value register 4a.
[0033]
The threshold value Th0 set in the threshold value register 4a is “1Ah” as shown in FIG. Accordingly, when the empty size Siz0 becomes “1Ah” or more, the transfer amount adjustment circuit 5 increases the transfer amount Trs0 from “8” (transfer for 8 addresses) to “16” (transfer for 16 addresses).
[0034]
Assume that the control circuits 6a and 6b output request signals Req0 and Req1 to the transfer arbitration circuit 2. The transfer arbitration circuit 2 receives the request signals Req0 and Req1, determines the priority of the resources 7a and 7b, and outputs response signals Ack0 and Ack1. Here, since it is assumed that the priority of the resource 7a is high, the transfer arbitration circuit 2 outputs a response signal Ack0 as shown in FIG. 3 to the control circuit 6a of the transfer CH0 corresponding to the resource 7a. Then, the transfer arbitration circuit 2 outputs the data Dat0 to the buffer 3a according to the transfer amount Trs0.
[0035]
The transfer amount Trs0 at this time is “16” as shown in FIG. Therefore, the transfer arbitration circuit 2 outputs data Dat0 for 16 addresses of the storage device 1 to the buffer 3a.
[0036]
In the buffer 3a, when the data Dat0 for 16 addresses is transferred from the storage device 1, the empty size Siz0 is changed from '1Ch' to '0Dh'. The transfer amount adjustment circuit 5 outputs the transfer amount Trs0 of “8” because the empty size Siz0 has become “0Ch” which is smaller than the threshold value Th0 of “1Ah”.
[0037]
Similarly, also in the transfer CH1, the transfer amount adjustment circuit 5 increases or decreases the transfer amount Trs1 depending on whether or not the empty size Siz1 of the buffer 3b has reached the threshold Th1. When the control circuit 6b outputs the request signal Req1 and the response signal Ack1 returns, the data Dat1 of the transfer amount Trs1 is transferred to the buffer 3b.
[0038]
Thus, the resources 7a and 7b from the storage device 1 depend on whether or not the empty sizes Siz0 and Siz1 of the buffers 3a and 3b provided in the resources 7a and 7b are equal to or greater than the thresholds Th0 and Th1 set in the threshold registers 4a and 4b. The transfer amounts Trs0 and Trs1 of the data Dat0 and Dat1 to be transferred to are increased or decreased. Thereby, the efficiency of data transfer from the storage device 1 to the resources 7a and 7b can be increased.
[0039]
In the above description, the transfer amounts Trs0 and Trs1 are increased or decreased depending on whether or not the empty sizes Siz0 and Siz1 of the buffers 3a and 3b are equal to or larger than the threshold values Th0 and Th1, but the data temporarily stored in the buffers 3a and 3b. The transfer amounts Trs0 and Trs1 may be increased or decreased depending on whether or not Dat0 and Dat1 are equal to or greater than the values set in the threshold registers 4a and 4b.
[0040]
In addition, when the transfer amount Trs0 of the resource 7a with a high priority increases, the transfer amount Trs1 of the resource 7b with a low priority can be prevented from increasing, thereby improving the data transfer efficiency. FIG. 4 is another example of a circuit diagram of the transfer amount adjustment circuit. 3, the detection results of the negative detection circuits 12a and 12b shown in FIG. 2 are ANDed by the AND circuit 14 and output to the selection circuit 13b. For example, in FIG. 3, when both the negative detection circuits 12a and 12b output an H state indicating a negative detection result, the AND circuit 14 outputs an L state. The selection circuit 13a outputs “16” as the transfer amount Trs0 from the H state of the negative detection circuit 12a, and the selection circuit 13b outputs “8” as the transfer amount Trs1 from the L state of the AND circuit 14. In this way, the transfer amount Trs1 of the resource 7b with low priority is not increased.
[0041]
Note that the number of resources may be two or more. In this case, it is only necessary to provide the transfer CH0, CH1,... Of FIG.
Next, a second embodiment of the present invention will be described. FIG. 5 is a circuit diagram of a data transfer apparatus according to the second embodiment. As shown in the figure, the data transfer device includes a storage device 21, a transfer arbitration circuit 22, buffers 23a and 23b, threshold registers 24aa and 24ba, transfer UP mask registers 24ab and 24bb, transfer DN request registers 24ac and 24bc, transfer amount adjustment. A circuit 25, control circuits 26a and 26b, and resources 27a and 27b are included. The transfer CH0 shown in the drawing represents a collection of circuits for transferring data Dat0 to the resource 27a, and includes a buffer 23a, a threshold register 24aa, a transfer UP mask register 24ab, a transfer DN request register 24ac, and a control circuit 26a. Yes. The transfer CH1 indicates a collection of circuits for transferring the data Dat1 to the resource 27b, and includes a buffer 23b, a threshold register 24ba, a transfer UP mask register 24bb, a transfer DN request register 24bc, and a control circuit 26b. 5, the storage device 21, the transfer arbitration circuit 22, the buffers 23a and 23b, the control circuits 26a and 26b, and the resources 27a and 27b are the same as the storage device 1, the transfer arbitration circuit 2, the buffer 3a, 3b, the control circuits 6a and 6b, and the resources 7a and 7b are the same as those in FIG.
[0042]
In the threshold registers 24aa and 24ba, thresholds Th0 and Th1 relating to the areas of the buffers 23a and 23b are set for the transfer amount adjustment circuit 25 to compare with the empty sizes Siz0 and Siz1 of the buffers 23a and 23b. In the transfer UP mask registers 24ab and 24bb, UP mask values Mask0 and Mask1 relating to the areas of the buffers 23a and 23b are set for the transfer amount adjustment circuit 25 to compare with the empty sizes Siz0 and Siz1 of the buffers 23a and 23b. . In the transfer DN request registers 24ac and 24bc, the DN request values Reqdn0 and Reqdn1 relating to the areas of the buffers 23a and 23b are set for the transfer amount adjustment circuit 25 to compare with the empty sizes Siz0 and Siz1 of the buffers 23a and 23b. . There is a relationship of threshold Th0 <UP mask value Mask0 <DN required value Reqdn0 and threshold Th1 <UP mask value Mask1 <DN required value Reqdn1.
[0043]
The transfer amount adjustment circuit 25 determines whether or not the empty sizes Siz0 and Siz1 are equal to or larger than the threshold values Th0 and Th1 for each of the buffers 23a and 23b, and increases or decreases the transfer amounts Trs0 and Trs1. Specifically, when the empty size Siz0 of the buffer 23a is equal to or greater than the threshold value Th0, the transfer amount adjustment circuit 25 increases the transfer amount Trs0. When the empty size Siz0 of the buffer 23a becomes a value smaller than the threshold value Th0 from a state where the threshold value Th0 is equal to or larger than the threshold value Th0, the transfer amount adjustment circuit 25 reduces the transfer amount Trs0 to a value before the increase. That is, when the empty sizes Siz0 and Siz1 of the buffers 23a and 23b are equal to or greater than the threshold values Th0 and Th1, the transfer amount adjustment circuit 25 increases the transfer amounts Trs1 and Trs0 of the data Dat0 and Dat1 of the transfer arbitration circuit 22, and the buffer 23a , 23b so that the empty sizes Siz0 and Siz1 become smaller.
[0044]
Further, the transfer amount adjustment circuit 25 determines whether or not the empty sizes Siz0 and Siz1 are equal to or larger than the UP mask values Mask0 and Mask1 for each of the buffers 23a and 23b, and the data Dat0 and Dat1 in the resources 27a and 27b with low priority. Transfer amount Trs0, Trs1 is not increased (not changed (increased / decreased)). Specifically, when the priority of data transfer of the resource 27a is higher than that of the resource 27b, when the empty size Siz0 of the buffer 23a is equal to or greater than the UP mask value Mask0, the empty size Siz1 of the buffer 23a is equal to or greater than the threshold Th1. However, the transfer amount Trs1 is not increased. That is, when the empty sizes Siz0 and Siz1 of the buffers 23a and 23b in the resources 27a and 27b with high priority become equal to or larger than the UP mask values Mask0 and Mask1, the data Dat0 and Dat1 of the other resources 27a and 27b with low priority The transfer amounts Trs0 and Trs1 are not increased.
[0045]
Further, the transfer amount adjustment circuit 25 determines whether or not the empty sizes Siz0 and Siz1 are greater than or equal to the DN request values Reqdn0 and Reqdn1 for each of the buffers 23a and 23b, and the data Dat0 and Dat1 in the resources 27a and 27b with low priority. Transfer amount Trs0, Trs1 is reduced. Specifically, when the priority of data transfer of the resource 27a is higher than that of the resource 27b, when the empty size Siz0 of the buffer 23a is equal to or greater than the DN request value Reqdn0, the transfer amount Trs1 in the resource 27b of low priority is reduced. . That is, when the empty sizes Siz0 and Siz1 of the buffers 23a and 23b in the resources 27a and 27b with high priority become equal to or greater than the DN request values Reqdn0 and Reqdn1, the data Dat0 and Dat1 of the other resources 27a and 27b with low priority Transfer amount Trs0, Trs1 is reduced.
[0046]
As described above, there is a relationship of threshold Th0 <UP mask value Mask0 and threshold Th1 <UP mask value Mask1. Therefore, when the empty size of the high priority resource buffer is larger than the threshold and larger than the UP mask value, an increase in the transfer amount to the buffer in the low priority resource is prohibited. In other words, the data transfer time of a resource with a low priority is suppressed, and the amount of data transferred to a resource with a high priority is allocated as much as the transfer time is suppressed, and the data transfer efficiency from the storage device to the resource is further increased.
[0047]
Further, there is a relationship of UP mask value Mask0 <DN request value Reqdn0 and UP mask value Mask1 <DN request value Reqdn0. Therefore, when the empty size of the high priority resource buffer is larger than the UP mask value and further larger than the DN request value, the transfer amount to the buffer in the low priority resource is reduced. That is, the transfer time of a resource with a low priority is reduced, and the transfer time is reduced, so that data transfer to a resource with a high priority is allocated, and the data transfer efficiency from the storage device to the resource is further increased.
[0048]
Hereinafter, the operation of FIG. 5 will be described using a timing chart. In FIG. 5, it is assumed that the transfer priority of the resource 27a is higher than that of the resource 27b. Further, it is assumed that “1Ah” is set as the threshold Th0 in the threshold register 24aa. It is assumed that “1Eh” is set as the UP mask value Mask0 in the transfer UP mask register 24ab. In the transfer DN request register 24ac, “20h” is set as the DN request value Reqdn0. It is assumed that “4Ah” is set as the threshold Th1 in the threshold register 24ba. It is assumed that “4Eh” is set in the transfer UP mask register 24bb as the UP mask value Mask1.
[0049]
FIG. 6 is a timing chart for explaining the operation of the data transfer apparatus of FIG. As shown in the figure, “18h”, “19h”,... Of Siz0 indicate changes in the empty size Siz0 of the buffer 23a. The transfer UP0 indicates the timing when the empty size Siz0 is equal to or greater than the threshold Th0. Trs0 indicates the transfer amount Trs0 of the data Dat0 that the transfer amount adjustment circuit 25 instructs the transfer arbitration circuit 22. Also, “43h”, “44h”,... Of Siz1 indicate changes in the empty size Siz1 of the buffer 23b. The transfer UP1 indicates the timing when the empty size Siz1 becomes equal to or greater than the UP mask value Mask1. The transfer DN1 shows the timing when the empty size Siz0 becomes larger than the DN request value Reqdn1. Trs1 indicates the transfer amount Trs0 of the data Dat1 that the transfer amount adjustment circuit 25 instructs the transfer arbitration circuit 22.
[0050]
As shown in FIG. 6, when the empty size Siz0 of the buffer 3a is equal to or greater than “1Ah” which is the threshold Th0, the transfer amount adjustment circuit 25 changes the transfer amount Trs0 from “8” (transfer for 8 addresses) to “16”. (Transfer for 16 addresses). Therefore, the transfer arbitration circuit 22 transfers 16 addresses of the storage device 21 when transferring the data Dat0.
[0051]
When the empty size Siz0 of the buffer 3a becomes equal to or larger than “1Eh” that is the UP mask value Mask0, the transfer amount adjustment circuit 25 transfers even if the empty size Siz1 of the buffer 3b becomes equal to or larger than “4Ah” that is the threshold Th1. Do not increase the amount Trs1.
[0052]
When the empty size Siz0 of the buffer 3a becomes equal to or greater than “20h” which is the DN request value Reqdn0, the transfer amount adjustment circuit 25 transfers the transfer amount Trs1 from “8” (transfer of 8 addresses) to “4” (transfer of 4 addresses). ). Therefore, the transfer arbitration circuit 22 transfers eight addresses of the storage device 21 when transferring the data Dat1.
[0053]
As described above, the resources 27a and 27b from the storage device 21 depend on whether or not the empty sizes Siz0 and Siz1 of the buffers 23a and 23b provided in the resources 27a and 27b are equal to or greater than the threshold values Th0 and Th1 set in the threshold registers 24aa and 24ba. The transfer amounts Trs0 and Trs1 of the data Dat0 and Dat1 to be transferred to are increased or decreased. Thereby, the transfer efficiency of the data from the storage device 21 to the resources 27a and 27b can be increased.
[0054]
Further, when the empty sizes Siz0 and Siz1 of the buffers 23a and 23b are further increased and become equal to or higher than the UP mask values Mask0 and Mask1 set in the transfer UP mask registers 24ab and 24bb, the data Dat0, The transfer amounts Trs0 and Trs1 of Dat1 are not increased (changed). Thereby, since the transfer time of the resource with low priority is suppressed, it is allocated to data transfer to the resource with high priority, and the transfer efficiency of data from the storage device 21 to the resources 27a and 27b can be improved.
[0055]
Further, when the empty sizes Siz0 and Siz1 of the buffers 23a and 23b become larger and become equal to or larger than the DN request values Reqdn0 and Reqdn1 set in the transfer DN request registers 24ac and 24bc, the data Dat0 and Dat1 in the resources 27a and 27b with low priority The transfer amount Trs0, Trs1 is reduced. Thereby, since the transfer time of the low priority resource is reduced, it is allocated to the data transfer to the high priority resource, and the data transfer efficiency from the storage device 21 to the resources 27a and 27b can be increased. .
[0056]
The threshold value Th0 may be the UP mask value Mask0, and the threshold value Th1 may be the UP mask value Mask1. That is, whether or not to increase (change) the transfer amounts Trs0 and Trs1 is determined based on the thresholds Th0 and Th1 set in the threshold registers 24aa and 24bb. As a result, the transfer UP mask registers 24ab and 24bb become unnecessary, and the cost can be reduced.
[0057]
Further, the threshold value Th0 may be the DN request value Reqdn0, and the threshold value Th1 may be the DN request value Reqdn1. That is, it is determined whether or not to reduce the transfer amounts Trs0 and Trs1 based on the thresholds Th0 and Th1 set in the threshold registers 24aa and 24bb. As a result, the transfer DN request registers 24ab and 24bb become unnecessary, and the cost can be reduced.
[0058]
In addition, a plurality of threshold registers 24aa and 24ba are provided, and the plurality of thresholds are compared with the empty sizes Siz0 and Siz1, and each time the empty sizes Siz0 and Siz1 exceed the plurality of thresholds, the transfer amount is gradually increased. Trs0 and Trs1 may be increased or decreased. Thereby, the transfer efficiency of the data from the storage device 21 to the resources 27a and 27b can be further increased.
[0059]
Further, each of the threshold registers 24aa and 24ba, the transfer UP mask registers 24ab and 24bb, and the transfer DN request registers 24ac and 24bc is made one, and each buffer 23a, You may make it compare with empty size Siz0 and Siz1 of 23b. That is, by sharing the threshold value, the UP mask value, and the DN request value in each buffer, only one threshold value register, transfer UP mask register, and transfer DN request register are required, and the cost can be reduced.
[0060]
Further, the operation of the transfer amount adjustment circuit 25 is activated when data is transferred with high transfer efficiency by a control device such as a CPU, for example, and is deactivated when it is not necessary to transfer data with high transfer efficiency. Thus, power consumption can be reduced.
[0061]
Note that the number of resources may be two or more. In this case, it is only necessary to provide the transfer CH0, CH1,... Of FIG.
Next, a third embodiment of the present invention will be described. FIG. 7 is a circuit diagram of a data transfer apparatus according to the third embodiment. As shown in the figure, the data transfer device includes a storage device 31, a transfer arbitration circuit 32, buffers 33a and 33b, transfer amount adjustment circuits 34a and 34b, control circuits 35a and 35b, and resources 36a and 36b. The transfer CH0 shown in the figure represents a collection of circuits for transferring the data Dat0 to the resource 36a, and includes a buffer 33a and a control circuit 35a. The transfer CH1 indicates a collection of circuits for transferring the data Dat1 to the resource 36b, and includes a buffer 33b and a control circuit 35b. Note that the storage device 31, the transfer arbitration circuit 32, the buffers 33a and 33b, the control circuits 35a and 35b, and the resources 36a and 36b illustrated in FIG. 7 are the same as the storage device 1, the transfer arbitration circuit 2, the buffer 3a, and the like illustrated in FIG. 3b, the control circuits 6a and 6b, and the resources 7a and 7b are the same as those in FIG.
[0062]
In the third embodiment, the transfer amount adjustment circuits 34a and 34b store the past empty sizes Siz0 and Siz1 of the buffers 33a and 33b, and the next data is based on the statistics of the stored empty sizes Siz0 and Siz1. The empty sizes Siz0 and Siz1 of the buffers 33a and 33b when Dat0 and Dat1 are transferred are predicted. Then, the transfer amount adjustment circuits 34a and 34b increase or decrease the transfer amounts Trs0 and Trs1 based on the predicted empty sizes Siz0 and Siz1.
[0063]
The transfer amount adjustment circuit 34a calculates the difference between the empty size Siz0 of the buffer 33a when the previous data Dat0 was transferred and the empty size Siz0 of the buffer 33a when the current data Dat0 was transferred. The data is stored in a built-in storage device. The transfer amount adjustment circuit 34a increases or decreases the transfer amount Trs0 by predicting an empty area of the buffer when data is transferred next time from the stored gradient of the past difference. Similarly to the transfer amount adjustment circuit 34a, the transfer amount adjustment circuit 34b predicts the empty size Siz1 of the buffer 33b and increases or decreases the transfer amount Trs1. FIG. 8 is a circuit diagram of the transfer amount adjustment circuit. As shown in the figure, the transfer amount adjustment circuit 34 a includes a latch circuit 41, a difference circuit 42, a storage device 43, an inclination prediction circuit 44, and a control circuit 45.
[0064]
The latch circuit 41 receives an empty size Siz0 and a response signal Ack0. When the response signal Ack0 is input, the latch circuit 41 outputs the stored empty size Siz0 at the previous transfer to the difference circuit 42, and stores the currently input empty size Siz0.
[0065]
The difference circuit 42 receives the current empty size Siz0 and the previous empty size Siz0 held in the latch circuit 41. The difference circuit 42 takes the difference between the input current empty size Siz0 and the previous empty size Siz0 and stores it in the storage device 43.
[0066]
The storage device 43 stores the difference value of the empty size Siz0 output from the difference circuit 42 for a plurality of times. The storage device 43 stores the difference value of the empty size Siz0 output from the difference circuit 42 in synchronization with the response signal Ack0. Further, the storage device 43 outputs the stored difference value of the empty size Siz0 to the inclination prediction circuit 44 in accordance with an instruction from the control circuit 45.
[0067]
The inclination prediction circuit 44 predicts the empty size Siz0 of the buffer 33a when the next data Dat0 transfer is performed according to the inclination of the difference value of the empty size Siz0 stored in the storage device 43. FIG. 9 is a graph of the difference value of the empty size stored in the storage device. The horizontal axis of the graph shown in the figure represents time, and the vertical axis represents the difference value of the empty size Siz0. Also, “◯” shown in the figure is the difference value of the empty size Siz0 stored in the storage device 43. In the figure, the difference value of the empty size Siz0 becomes the past as '◯' goes to the right.
[0068]
In FIG. 9, the difference value of the empty size Siz0 tends to increase. The inclination prediction circuit 44 predicts that the empty size Siz0 of the buffer 33a when the data Dat0 is transferred next time increases according to the inclination of the increase in the difference value of the empty size stored in the storage device 43. To do.
[0069]
The control circuit 45 increases or decreases the transfer amount Trs0 of the data Dat0 based on the prediction of the empty size Siz0 of the buffer 33a by the inclination prediction circuit 44. A response signal Ack0 is input to the control circuit 45, and the transfer amount Trs0 is increased or decreased in synchronization with the response signal Ack0.
[0070]
In FIG. 9, since the slope prediction circuit 44 predicts that the empty size Siz0 of the buffer 33a increases, the control circuit 45 increases the transfer amount of the data Dat0.
[0071]
The transfer amount adjustment circuit 34b has the same configuration as the transfer amount adjustment circuit 34a shown in FIG. 8, and a description thereof will be omitted.
Hereinafter, the operation of FIG. 7 will be described. In FIG. 7, it is assumed that the transfer priority of the resource 36a is greater than that of the resource 36b. It is assumed that the control circuits 35a and 35b output request signals Req0 and Req1 to the transfer arbitration circuit 32. The transfer arbitration circuit 32 receives the request signals Req0 and Req1, and determines the priority of the resources 36a and 36b. Here, since the priority of the resource 36a is high, the transfer arbitration circuit 32 outputs the response signal Ack0 to the control circuit 35a. Then, the transfer arbitration circuit 32 outputs data Dat0 to the buffer 33a in accordance with the transfer amount Trs0 output from the transfer amount adjustment circuit 34a.
[0072]
Upon receiving the response signal Ack0, the transfer amount adjustment circuit 34a takes the difference between the current empty size Siz0 output from the buffer 33a and the empty size Siz0 of the buffer 33a in the previous transfer, as shown in FIG. In addition, the difference value of the empty size Siz0 is stored in the storage device 43.
[0073]
The inclination prediction circuit 44 of the transfer amount adjustment circuit 34a predicts the empty size Siz0 of the buffer 33a when the next data Dat0 is transferred from the inclination of the difference value of the empty size Siz0 stored in the storage device 43. The control circuit 45 of the transfer amount adjustment circuit 34a increases the transfer amount Trs0 if the slope prediction circuit 44 predicts that the empty size Siz0 is increased, and decreases the transfer amount Trs0 if it is predicted to decrease.
[0074]
As described above, the past empty sizes Siz0 and Siz1 are stored in the buffers 33a and 33b, and the buffers 33a and 33b when the data Dat0 and Dat1 are next transferred are based on the statistics of the stored empty sizes Siz0 and Siz1. The amount of transfer was increased / decreased by predicting the free space. Thereby, the transfer efficiency of the data from the storage device 31 to the resources 36a and 36b can be increased.
[0075]
The operation of the transfer amount adjustment circuits 34a and 34b is activated when data is transferred with high transfer efficiency by a control device such as a CPU, for example, and is deactivated when transfer with high transfer efficiency is not required. By doing so, power consumption can be reduced.
[0076]
Further, the number of resources may be two or more, and in this case, it is only necessary to provide the transfer CH0, CH1,... Of FIG.
Next, a fourth embodiment of the present invention will be described. FIG. 10 is a circuit diagram of a data transfer apparatus according to the fourth embodiment. As shown in the figure, the data transfer device includes a storage device 51, a transfer arbitration circuit 52, buffers 53a and 53b, transfer amount adjustment circuits 54a and 54b, an inter-CH arbitration circuit 55, control circuits 56a and 56b, and resources 57a and 57b. have. The transfer CH0 shown in the figure represents a collection of circuits for transferring the data Dat0 to the resource 57a, and includes a buffer 53a and a control circuit 56a. The transfer CH1 indicates a collection of circuits for transferring the data Dat1 to the resource 57b, and includes a buffer 53b and a control circuit 56b. Note that the storage device 51, the buffers 53a and 53b, the control circuits 56a and 56b, and the resources 57a and 57b shown in FIG. 10 are the storage device 31, the buffers 33a and 33b, the control circuits 35a and 35b, and the resources shown in FIG. This is the same as 36a and 36b, and a description thereof is omitted.
[0077]
In the fourth embodiment, the inter-CH arbitration circuit 55 changes the priority of the resources 57a and 57b. The inter-CH arbitration circuit 55 adds and subtracts the priority calculated by the transfer amount adjustment circuits 54a and 54b from the preset fixed priority of the resources 57a and 57b to thereby give the priority of the resources 57a and 57b. change.
[0078]
The transfer amount adjustment circuits 54a and 54b have the same functions as the transfer amount adjustment circuits 34a and 34b in FIG. 7, and the priority level is adjusted according to the difference between the empty sizes Siz0 and Siz1 of the buffers 53a and 53b. It has the function to calculate. For example, the transfer amount adjustment circuit 54a predicts that the empty size Siz0 of the buffer 53a will increase if the slope of the difference value of the empty size Siz0 increases, and gives a predetermined priority to the fixed priority of the resource 57a. Add degrees.
[0079]
The transfer arbitration circuit 52 determines the resources 57 a and 57 b to be transferred based on the priority of the inter-CH arbitration circuit 55.
Further, the inter-CH arbitration circuit 55 increases the transfer amounts Trs0 and Trs1 of the data Dat0 and Dat1 in the resources 57a and 57b when the priority of the resources 57a and 57b is equal to or higher than the set predetermined value. Also, a plurality of set predetermined values are provided, and the inter-CH arbitration circuit 55 gradually transfers the transfer amounts Trs0, Trs1 each time the priority of the resources 57a, 57b becomes equal to or higher than the predetermined values provided. Increase.
[0080]
Hereinafter, the operation of FIG. 10 will be described. It is assumed that the transfer amount Trs0 is not increased unless the priority of the resource 57a becomes “3” or higher. The transfer amount Trs0 can be increased up to eight addresses of the storage device 51 when the priority of the resource 57a is “4” or more. Furthermore, the transfer amount Trs0 can be increased to 10 addresses of the storage device 51 when the priority of the resource 57a is '5' or more.
[0081]
The inter-CH arbitration circuit 55 adds and subtracts the priority calculated by the transfer amount adjustment circuits 54a and 54b to the preset fixed priority of the resources 57a and 57b.
[0082]
The inter-CH arbitration circuit 55 prevents the transfer amount Trs0 output from the transfer amount adjustment circuit 54a from increasing if the priority of the added and subtracted resource 57a is “1” to “3”.
[0083]
The inter-CH arbitration circuit 55 can increase the transfer amount Trs0 output from the transfer amount adjustment circuit 54a up to eight addresses of the storage device 51 if the priority of the resource 57a is changed to “4” or more.
[0084]
The inter-CH arbitration circuit 55 can increase the transfer amount Trs0 output from the transfer amount adjustment circuit 54a to 10 addresses of the storage device 51 when the priority of the resource 57a is changed to “5” or more.
[0085]
As described above, the priority of the resources 57a and 57b is changed by the inter-CH arbitration circuit 55, and the increase / decrease width of the transfer amounts Trs0 and Trs1 is changed by stepping the priority to a predetermined value. . Thereby, the transfer efficiency of the data from the storage device 51 to the resources 57a and 57b can be increased.
[0086]
The operation of the transfer amount adjustment circuits 54a and 54b is activated when data is transferred with high transfer efficiency by a control device such as a CPU, for example, and is deactivated when transfer with high transfer efficiency is not required. By doing so, power consumption can be reduced.
[0087]
Further, the number of resources may be two or more, and in this case, it is only necessary to provide the transfer CH0, CH1,... Of FIG.
(Supplementary Note 1) In a data transfer apparatus that arbitrates data transfer,
A storage device for storing data shared by a plurality of resources;
A transfer arbitration circuit that transfers the data according to a transfer amount indicated by the resource having a high transfer priority;
A buffer provided for each resource and temporarily storing and outputting the data transferred from the transfer arbitration circuit;
A threshold value register in which a threshold value related to the area for each buffer is set;
A transfer amount adjustment circuit that increases or decreases the transfer amount depending on whether or not the free space for each buffer reaches the threshold;
A data transfer device comprising:
[0088]
(Supplementary note 2) The data transfer device according to supplementary note 1, wherein the transfer amount adjustment circuit increases or decreases the transfer amount depending on whether or not the data temporarily stored for each buffer reaches the threshold value. .
[0089]
(Additional remark 3) It has further the increase / decrease prohibition register in which the transfer amount increase / decrease prohibition threshold is set,
The transfer amount adjustment circuit does not increase or decrease the transfer amount in the resource having a lower transfer priority when an empty area for each buffer reaches the transfer amount increase / decrease prohibition threshold. Data transfer device.
[0090]
(Additional remark 4) It further has a reduction request register in which a transfer amount reduction request threshold is set,
The transfer amount adjusting circuit according to claim 1, wherein the transfer amount adjustment circuit reduces the transfer amount in the resource having a lower transfer priority when an empty area for each buffer reaches the transfer amount reduction request threshold. Data transfer device.
[0091]
(Additional remark 5) The said transfer amount adjustment circuit does not increase / decrease the said transfer amount in the said other resource with low transfer priority, when the vacant area for every said buffer reaches the said threshold value Data transfer device.
[0092]
(Supplementary note 6) The transfer amount adjustment circuit reduces the transfer amount in another resource having a low transfer priority when an empty area for each buffer reaches the threshold value. Data transfer device.
[0093]
(Supplementary note 7) A plurality of the thresholds are set in the threshold register,
2. The data transfer apparatus according to claim 1, wherein the transfer amount adjustment circuit increases or decreases the transfer amount step by step each time the free area reaches the plurality of threshold values.
[0094]
(Supplementary note 8) The data transfer device according to supplementary note 1, wherein the transfer amount adjustment circuit is activated and deactivated by a selection signal.
(Supplementary note 9) The data transfer device according to supplementary note 1, wherein the threshold value is common to all free areas of the buffer.
[0095]
(Supplementary note 10) The data transfer device according to supplementary note 3, wherein the transfer amount increase / decrease prohibition threshold is common to all free areas of the buffer.
(Supplementary note 11) The data transfer device according to supplementary note 4, wherein the transfer amount reduction request threshold value is common to all free areas of the buffer.
[0096]
(Supplementary Note 12) In a data transfer apparatus that arbitrates data transfer,
A storage device for storing data shared by a plurality of resources;
A transfer arbitration circuit that transfers the data according to a transfer amount indicated by the resource having a high transfer priority;
A buffer provided for each resource and temporarily storing and outputting the data transferred from the transfer arbitration circuit;
A transfer that stores a past free area for each buffer, predicts a free area for each buffer when the data is next transferred based on statistics of the past free area, and increases or decreases the transfer amount A quantity adjustment circuit;
A data transfer device comprising:
[0097]
(Additional remark 13) The said transfer amount adjustment circuit memorize | stores the difference of the present empty area | region and the empty area | region when the said data transfer was performed last time, and the said data is next from the inclination of the said stored difference. 13. The data transfer device according to appendix 12, wherein an empty area for each of the buffers when the data is transferred is predicted.
[0098]
(Supplementary note 14) The data transfer device according to supplementary note 12, further comprising an inter-transfer arbitration circuit that changes transfer priorities of the plurality of resources based on an empty area for each of the buffers.
[0099]
(Supplementary note 15) The data transfer device according to supplementary note 14, wherein the transfer amount adjustment circuit increases or decreases the transfer amount based on the changed transfer priority.
(Supplementary note 16) The data transfer device according to supplementary note 12, wherein the transfer amount adjustment circuit is activated and deactivated by a selection signal.
[0100]
【The invention's effect】
As described above, according to the present invention, the transfer amount of data transferred from the storage device to the resource is increased or decreased depending on whether or not the free area of the buffer provided for each of the resources has reached the threshold set in the threshold register. Like When the free space for each buffer reaches the transfer amount increase prohibition threshold, increase of the transfer amount in other low transfer priority resources is prohibited, and when the transfer amount decrease request threshold is reached, Reduce the amount of transfer for resources with low transfer priority. It was. This Without drastically reducing the data transfer efficiency of low priority resources, Data transfer efficiency from the storage device to a plurality of resources can be increased.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a data transfer apparatus according to a first embodiment.
FIG. 2 is a specific circuit diagram of the transfer amount adjustment circuit of FIG. 1;
FIG. 3 is a timing chart for explaining the operation of the data transfer apparatus in FIG. 1;
FIG. 4 is another example of a circuit diagram of the transfer amount adjustment circuit.
FIG. 5 is a circuit diagram of a data transfer apparatus according to a second embodiment.
6 is a timing chart for explaining the operation of the data transfer apparatus in FIG. 5;
FIG. 7 is a circuit diagram of a data transfer apparatus according to a third embodiment.
FIG. 8 is a circuit diagram of a transfer amount adjustment circuit.
FIG. 9 is a graph of the difference value of the empty size stored in the storage device.
FIG. 10 is a circuit diagram of a data transfer apparatus according to a fourth embodiment.
FIG. 11 is a circuit diagram of a conventional data transfer device.
12 is a timing chart for explaining the operation of the data transfer apparatus of FIG.
[Explanation of symbols]
1, 21, 31, 43, 51 Storage device
2,22,32,52 Transfer arbitration circuit
3a, 3b, 23a, 23b, 33a, 33b, 53a, 53b buffer
4a, 4b, 24aa, 24ba threshold register
5, 25, 34a, 34b, 54a, 54b Transfer amount adjustment circuit
6a, 6b, 26a, 26b, 35a, 35b, 45, 56a, 56b Control circuit
7a, 7b, 27a, 27b, 36a, 36b, 57a, 57b Resources
24ab, 24bb transfer UP mask register
24ac, 24bc Transfer DN request register
41 Latch circuit
42 Difference circuit
44 Inclination prediction circuit
55 arbitration circuit between channels

Claims (3)

In a data transfer device that arbitrates data transfer,
A storage device for storing data shared by a plurality of resources;
A transfer arbitration circuit that transfers the data according to a transfer amount indicated by the resource having a high transfer priority;
A buffer provided for each resource and temporarily storing and outputting the data transferred from the transfer arbitration circuit;
A threshold value register in which a threshold value related to the area for each buffer is set;
An increase prohibition register in which a transfer amount increase prohibition threshold is set,
A reduction request register in which a transfer amount reduction request threshold is set;
The transfer amount is increased or decreased depending on whether or not the free area for each buffer has reached the threshold value. A transfer amount adjustment circuit for prohibiting an increase in the transfer amount in the low resource and reducing the transfer amount in the resource having a low transfer priority when the transfer amount reduction request threshold is reached;
A data transfer device comprising:   2. The data transfer apparatus according to claim 1, wherein the transfer amount adjustment circuit increases or decreases the transfer amount depending on whether or not the data temporarily stored for each buffer reaches the threshold value. A plurality of the thresholds are set in the threshold register,
2. The data transfer apparatus according to claim 1, wherein the transfer amount adjustment circuit increases or decreases the transfer amount step by step each time the free area reaches the plurality of threshold values.

Images