JP4067945B2 - Semiconductor integrated circuit, memory control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a storage control device including the semiconductor integrated circuit.
[0002]
[Prior art]
Many semiconductor integrated circuits (hereinafter referred to as “data transfer circuits”) that involve data transfer are used in computer systems, storage control devices, and the like. The data transfer circuit includes a data path unit that transfers a data signal through processes such as propagation, selection, and calculation of a data signal, and a control circuit that controls the operation of an element corresponding to the above-described process in the data path unit. It becomes the composition to provide. Since high reliability is required in data transfer circuits, equivalent circuits that perform logical operations of the same content are arranged to be duplicated, and are configured to switch to the other circuit immediately when one circuit fails. The
[0003]
In each data transfer circuit, a parity bit or an error correcting code such as a Hamming code or CRC (Cyclic Redundancy Code) is added to the data signal. A mechanism for detecting a failure such as a bit error occurring during data transfer using a parity bit or an error correction code added to the data signal is provided. However, in this mechanism, in the data transfer circuit, a failure in the control circuit itself, a failure in supplying a control signal from the control circuit to the data path unit, etc. (collectively these are referred to as “control system failure”) Cannot be detected.
[0004]
For example, in the conventional data transfer circuit 20 shown in FIG. 6, the fact that a failure of a clock enable signal (hereinafter referred to as a CE signal) supplied to the flip-flop 24 cannot be detected will be described with reference to a timing chart shown in FIG. To do.
[0005]
In FIG. 7, “1” (or “0”) bits included in the data signal (1 Byte) and the parity bit (1 bit) input to the flip-flop 24 are totaled over each clock cycle (T0 to T4 period). This number is based on the premise that the specified number is an even number (or odd number) (hereinafter, the relationship specified between the data signal (1 Byte) and the parity bit (1 bit). (Referred to as “parity relationship”).
[0006]
First, the operation of the conventional data transfer circuit 20 when the CE signal is normal will be described. The CE signal is switched from the L level to the H level in the period T1, and the clock signal supplied to the flip-flop 24 becomes valid. Then, the data signal t1 and the parity bit t1 input to the flip-flop 24 are held at the edge of the clock signal in the T1 period (FIG. 7: (A)).
[0007]
The retained data signal t1 and parity bit t1 are input in the period T2 to the parity checker 22 and the like that are the next stage of the flip-flop 24 (FIG. 7: (B)). The parity checker 22 performs a parity check in the T3 period using the data signal t1 and the parity bit t1 input in the T2 period. Here, since the parity relationship between the data signal t1 and the parity bit t1 is normal, the parity checker 22 sets the result of the parity check as “no error” and outputs an error detection signal (FIG. 7: ( C)).
[0008]
Next, the operation in the case where a failure occurs in the CE signal in the conventional data transfer circuit 20 will be described. In the T1 period, a failure is assumed in which the CE signal does not switch from the L level to the H level and maintains the L level state. In this case, since the clock signal supplied to the flip-flop 24 becomes invalid in the T1 period, the data signal t1 and the parity bit t1 are not held (FIG. 7: (D)).
[0009]
Therefore, the data signal t0 and the parity bit t0 held in the clock cycle before the T1 period are input to the parity checker 22 and the like subsequent to the flip-flop 24 in the T2 period (FIG. 7). : (E)). The parity checker 22 performs a parity check in the T3 period using the data signal t0 and the parity bit t0 input in the T2 period. Here, since the parity relationship between the data signal t0 and the parity bit t0 is normal, the parity checker 22 sets the parity check result to “no error” and outputs an error detection signal (FIG. 7: (F )).
[0010]
In this manner, the conventional data transfer circuit 20 has a disadvantage that the failure cannot be detected even when a failure occurs in the CE signal (FIG. 7: (F)). Therefore, in order to avoid such an inconvenience, one additional data transfer circuit having the same contents is arranged with respect to the positive data transfer circuit. Then, a mechanism called a “full duplex system” has been proposed in which the output signals of the primary and secondary data transfer circuits are compared and can be detected as a fault if there is a difference (see, for example, Patent Document 1).
[0011]
[Patent Document 1]
JP 2000-188553 A
[0012]
[Problems to be solved by the invention]
Here, for example, a configuration employing a full duplex system is proposed for the data transfer circuit 20 shown in FIG. 6 (see FIG. 8). With the configuration shown in FIG. 8, by comparing the output signals of the positive data path unit 21a and the sub data path unit 21b in the comparator 26, it is possible to detect the above-described fault in the control system. However, by adopting the full duplex system, the circuit having the same contents is further added, so that the circuit scale of the data transfer circuit is remarkably increased. As the circuit scale increases, the number of functions (blocks) accommodated on a board with a limited mounting area is reduced, leading to a reduction in processing capacity as a whole.
[0013]
In addition, with the recent advancement of semiconductor technology such as miniaturization, the control of the data transfer circuit has become complicated, and the amount of transferred data has increased accordingly. Here, the transfer data amount is determined by the product of the transfer bit rate (the number of transfer bits per unit time) and the data path width. Therefore, the data path width must be increased simultaneously with the transfer bit rate as the amount of transfer data increases. However, if the full duplex system is adopted, the circuit scale increases at an accelerated rate by increasing the data path width.
[0014]
The present invention has been made based on the above circumstances, and an object thereof is to provide a semiconductor integrated circuit and a storage control device including the semiconductor integrated circuit.
[0015]
[Means for Solving the Problems]
  The main present invention for solving the above problems is as follows.
  A first flip-flop capable of controlling the validity / invalidity of a clock signal used to hold data of the data signal based on a first clock enable signal when a data signal is input;
The parity bit added to the data signal is input in the same clock cycle as the data signal, and the validity / invalidity of the clock signal used to hold the data of the parity bit can be controlled based on the second clock enable signal. A second flip-flop;
A first control circuit for outputting the first clock enable signal to the first flip-flop;
A second control circuit for outputting the second clock enable signal to the second flip-flop;
The data signal held in the first flip-flop and the parity bit held by the second flip-flop are input in the same clock cycle and input in the same clock cycle. Parity check is performed using the data signal and the parity bit, and the result is output as an error detection signal indicating whether a failure of the first clock enable signal, the second clock enable signal or the data signal is detected. A parity checker to
  A semiconductor integrated circuit having
  Other features of the present invention will become apparent from the accompanying drawings and the description of this specification.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
=== Summary of disclosure ===
The following disclosure will reveal at least the following.
Here, the above-mentioned “semiconductor integrated circuit” is, for example, a “data transfer circuit” described later. The above-mentioned “first element” and “second element” are, for example, a “flip-flop” and a “selector circuit” to be described later. The above-mentioned “output circuit” is, for example, a “parity checker” described later. The “correspondence” between the data signal and the verification code is, for example, when the verification code is a parity bit, the data signal and the bit of “1” (or “0”) included in the parity bit are totaled. The relationship is such that the number is an even number (or an odd number).
[0017]
According to the present invention, the first element to which the data signal is input and the second element to which the verification code of the data signal is input are separated, and the operation of the first element and the operation of the second element are respectively performed. In a configuration with individual control circuits for independent control, for example, failure of the first or second control circuit or supply of control signals from the first or second control circuit to the first or second element A case is assumed where the operation controlled in the first or second element is not normally performed due to a failure or the like.
[0018]
In this case, when the data signal controlled by the first element is compared with the verification code controlled by the second element in the output circuit, the correspondence between the data signal and the verification code may not be established. Therefore, it is possible to detect the failure of the controlled operation in the first or second element, and the reliability of the semiconductor integrated circuit can be improved.
[0019]
Further, in the present invention, compared with the conventional semiconductor integrated circuit adopting the full duplex system, the first and second elements can be suppressed while preventing the circuit scale from increasing, for example, the first and second elements need not be duplexed. It is possible to detect a failure in the operation controlled by the element. Further, according to the present invention, the data path width can be increased, that is, the data transfer amount can be increased while suppressing an increase in circuit scale as compared with a conventional semiconductor integrated circuit adopting a full duplex system.
[0020]
As a second aspect of the present invention, the data signal and the verification code are input to the element in the same clock cycle, and the output circuit includes the data signal and the verification code controlled by the element. May be input in the same clock cycle, and a result obtained by comparing the data signal input in the same clock cycle with the verification code may be output.
[0021]
With this configuration, when the operation controlled in the first or second element is not normally performed in the clock cycle (when a failure occurs), when comparing the data signal and the verification code in the output circuit, The clock cycle when the data signal and the verification code are input to the first and second elements may be different, and the correspondence may not be established. Therefore, it is possible to detect a failure of the controlled operation in the first or second element, and the reliability of the semiconductor integrated circuit can be improved.
[0022]
As a third aspect of the present invention, the verification code is a parity bit or an error correction code, and the output circuit is the data signal controlled by the first element, and the data signal controlled by the second element. A result obtained by comparing parity bits or the error correction code may be output.
Here, the above-mentioned “error correction code” is, for example, a “hamming code” or “CRC (Cyclic Redundancy Code)” described later.
[0023]
In this way, in addition to the failure of the operation controlled in the first or second element, it is possible to detect a failure such as a bit error occurring during data transfer according to various error detection methods adopted. The reliability of the semiconductor integrated circuit can be improved.
[0024]
As a fourth aspect of the present invention, the first element is a first flip-flop to which the data signal is input, and the second element is a second flip-flop to which the verification code is input. The first control circuit may control the operation of the first flip-flop, and the second control circuit may control the operation of the second flip-flop.
[0025]
Here, “the operation of the first or second flip-flop” described above is, for example, “a clear operation for forcibly resetting the output signal of the flip-flop” described later, and “the output signal of the flip-flop is forcibly set. “Preset operation for setting to“ H ”or“ L ”level”, “operation for setting validity / invalidity of clock signal”, and the like. That is, according to the present invention, it is possible to detect failures such as a clear operation controlled by the first or second flip-flop, a preset operation, and an operation for setting the validity / invalidity of the clock signal. Can be improved.
[0026]
As a fifth aspect of the present invention, the first element is a first flip-flop that can control the validity / invalidity of a clock signal used to hold data of the data signal, and the second element is the A second flip-flop that can control the validity / invalidity of the clock signal used to hold the data of the verification code is used, and the first control circuit validates / invalidates the clock signal input to the first flip-flop. The second control circuit may control validity / invalidity of the clock signal input to the second flip-flop.
[0027]
In this way, it is possible to detect a failure in the operation for setting the validity / invalidity of the clock signal controlled in the first or second flip-flop, and the reliability of the semiconductor integrated circuit can be improved.
[0028]
As a sixth aspect of the present invention, the first element is a first select circuit that performs a select operation on the plurality of data signals, and the second element is added to each of the plurality of data signals. The verification code is a second select circuit that performs a select operation, the first control circuit controls the select operation in the first select circuit, and the second control circuit includes the second select circuit. The select operation in the circuit may be controlled.
Here, the above-mentioned “select circuit” is, for example, a “multiplexer” or “demultiplexer” described later. In this way, it is possible to detect a failure in the select operation controlled in the first or second select circuit, and to improve the reliability of the semiconductor integrated circuit.
[0029]
As a seventh aspect of the present invention, a cache memory for storing data exchanged between a host computer and a storage device, and a channel for controlling data transfer between the host computer and the cache memory Communicating between a control unit, a disk control unit that controls data transfer between the cache memory and the storage device, a cache memory control unit that controls the cache memory, the channel control unit, and the disk control unit And a switching control unit for connecting to the storage control device, wherein at least one of the channel control unit, the disk control unit, the cache memory control unit, and the switching control unit receives a data signal. A first element and a verification code corresponding to the data signal are input. A first control circuit for controlling the operation of the first element, a second control circuit for controlling the operation of the second element, and the data signal controlled by the first element And an output circuit that outputs a result of comparing the verification code controlled by the second element.
Here, the above-mentioned “storage control device” is, for example, a “disk array device” or “tape array device” described later.
[0030]
In this way, the memory control device requires less circuit modification and additional circuits than the conventional semiconductor integrated circuit, and can detect the failure of the operation controlled by the first or second element. With this, high reliability can be realized at low cost.
[0031]
=== Specific Description of Examples ===
<Block diagram of data transfer circuit>
FIG. 1 shows a functional block diagram of a data transfer circuit according to an embodiment of the present invention. The data transfer circuit 20 shown in FIG. 1 is one of a plurality of systems used in the system. The data transfer circuit 10 is arranged at the front stage and the data transfer circuit 30 is arranged at the rear stage. When a data signal is input from the data transfer circuit 10 in the previous stage, the data transfer circuit 20 has a function of transferring data to the data transfer circuit 30 in the subsequent stage through steps such as propagation, selection, and calculation of the data signal. It is assumed that a parity bit (1 bit: verification code) is added to the data signal (1 Byte) input from the data transfer circuit 10 in the previous stage. (Note that the size of the data signal is not limited to “1 Byte”.)
The data transfer circuit 20 includes a data path unit 21, a control circuit 23, and a parity checker 22.
The data path unit 21 is a circuit that transfers data through each process such as propagation, selection, and calculation of a data signal (1 byte) to which a parity bit (1 bit) is added. The data path unit 21 includes a first data path unit having a first element to which a data signal (1 Byte) is input and second data having a second element to which a parity bit (1 bit) is input. And a pass part.
[0032]
In FIG. 1, as the first and second elements, a D flip-flop 24a with a clock enable terminal that can control the validity / invalidity of a clock signal based on a clock enable signal (hereinafter referred to as a CE signal). 1st element) and 24b (2nd element) are shown.
[0033]
The control circuit 23 is a circuit that controls the operation of an element corresponding to each of the above-described steps (data signal propagation, selection, calculation, etc.) in the data path unit 21, and is realized by, for example, a state machine. The control circuit 23 is separated into a first control circuit 23a for controlling the operation of the first element and a second control circuit 23b for controlling the operation of the second element.
[0034]
Here, the first control circuit 23a outputs a CE signal (referred to as a first CE signal) to the flip-flop 24a. The second control circuit 23b outputs a CE signal (referred to as a second CE signal) to the flip-flop 24b in the same clock cycle as that of the first CE signal described above.
[0035]
In the parity checker (output circuit) 22, the data signal (1 Byte) held in the flip-flop 24a and the parity bit (1 Bit) held in the flip-flop 24b are input in the same clock cycle. The parity checker 22 performs a parity check using the data signal (1 Byte) and the parity bit (1 Bit) input in the same clock cycle, and outputs the result as an error detection signal.
[0036]
As a code to be added to the data signal (1 Byte), an error correcting code such as a Hamming code or CRC (Cyclic Redundancy Code) can be used in addition to the parity bit. In this case, the parity checker 22 can be replaced with a circuit corresponding to the error detection method to be employed.
[0037]
As described above, the data transfer circuit 20 includes the first element (flip-flop 24a and the like) to which the data signal is input and the second element (flip-flop and the like) to which the verification code (parity bit, error correction code, etc.) is input. 24b and the like, and the first control circuit 23a and the second control circuit 23b are individually provided to independently control the operation of the first element and the operation of the second element.
[0038]
With this configuration, the data transfer circuit 20 can be controlled while suppressing an increase in circuit scale, such as not having to double the data path unit 21 as compared with the data transfer circuit 20 of the full duplex system as shown in FIG. It is possible to detect a failure of the circuit 23 itself, a failure in supplying a control signal from the control circuit 23 to the data path unit 21, and the like (collectively referred to as a control system failure).
[0039]
Further, the data transfer circuit 20 increases the data path width, that is, increases the data transfer amount, while suppressing an increase in circuit scale, as compared with the full-duplex data transfer circuit 20 shown in FIG. can do.
[0040]
<Operation of data transfer circuit>
FIG. 2 shows a timing chart of main signals for explaining the detection operation, taking as an example the failure of the first CE signal supplied to the flip-flop 24a of the data transfer circuit 20. The operation for detecting the failure of the second CE signal supplied to the flip-flop 24b is the same as the operation for detecting the failure of the first CE signal, and the description thereof will be omitted below.
[0041]
First, the operation of the data transfer circuit 20 when the first and second CE signals are normal will be described. Note that the data signal (1 Byte) and the parity bit (1 bit) input to the flip-flops 24a and 24b in the same clock cycle over each clock cycle (T0 to T4 period) are “1” (or “0”). It is assumed that the total number of ")" bits is an even number (or odd number) as defined. Note that the relationship defined between the data signal (1 Byte) and the parity bit (1 bit) is referred to as “parity relationship”.
[0042]
The first and second CE signals are switched from the L level to the H level in the T1 period, and the clock signals supplied to the flip-flops 24a and 24b are in an effective state.
[0043]
Under such a premise, the flip-flops 24a and 24b hold the data signal t1 and the parity bit t1 at the edge of the clock signal in the T1 period (FIG. 2: (A)). The held data signal t1 and parity bit t1 are input in the period T2 to the parity checker 22 and the like subsequent to the flip-flops 24a and 24b (FIG. 2: (B)).
[0044]
The parity checker 22 performs a parity check in the T3 period using the data signal t1 and the parity bit t1 input in the T2 period. Here, since the parity relationship between the data signal t1 and the parity bit t1 is normal, the parity checker 22 sets the result of the parity check as “no error” and outputs an error detection signal (FIG. 2: (C )).
[0045]
Next, an operation in the case where a failure occurs in the first CE signal in the data transfer circuit 20 will be described. As a failure of the first CE signal, a failure is assumed in which the first CE signal does not switch from the L level to the H level in the T1 period and maintains the L level state (FIG. 2: (D) ). In this case, in the T1 period, the clock signal supplied to the flip-flop 24a becomes invalid and the data signal t1 is not held. On the other hand, since the second CE signal is normal in the flip-flop 24b, the parity bit t1 is held in the T1 period (FIG. 2: (D)).
[0046]
Therefore, the input in the T2 period of the parity checker 22 includes the data signal t0 held in the clock cycle before the T1 period in the flip-flop 24a, and the parity bit t1 held in the T1 period in the flip-flop 24b. (FIG. 2: (E)). In the T3 period, the parity checker 22 performs a parity check using the data signal t0 and the parity bit t1. Here, since the parity bit t1 is not a parity code based on the data signal t0, the parity relationship between the data signal t0 and the parity bit t1 basically does not hold. Therefore, the parity checker 22 outputs an error detection signal with the result of the parity check being “error” (FIG. 2: (F)), and detects a failure in the first CE signal.
[0047]
As described above, when the operation controlled in the first or second element (flip-flops 24a and 24b) is not normally performed, the output circuit (parity checker 22 or the like) is controlled by the first element. If the data signal and the verification code controlled by the second element are compared, correspondence (parity relationship or the like) between the data signal and the verification code may not be established. Therefore, the data transfer circuit 20 can detect a failure in the operation controlled in the first or second element, and can achieve high reliability while suppressing an increase in circuit scale as described above.
[0048]
<Select circuit>
As shown in FIG. 3, it is also possible to detect a failure of the select control signal for controlling the select operation for the select circuit 25 (multiplexer, demultiplexer, etc.) constituting the data path unit 21.
[0049]
According to the figure, on the first data path side of the data path unit 21, a signal line for transmitting a data signal (1 Byte) is branched by a combinational circuit (not shown) or the like. A select circuit 25a that performs a select operation on a data signal (1 Byte) transmitted from the branched signal lines via the flip-flops 24a and 24c and the like is provided.
[0050]
On the second data path unit side of the data path unit 21, a signal line for transmitting the parity bit (1 bit) of the data signal (1 Byte) described above is branched by a combinational circuit (not shown) or the like. A select circuit 25b is provided for selecting a parity bit (1 bit) transmitted from the branched signal lines via the flip-flops 24b and 24d.
[0051]
For the select circuits 25a and 25b, the first control circuit 23a outputs a first select control signal for controlling the select operation in the select circuit 25a. The second control circuit 23b outputs a second select control signal for controlling the select operation in the select circuit 25b in the same clock cycle as the first select control signal described above. In the parity checker 22, the data signal (1 Byte) selected by the select circuit 25a and the parity bit (1 bit) selected by the select circuit 25b are input in the same clock cycle.
[0052]
The parity checker 22 performs a parity check using the data signal (1 Byte) and the parity bit (1 bit) input in the same clock cycle, and outputs the result as an error detection signal.
[0053]
With this configuration, the data transfer circuit 20 can detect the above-described failure of the control system with the same circuit scale as the conventional data transfer circuit 20 as shown in FIG. Further, when compared with the data transfer circuit 20 of the full duplex system shown in FIG. 8, it is possible to detect the above-mentioned control system failure while suppressing an increase in circuit scale, for example, it is not necessary to duplicate the data path unit 21. it can. Further, the data transfer circuit 20 increases the data path width, that is, increases the data transfer amount, while suppressing an increase in circuit scale, as compared with the full-duplex data transfer circuit 20 shown in FIG. can do.
[0054]
FIG. 4 shows a timing chart of main signals for explaining the detection operation in the data transfer circuit 20 shown in FIG. 3, taking as an example the failure of the first select control signal supplied to the select circuit 25a. . The operation for detecting the failure of the second select control signal is the same as the operation for detecting the failure of the first select control signal, and thus the description thereof is omitted.
[0055]
As shown in FIG. 4, in the normal case, the first and second select control signals are switched from the L level to the H level at a predetermined timing in the T2 period. As a result, the select circuits 25a and 25b are switched from the D0 terminal input to the D1 terminal input select.
[0056]
Here, a failure is assumed in which the first select control signal does not switch from the L level to the H level in the T2 period and maintains the L level state (FIG. 4: (A)). In this case, the select circuit 25a maintains the selection of the D0 terminal input. On the other hand, in the select circuit 25b, since the second select control signal is normal, the D0 terminal input is switched to the D1 terminal input select.
[0057]
Therefore, the input in the period T2 of the parity checker 22 is the data signal t2 (0) that is the output of the select circuit 25a and the parity bit t2 (1) that is the output of the select circuit 25b (FIG. 4: (B)). ). In the T3 period, the parity checker 22 performs a parity check on the content of the data signal t2 (0) based on the parity bit t2 (1).
[0058]
Here, since the parity bit t2 (1) is not a parity code based on the content of the data signal t2 (0), the parity between the data signal t2 (0) and the parity bit t2 (1) The relationship is not basically established. Therefore, the parity checker 22 sets the result of the parity check as “error” and outputs an error detection signal (FIG. 4: (C)).
[0059]
In this way, the data transfer circuit 20 can detect a failure in the first or second select control signal supplied to the select circuit 25a, and suppresses an increase in circuit scale as described above, while increasing the circuit scale. Reliability can be realized.
[0060]
<Other elements>
In the embodiment according to the present invention, the flip-flop 24 (D, JK flip-flop, etc.) constituting the data path unit 21 is cleared (reset) to which a reset signal for forcibly resetting the output signal is input. It is assumed that a terminal and a preset (set) terminal to which a set signal for forcibly setting the output signal to “H” or “L” level is input are provided. Here, as an embodiment according to the present invention, a configuration for detecting a failure of a reset signal input to a clear terminal or a set signal input to a preset terminal is also conceivable.
[0061]
In this case, the first element is a flip-flop 24a with a clear / preset terminal to which a data signal is input, and the second element is a clear / reset terminal to which an error detection (or correction) code such as a parity bit is input. A flip-flop 24b is provided. The first control circuit 23a controls the clear / preset operation in the flip-flop 24a, and the second control circuit 23b controls the clear / preset operation in the flip-flop 24b.
[0062]
With this configuration, the data transfer circuit 20 can detect the failure of the clear / preset operation controlled by the flip-flops 24a and 24b, and can realize high reliability.
[0063]
<Storage control device>
A storage control device including the data transfer circuit 20 according to the present invention will be described. In the following, the storage controller is a disk array device 40, and the configuration of the storage device system including the disk array device 40 is shown in FIG.
[0064]
In the storage device system, the host computer 50 and the disk array device 40 are connected via communication means 60 such as ESCON (registered trademark), LAN (Local Area Network), SAN (Storage Area Network) or the like. The host computer 50 is an open system computer such as a mainframe computer, a personal computer, or a workstation.
[0065]
The disk array device 40 includes a channel control unit 41, a disk control unit 42, a cache memory control unit 43 including a cache memory 43a, and a disk drive 45. The channel control unit 41, the disk control unit 42, and the cache memory control unit 43 are communicably connected via a switching control unit 44 configured by a crossbar switch or the like.
[0066]
The channel control unit 41 includes a communication interface with the host computer 50, and controls data transfer between the host computer 50 and the cache memory 43a. The disk control unit 42 controls data transfer between the cache memory 43 a and the disk drive 45. The cache memory 43a is accessible from both the channel control unit 41 and the disk control unit 42, and stores input / output data of the disk drive 45. The cache memory control unit 43 controls access to the cache memory 43a.
[0067]
The disk drive 45 may be controlled by a RAID (Redundant Array of Inexpensive (or Independent) Disks) method. The recording area provided by the disk drive 45 is managed using a logical volume that is a logical storage area set on this storage area.
[0068]
The disk array device 40 having such a configuration includes the data transfer circuit 20 according to the present invention for at least one of the channel control unit 41, the disk control unit 42, the cache memory control unit 43, and the switching control unit 44. For example, in the channel control unit 41, a first element (flip-flop 24a or the like) to which a data signal is input, a second element (flip-flop 24b or the like) to which a verification code corresponding to the data signal is input, A first control circuit (first control circuit 23a) for controlling the operation of the first element, a second control circuit (second control circuit 23b) for controlling the operation of the second element, And an output circuit (parity checker 22 or the like) that outputs a result of comparing the data signal controlled by the element and the verification code controlled by the second element. Become.
[0069]
Here, as described above, the data transfer circuit 20 according to the present invention can improve the reliability while suppressing an increase in circuit scale. Therefore, the disk array device 40 requires fewer circuit changes and additional circuits than those of the conventional data transfer circuit 20, and the data transfer according to the present invention can detect the failure of the operation controlled by the first or second element. By providing the circuit 20, high reliability can be realized at low cost.
[0070]
The storage control device is not limited to the above-described disk array device 40. For example, the storage control device may be a tape array device for cartridge type or open reel type magnetic tapes.
[0071]
As mentioned above, although embodiment of this invention was described concretely based on the embodiment, it is not limited to this and can be variously changed in the range which does not deviate from the summary.
[0072]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor integrated circuit and a storage control device including the semiconductor integrated circuit.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of a semiconductor integrated circuit (data transfer circuit) according to an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation timing of the semiconductor integrated circuit (data transfer circuit) according to the embodiment of the present invention.
FIG. 3 is a functional block diagram of a semiconductor integrated circuit (data transfer circuit) according to another embodiment of the present invention.
FIG. 4 is a timing chart for explaining an operation timing of a semiconductor integrated circuit (data transfer circuit) according to another embodiment of the present invention.
FIG. 5 is a schematic configuration diagram of a system including the storage control device in relation to the storage control device including the semiconductor integrated circuit (data transfer circuit) according to the present invention.
FIG. 6 is a functional block diagram of a conventional semiconductor integrated circuit (data transfer circuit).
FIG. 7 is a timing chart for explaining the operation timing of a conventional semiconductor integrated circuit (data transfer circuit).
FIG. 8 is a functional block diagram when a full duplex system is adopted in a semiconductor integrated circuit (data transfer circuit) according to the present invention.
[Explanation of symbols]
10, 20, 30 Data transfer circuit
21 Data path section
22 Parity checker
23 Control circuit
24 flip-flops
25 Select circuit
40 Disk array device
41 Channel controller
42 Disk controller
43 Cache memory controller
44 Switching control unit
45 disk drive
50 Host computer
60 communication means

Claims (2)

A first flip-flop capable of controlling the validity / invalidity of a clock signal used to hold data of the data signal based on a first clock enable signal when a data signal is input;
The parity bit added to the data signal is input in the same clock cycle as the data signal, and the validity / invalidity of the clock signal used to hold the data of the parity bit can be controlled based on the second clock enable signal. A second flip-flop;
A first control circuit for outputting the first clock enable signal to the first flip-flop;
A second control circuit for outputting the second clock enable signal to the second flip-flop;
The data signal held in the first flip-flop and the parity bit held by the second flip-flop are input in the same clock cycle and input in the same clock cycle. Parity check is performed using the data signal and the parity bit, and the result is output as an error detection signal indicating whether a failure of the first clock enable signal, the second clock enable signal or the data signal is detected. A parity checker to
A semiconductor integrated circuit comprising: A cache memory for storing data exchanged between the host computer and the storage device; a channel control unit for controlling data transfer between the host computer and the cache memory; the cache memory; A disk control unit that controls data transfer to and from the storage device, a cache memory control unit that controls the cache memory, and a switching control unit that connects the channel control unit and the disk control unit in a communicable manner. In a storage control device having
At least one of the channel control unit, the disk control unit, the cache memory control unit, or the switching control unit is:
A first flip-flop capable of controlling the validity / invalidity of a clock signal used to hold data of the data signal based on a first clock enable signal when a data signal is input;
The parity bit added to the data signal is input in the same clock cycle as the data signal, and the validity / invalidity of the clock signal used to hold the data of the parity bit can be controlled based on the second clock enable signal. A second flip-flop;
A first control circuit for outputting the first clock enable signal to the first flip-flop;
A second control circuit for outputting the second clock enable signal to the second flip-flop;
The data signal held in the first flip-flop and the parity bit held by the second flip-flop are input in the same clock cycle and input in the same clock cycle. Parity check is performed using the data signal and the parity bit, and the result is output as an error detection signal indicating whether a failure of the first clock enable signal, the second clock enable signal or the data signal is detected. A parity checker to
A storage control device comprising: a semiconductor integrated circuit including:

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