JP4068263B2 - Cell transmission circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a cell transmission circuit, and more particularly to an OAM (Operation, Administration and Maintenance) transmission circuit in an ATM (Asynchronous Transfer Mode) apparatus.
[0002]
[Prior art]
Conventionally, an OAM processing LSI (large scale integrated circuit) using a processor performs all OAM transmission processing by an OAM cell transmission processor 100 as shown in FIG. That is, when the receiving cell 101 is input to the processor 100, the processor 100 performs a predetermined process and outputs the transmitting cell 102. The line bandwidth to be processed was up to about 150 Mbps.
[0003]
In recent years, data transfer speeds have increased, and for example, there has been a demand for DAM processing LSIs using processors that perform high-speed processing such as 2.4 Gbps. However, it is impossible in terms of speed to perform all processing related to the OAM transmission processing by the processor. Therefore, as shown in FIG. 3, for example, the OAM cell transmission processor 200 and the OAM cell transmission scheduler 210 are separated and handled as hardware processing. In the configuration of FIG. 3, the reception cell 201 is input to the OAM cell transmission processor 200, and the transmission cell 202 is output. A transmission OAM cell type 211 is input from the OAM cell transmission scheduler 210 to the OAM cell transmission processor 200.
[0004]
Next, the OAM cell transmission scheduler 210 by the hardware of FIG. 3 can be configured as shown in FIG. The scheduler 210 includes a memory 10, an arbitration unit 20, a, b,. . . x cell transmission determination units 30a, 30b,. . . . , 30x, a priority determination unit 40, and a selector 50. The memory 10 stores (stores) data CN # 1 data to CN # X data at addresses 0000 to XXX. The arbitration unit 20 is connected to the memory 10 via an address and data bus and receives memory setting data from firmware (F / W).
[0005]
The arbitration unit 20 outputs the transmission OAM cell assembly data to the processor and is connected to the a to x cell transmission determination units 30a to 30x. Each of the cell determination units 30a to 30x has the same configuration and includes a timer A31, a timer B32, a transmission request determination unit 33, and an address counter 34. The address counter 34 receives the outputs of the counters 31 and 32 and outputs an address to the arbitration unit 20 and the selector (SEL) 50. The transmission request determination unit 33 receives the cell transmission request bit from the arbitration unit 20 and outputs a corresponding cell transmission request flag to the priority determination unit 40. Further, the priority determination unit 40 outputs the transmission OAM cell type (a to x cells) to the processor. The selector 50 receives the a to x cell transmission request bits and outputs a memory read address to the processor.
[0006]
The memory 10 is divided into information areas for each connection number along the address, and a plurality of types (AIS, RDI, loopback, etc.) of OAM cell transmission request bits are stored for each connection. For example, assuming that a to x cells have a certain OAM type, the a to x cell transmission determination units 30a to 30x access the memory 10 and read the OAM cell transmission request bit of the corresponding OAM cell type. It is determined whether or not this is standing, and if it is standing, a corresponding transmission request flag is set. Upon receiving these flags, the priority determination unit 40 selects one transmission OAM cell type according to the priority order of the OAM type to be transmitted, and transmits it as the transmission OAM cell type 211 to the processor 200 of FIG.
[0007]
At the same time, the address counter 34 of the cell transmission determination units 30a to 30x transmits the address where the standing OAM cell transmission request bit exists, and the selector according to the transmission OAM cell type selected by the priority determination unit 40 The address is selected at 50 and the memory read address is sent to the processor (processor 200 of FIG. 3). Therefore, the processor reads information for assembling an OAM cell of the corresponding transmission OAM cell type from the address according to the transmission OAM cell type and address, and assembles and transmits the OAM cell.
[0008]
Each of the transmission determination units 30a to 30x has a pair of timers (AB, CD, EF) 31 and 32, and thereby controls increment and reset of the address counter 34.
[0009]
The timer 31 is a timer that counts a period for resetting the count value of the address counter 34, and transmits a unique period (according to specifications for each OAM type) pulse to the address counter 34. The address counter 34 is reset by the above-described periodic pulse after the address pointer of the memory 10 advances from connection number 1 to n, and the pointer is returned to the head of the address. That is, the cell transmission determination unit 30 for each OAM type determines the transmission of the OAM cell having the same connection number in the period of the timer 31 and performs transmission.
[0010]
On the other hand, the timer 32 is a timer that counts the period for incrementing the count value of the address counter 34, and transmits a unique period (according to the specification for each OAM type) to the address counter 34. When the count value is incremented, the address counter 34 advances the address pointer of the memory 10 and reads the area of the next connection number. That is, the cell transmission determination unit 30 for each OAM type determines the OAM cell transmission between connections at the time interval of the timer 32 and performs transmission.
[0011]
[Problems to be solved by the invention]
In the prior art described above, the circuit scale is increased because the transmission determination unit 30 including the timers 31 and 32 and the address counter 34 is provided for each type of OAM cell. Further, there are many accesses to the memory 10 with the processor, each transmission determination unit 30 and firmware, and there is a problem that the control of the arbitration unit 20 becomes complicated.
[0012]
An object of the present invention is to provide an OAM cell transmission circuit capable of high-speed operation using an OAM cell transmission scheduler circuit having a small circuit scale.
[0013]
[Means for Solving the Problems]
In order to solve the above-described problems, the cell transmission circuit according to the present invention employs the following characteristic configuration.
[0014]
(1) In a cell transmission circuit having an OAM cell transmission processor that inputs a reception cell and outputs a transmission cell, and an OAM cell transmission scheduler that outputs a transmission OAM cell type to the processor,
The OAM cell transmission scheduler includes a memory for storing cell assembly data, a transmission determination unit for reading a cell transmission request bit from the memory and outputting a cell transmission request flag, and a priority determination for selecting a cell to be transmitted according to priority. And a cell data storage memory for temporarily storing cell assembly data read from the memory.
[0015]
(2) Between the memory of the scheduler for OAM transmission and the transmission determination unit and the cell data storage memory, data setting to the memory and reading of a cell transmission request bit from the memory of the transmission determination unit; The cell transmission circuit according to (1), further including an arbitration unit that performs arbitration.
[0016]
(3) The transmission determination unit includes a transmission request determination unit that transmits the cell transmission request flag, an address counter that is incremented by an increment signal from the transmission request determination unit, a timer that inputs a pulse to the address counter, The cell transmission circuit according to (1), further including an N counter that receives the pulse of the timer and outputs a pulse to the transmission request determination unit.
[0017]
(4) The cell transmission circuit according to (3), wherein the timer includes a first timer that outputs an L second pulse to the address counter and the N counter, and a second timer that outputs a K second pulse to the address counter.
[0018]
(5) The cell transmission circuit according to (1), wherein the cell data storage memory stores cell assembly data for one connection read from the memory.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of a cell transmission circuit according to the present invention will be described in detail with reference to FIG.
[0020]
The figure is a block diagram of a preferred embodiment of a cell transmission circuit according to the invention, in particular its OAM cell transmission scheduler circuit. Since the OAM cell transmission scheduler circuit of FIG. 1 is similar to the circuit of FIG. 4, the corresponding constituent elements are denoted by the same reference numerals.
[0021]
The cell OAM cell transmission scheduler circuit of FIG. 1 includes a memory 10, an arbitration unit 20, a transmission determination unit 30 ′, a priority determination unit 40, and a transmission OAM cell data storage memory 70. The memory 10 stores data for CN # 1 to data for CN # n at addresses 0000 to XXXX. Data is exchanged between the memory 10 and the arbitration unit 20. The arbitration unit 20 receives in-memory setting data from the firmware (F / W), and the output is sent to a transmission request determination unit 65 (to be described later) of the cell transmission determination unit 30 and a transmission OAM cell data storage memory 70. This transmission OAM cell data storage memory 70 outputs transmission OAM cell assembly data to the processor (processor 200 in FIG. 3).
[0022]
Next, the transmission determination unit 30 ′ includes a pair of timers 62 and 63, an N counter 61, an address counter 64, and a transmission request determination unit 65. The transmission request determination unit 65 outputs a to x cell transmission request flags to the priority determination unit 40. The priority determination unit 40 outputs the transmission OAM cell type (a to x cells) to the processor.
[0023]
The memory 10 has information for assembling a plurality of OAM cell transmission request bits and various OAM cells corresponding to the OAM cell transmission request bits, and these pieces of information are set by F / W. Pointer control is performed by an address from the address counter 64. The increment and reset control of the address counter 64 is performed by the transmission request determination unit 65, the timer G62, and the timer H63.
[0024]
The arbitration unit 20 performs arbitration between data setting to the memory 10 from the F / W and reading of the OAM cell transmission request bit from the memory 10 of the transmission determination unit 30 ′.
[0025]
The transmission request determination unit 65 receives all types of OAM cell transmission request bits in a certain connection from the memory 10 and determines whether or not these are set. For those standing, the corresponding transmission request flag (cell a to cell x) is set and transmitted to the priority determination unit 40.
[0026]
The timer G62 counts L seconds and transmits an L second pulse to the address counter 64, thereby resetting the count value of the address counter 64. The timer H63 counts K seconds and transmits a K second pulse to the address counter 64. The timer is started at the same time as the address counter 64 is incremented, and is stopped when counting for K seconds.
[0027]
The N counter 61 receives the L second pulse from the timer G62, generates an N × L second pulse, and transmits it to the transmission request determination unit 65.
[0028]
The priority determination unit 40 receives the received plural (a to x) OAM cell transmission request flags, selects one transmission OAM cell type based on the priority order according to the OAM type, and transmits it to the processor.
[0029]
The transmission OAM cell data storage memory 70 temporarily holds all OAM cell assembly data for one connection read from the memory 10. The capacity of the OAM cell data storage memory 70 is equivalent to the total OAM cell assembly data for one connection. When the processor assembles a type of OAM cell in which the OAM cell transmission request bit of the connection is set, reading is performed by the processor. The next new data is written into the transmission OAM cell data storage memory 70 when the scan advances to the address of the next connection in the memory.
[0030]
The operation of the OAM cell transmission scheduler embodiment of FIG. 1 will be described below. The transmission request determination unit 65 receives all types of OAM cell transmission request bits in a certain connection from the memory 10 and determines whether or not these are set. For those standing, the corresponding transmission request flag (cell a to cell x) is set and transmitted to the priority determination unit 40. The priority determination unit 40 receives the received plurality of OAM cell transmission request flags, selects one transmission OAM cell type based on the priority order according to each cell type, and transmits it to the processor.
[0031]
The transmission determination unit 30 ′ scans the memory 10 for each connection. At the same time as reading all OAM cell transmission request bits of a certain connection, all the OAM cell assembly data (corresponding transmission) of this connection is read. Is written in the transmission OAM cell data storage memory 70 regardless of whether the request bit is set. When the processor assembles a type of OAM cell in which the OAM cell transmission request bit of this connection is set, reading is performed by the processor.
[0032]
When the processor receives the transmission OAM type from the priority determination unit 40, the processor receives predetermined assembly data from the transmission OAM cell data storage memory 70 at the OAM cell insertion timing (empty cell arrival or the like, which is managed by the processor here). Read and assemble / insert OAM cells.
[0033]
The priority determination unit 40 resets the corresponding transmission request flag received from the transmission request determination unit 65 at the same time when the processor receives the transmission OAM cell type.
[0034]
The address counter 64 is reset in a cycle of L seconds by the L second pulse of the timer G62. That is, after the address pointer value in the memory 10 reaches the end (XXXX) and L seconds have elapsed, the pointer is returned to the address head (0000). As a result, each OAM cell transmission request bit of the same connection number is determined in the L second cycle, and the OAM cell of the type in which the OAM cell transmission request bit is set can transmit in the L second cycle over the same connection. .
[0035]
The address counter 64 increments the count value under the condition that all (a cell to x cell) transmission request flags are 0 and K seconds from the previous increment. This means that K seconds have passed since the transmission of the previous connection number, and all the OAM cells corresponding to the OAM cell transmission request bit standing in the current connection number have been transmitted. In this way, the determination of each OAM cell transmission request bit between connection numbers is performed at intervals of K seconds or more, and the OAM cell of the type in which the OAM cell transmission request bit is set has a time interval of K seconds or more between connections. Can be sent.
[0036]
By the way, depending on the OAM type, there is a cell transmission cycle of the same connection other than L seconds. In this case, the transmission request determination unit 65 performs cell transmission at an N × L second cycle if the transmission request determination is made only once every N seconds for the L × L second pulse by the N × L second pulse received from the N counter 61. be able to. Although not shown, the transmission cycle of the same connection can be set to various values by adding small counters such as an M counter and a P counter that function in the same manner as the N counter.
[0037]
Therefore, this circuit can realize the same operation as the circuit in the prior art, which has a timer and transmission request determination circuit for each OAM type and performs scheduling.
[0038]
The preferred embodiment of the cell transmission circuit according to the present invention has been described above in detail. However, it should be understood by those skilled in the art that the present invention should not be limited to only such specific examples, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention is not limited to an OAM cell transmission circuit in an ATM device, but can be applied to a packet transmission scheduler in a general packet communication device.
[0039]
【The invention's effect】
As described above, according to the present invention, there is provided an OAM cell transmission circuit that accommodates a high-speed line using a processor with a small circuit scale of an OAM cell transmission scheduler circuit.
[Brief description of the drawings]
FIG. 1 is a block diagram of a preferred embodiment of an OAM cell transmission scheduler for use in a cell transmission circuit according to the present invention.
FIG. 2 is a block diagram of an OAM processing circuit based on conventional processor processing.
FIG. 3 is a block diagram of an OAM processing circuit by processor processing when accommodating a high-speed line.
FIG. 4 is a block diagram of a general OAM cell transmission scheduler.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Memory 20 Arbitration part 30 'Transmission determination part 40 Priority determination part 61 N counter 62, 63 Timer 64 Address counter 65 Transmission request determination part 70 Cell data storage memory 200 OAM cell transmission processor

Claims (5)

In a cell transmission circuit having an OAM cell transmission processor for inputting a reception cell and outputting a transmission cell, and an OAM cell transmission scheduler for outputting a transmission OAM cell type to the processor,
The OAM cell transmission scheduler includes a memory for storing cell assembly data, a transmission determination unit for reading a cell transmission request bit from the memory and outputting a cell transmission request flag, and a priority determination for selecting a cell to be transmitted according to priority. And a cell data storage memory for temporarily storing cell assembly data read from the memory. Between the memory of the scheduler for OAM transmission and the transmission determination unit and the cell data storage memory, arbitration between data setting to the memory and cell transmission request bit reading from the memory of the transmission determination unit The cell transmission circuit according to claim 1, further comprising an arbitration unit. The transmission determination unit includes a transmission request determination unit that transmits the cell transmission request flag, an address counter that is incremented by an increment signal from the transmission request determination unit, a timer that inputs a pulse to the address counter, The cell transmission circuit according to claim 1, further comprising an N counter that receives the pulse and outputs the pulse to the transmission request determination unit. 4. The cell according to claim 3, wherein the timer includes a first timer that outputs an L second pulse to the address counter and the N counter, and a second timer that outputs a K second pulse to the address counter. Transmitter circuit. 2. The cell transmission circuit according to claim 1, wherein the cell data storage memory stores cell assembly data for one connection read from the memory.

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