JP4072082B2 - Defective solder diagnosis circuit for semiconductor devices - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit for diagnosing a soldering failure between a semiconductor device such as an LSI and a printed board, and more particularly to a circuit for providing a highly versatile soldering failure diagnosing circuit.
[0002]
[Prior art]
Conventionally, as this type of circuit, for example, when an LSI using an IC package called BGA (Ball Grid Array) is soldered to a PCB (printed wiring board), thermal expansion between the BGA and the PCB is performed. Due to this difference, the soldering between the pins of the BGA, particularly the outermost peripheral pins, and the PCB is subject to a large mechanical stress compared to other parts, so that cracking and peeling are likely to occur in the soldering of this part. In view of this, there has been proposed one in which a detection circuit for detecting a soldering failure between the pin on the outermost peripheral portion of the BGA and the PCB is provided (for example, see Patent Document 1).
[0003]
[Patent Document 1]
JP 2001-228191 A (page 3-4, FIGS. 1-4)
[0004]
[Problems to be solved by the invention]
However, in the above prior art, it is necessary to secure a plurality of pins dedicated to the BGA in order to connect the detection circuit. Therefore, a new pin for connecting the detection circuit to the BGA before the detection circuit is provided. If there is not enough room to ensure the BGA, it is necessary to change the BGA itself, and there is a problem that the versatility of the detection circuit is lacking.
The present invention has been made in view of the above circumstances, and provides a highly versatile solder failure diagnosis circuit for a semiconductor device without changing the pin arrangement of the semiconductor device.
Another object of the present invention is to provide a solder failure diagnostic circuit for a semiconductor device that can improve the reliability of the semiconductor device with a relatively simple configuration.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, a solder failure diagnostic circuit for a semiconductor device according to the present invention comprises:
A solder failure diagnosis circuit for a semiconductor device that detects a soldering failure between a semiconductor device and a printed circuit board and performs a notification operation according to a detection result,
The semiconductor device solder failure diagnostic circuit includes a comparison circuit and a notification unit,
The semiconductor device is provided with a plurality of pads arranged in a BGA arrangement on a surface to be soldered to the printed circuit board, and a pad located on the outermost peripheral portion of the pad surface and a pad located on the outermost peripheral portion. The pad located on the inside is secured to supply power to the semiconductor device,
The comparison circuit includes a first resistor and a second resistor connected in series between a power source supplied to the semiconductor device and a ground, and an end portion on the power source side of the first resistor While the pad located at the outermost peripheral portion where the defective soldering of the pad surface of the semiconductor device is likely to occur first is connected to the pad for supplying power to the semiconductor device,
A third resistor and a capacitor are connected in series between a power source supplied to the semiconductor device and the ground, and a pad of the semiconductor device is connected to a connection point between the third resistor and the capacitor. A pad located on the inner side of a pad located on the outermost peripheral portion of the surface and connected to a pad for supplying power to the semiconductor device, and the pad for supplying power can be used for detecting occurrence of a soldering failure. Being
Using the voltage at the connection point between the first and second resistors as a reference voltage, a comparison result of the voltage at the connection point between the reference voltage and the third resistor and the capacitor is obtained. And
The notification unit is configured to perform a preset notification operation when a predetermined signal corresponding to a soldering failure between the semiconductor device and the printed circuit board is output from the comparison circuit.
[0006]
In such a configuration, among the pads to which the power supply voltage supplied to the semiconductor device is applied, the power supply that supplies the power supply voltage of the semiconductor device to the pad located at the outermost peripheral portion where the soldering failure is likely to occur first. A pad located on the power supply side of the third resistor provided between the first resistor and the ground, and a pad located on the inner side of the pad located on the outermost peripheral portion are connected to the other end of the third resistor, respectively. However, unlike the conventional case, it is possible to detect the presence or absence of soldering defects by adopting a configuration that can detect voltage fluctuations that occur in the third resistor when the solder located on the outermost pad is peeled off. Therefore, it is possible to detect the presence or absence of soldering defects without providing dedicated pads and pins in the semiconductor device.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a semiconductor device S in which a solder failure diagnosis circuit for a semiconductor device according to an embodiment of the present invention is used will be described with reference to FIG.
In FIG. 4, the semiconductor device S and the printed circuit board 11 to which the semiconductor device S is soldered are schematically shown, and the schematic internal structure of the semiconductor device S is schematically shown.
In general, the semiconductor device S has a semiconductor chip 12 provided therein and is connected to an electronic component 13 provided around the semiconductor chip 12 via a bonding wire 14 to form a desired circuit. It has become so. The semiconductor device S in the embodiment of the present invention is represented by, for example, an LSI (Large Scale Integration), and in particular, a BGA (Ball Grid Array) which has become mainstream in recent years as a package of this type of semiconductor device. ) And a package having an input / output pin arrangement. A plurality of pads 15 are provided in a BGA arrangement on the surface of the semiconductor device S to be soldered to the printed board 11, and a known and known so-called reflow soldering is applied to the solder bumps 16 provided on the printed board 11. It is designed to be soldered by attaching. Since so-called input / output pins (not shown) of the semiconductor device S are connected to the pads 15, soldering the pads 15 to the printed circuit board 11 means that the input / output pins of the semiconductor device S are attached to the printed circuit board 11. It must be soldered. Here, the input / output pins include not only signals but also those used for power supply and ground.
[0008]
As shown in FIG. 5, the surface to be soldered to the printed circuit board 11 of the semiconductor device S, that is, the pad surface, has a large number of pads 15 arranged in a BGA pattern like a grid. In the example shown in the figure, the pad position at the upper left corner of the drawing is “A1”, and A2, A3,... .., Y are added in alphabetical order as one row is moved downward from the position of, and the position in the row direction (vertical direction on the paper surface in FIG. 5) is alphabetically and in the column direction (FIG. 5). In this example, the position of the pad is specified by numerically representing the position in the horizontal direction in FIG.
The pad surface of the semiconductor device S according to the embodiment of the present invention includes pads (A1 to A20, B1 to Y1, B20 to Y20, Y1 to Y20) located on the outermost periphery and pads (A2) located on the inner periphery thereof. To A19, B2 to X2, B19 to X19, and Y2 to Y19) are ensured to be used for supplying power (for example, 5 V) of the semiconductor device S. In FIG. 5, for simplification of the drawing, the illustration of the pads located further inside than these pads and used for signal input / output is omitted.
[0009]
Next, a configuration example of the solder failure diagnostic circuit CR1 for a semiconductor device in the embodiment of the present invention will be described with reference to FIG.
The semiconductor device solder failure diagnosis circuit CR1 is roughly divided into a comparison circuit 101 configured with the comparator 1 at the center and a notification unit 102 that performs a notification process required according to the comparison result of the comparison circuit 101. It is configured. The semiconductor device solder failure diagnosis circuit CR1 is provided on the printed circuit board 11 or when the semiconductor device S is a so-called custom LSI, and there is a margin in the internal component arrangement space. Even if it is incorporated in S, any of them may be used.
First, the comparison circuit 101 includes a comparator 1 and is connected between a power supply line 2 to which a power supply (not shown) that supplies power supply voltage for the semiconductor device S and the solder failure diagnostic circuit CR1 for the semiconductor device is connected and the ground. 1 includes a first resistor (indicated as “R1” in FIG. 1) 3 and a second resistor (indicated as “R2” in FIG. 1) 4 connected in series, and a mutual connection between them. The connection point is connected to the inverting input terminal of the comparator 1. The power supply line 2 is connected to a plurality of pads for power supply among pads located on the outermost peripheral portion of the pad surface of the semiconductor device S (hereinafter, this pad is referred to as “outermost peripheral pad” for convenience). Yes. That is, in the embodiment of the present invention, the power supply line 2 is connected to the outermost peripheral pads A1, A20, Y1, Y20 (see FIGS. 1 and 5). That is, in other words, in the embodiment of the present invention, these outermost peripheral pads A1, A20, Y1, Y20 are connected to a power supply pin (5 V) (not shown) of the semiconductor device S.
[0010]
A third resistor (indicated as “R3” in FIG. 1) 5 and a capacitor (indicated as “C1” in FIG. 1) 6 are connected in series between the power supply line 2 and the ground. The connection point is connected to the non-inverting input terminal of the comparator 1. Further, the non-inverting input terminal of the comparator 1 is a pad located on the inner periphery of the outermost peripheral portion of the pad surface of the semiconductor device S (hereinafter, this pad is referred to as “inner pad” for convenience). Are connected to a plurality of pads for power supply. That is, in the embodiment of the present invention, the non-inverting input terminal of the comparator 1 is connected to the inner pads B2, A16, B19, P20, W2, and W19 (see FIGS. 1 and 5). ).
The outermost peripheral pads A1, A20, Y1, Y20 connected to the previous power supply line 2 and the inner pads B2, A16, B19, P20, W2, W19 connected to the non-inverting input terminal of the comparator 1 are semiconductors. When the device S is in a normal state, it is a matter of course that the device S is in an electrically conductive state via a power supply line (not shown) inside the semiconductor device S.
[0011]
On the other hand, the output terminal of the comparator 1 is connected to the input stage of the notification unit 102 described below.
The notification unit 102 is configured to perform a notification operation to make the user recognize when a predetermined signal corresponding to a soldering failure is output from the comparator 1 as will be described later. It is. Here, as the notification operation, for example, lighting of a lighting element, ringing of an alarm element, display by a display element such as a character or a figure, and the like are preferable, and it is not necessary to be limited to any of them.
FIG. 2 shows a configuration example of the notification unit 102 that performs the lighting operation. Hereinafter, the configuration example will be described with reference to FIG. 2. This configuration example uses the LED 7 as a lighting element. Thus, the anode power supply voltage V _B is applied to the anode via the fourth resistor 8, while the cathode is connected to the output terminal of the comparator 1. . In this case, the comparator 1 is preferably one whose output stage is a so-called open collector.
[0012]
Next, the operation of the solder failure diagnosis circuit for a semiconductor device in the embodiment of the present invention having the above-described configuration will be described.
First, it is assumed that the notification unit 102 has the configuration described with reference to FIG.
First, when there is no abnormality (defect) in soldering between the semiconductor device S and the printed circuit board 11 and the semiconductor device S is operating normally, both ends of the third resistor 5 are connected to the outermost peripheral pads A1, Since A20, Y1, Y20 and the inner pads B2, A16, B19, P20, W2, W19 are in a conductive state inside the semiconductor device S, all are held at the power supply voltage Vcc. The inverting input terminal is also held at the power supply voltage Vcc.
On the other hand, in the series connection portion of the first and second resistors 3 and 4, the power supply voltage Vcc is resistance-divided, so that the reference voltage Vref = R2 × Vcc / (R1 + R2) is applied to the inverting input terminal of the comparator 1. ) Is applied. Here, for the sake of convenience, R1 and R2 are the resistance value of the first resistor 3 and the resistance value of the second resistor 4, respectively, and Vcc is the value of the power supply voltage.
[0013]
The reference voltage Vref at the inverting input terminal of the comparator 1 is smaller than the voltage at the non-inverting input terminal of the comparator 1 during the normal operation, that is, in the embodiment of the present invention. , The resistance values of the first and second resistors 3 and 4 are set in advance so that Vref <Vcc.
Therefore, during normal operation, since the voltage at the non-inverting input terminal exceeds the reference voltage Vref at the inverting input terminal, the comparator 1 outputs a signal corresponding to the logical value High.
When the output of the comparator 1 is in a state corresponding to the logical value High, the LED 7 is turned off because it is in a non-conductive state.
[0014]
Next, a case where a soldering failure occurs will be described. First, as conventionally known, the soldering failure, that is, specifically, the peeling of soldering is performed by the semiconductor device S using the BGA package. In most cases, the first occurs at the pad located at the outermost peripheral portion of the pad surface of the semiconductor device S due to the difference in thermal expansion from the printed circuit board 11.
For example, it is assumed that the soldering peeling from the printed circuit board 11 occurs in any of the outermost peripheral pads A1, A20, Y1, and Y20. In this case, since the supply of the power supply voltage Vcc to the semiconductor device S is performed via the outermost peripheral pad, the voltage at the non-inverting input terminal and the inverting input terminal of the comparator 1 does not change, and the notification unit 102 is normal. The operating state at the time will be maintained.
Next, of the pads located on the outermost periphery of the pad surface of the semiconductor device S, all of the pads connected to the semiconductor device solder failure diagnostic circuit CR1, that is, the outermost periphery in the embodiment of the present invention. If solder peeling occurs in all of the pads A1, A20, Y1, and Y20, the inner pads, that is, the inner pads B2, A16, B19, P20, and W2 in the embodiment of the present invention are connected to the semiconductor device S. , W19 is used to supply the power supply voltage Vcc. Therefore, at the normal time, as described above, both ends of the third resistor 5 are held at the power supply voltage Vcc and no current flows, whereas the outermost peripheral pads A1, A20, Y1, When the soldering peeling occurs in all of Y20, a current flow occurs in the third resistor 5, so that a voltage drop occurs. As a result, the voltage at the non-inverting input terminal of the comparator 1 is reduced by a voltage drop (R3 × I3) in the third resistor 5 as compared with the normal state as expressed by Vcc−R3 × I3. Become. Here, for convenience, R3 is a resistance value of the third resistor 5, and I3 is a current value flowing through the third resistor 5.
[0015]
The resistance value of the third resistor 5 is set in advance so that the voltage (Vcc−R3 × I3) of the non-inverting input terminal of the comparator 1 is sufficiently lower than the reference voltage Vref of the inverting input terminal. After all, when the soldering peeling occurs, the comparator 1 outputs a signal corresponding to the logical value Low, so that the LED 7 is turned on and turned on, and the user is notified of the occurrence of the soldering peeling. Become.
In the case where the notification unit 102 is configured to use a ringing element such as a buzzer instead of the LED 7 described above, a buzzer (not shown) sounds instead of the lighting of the LED 7 when the soldering peeling occurs. Except for this point, the basic operation of the other circuit portions is the same as described above, and thus detailed description thereof is omitted.
[0016]
Next, another configuration example of the notification unit 102 will be described with reference to FIG.
The notifying unit 102 is configured with a known and well-known microcomputer (noted as “CPU” in FIG. 3) 9 and a display element (noted as “DSP” in FIG. 3) 10 as main components. It has become. And the output terminal of the comparator 1 is connected to the signal input terminal of the microcomputer 9, and the logical value judgment is performed. The display element 10 is a known or well-known device typified by a so-called CRT or liquid crystal display, but of course, the display device 10 is not limited to a specific type and can display characters and images. Anything is good.
In this configuration, as described above, when the signal corresponding to the logical value High is output from the comparator 1 on the assumption that the soldering peeling does not occur in the outermost peripheral pad, the input signal is a logical value in the microcomputer 9. High, it is determined that the soldering peeling has not occurred in the outermost peripheral pad, and a predetermined display using characters, drawings, or the like indicating that the soldering peeling has not occurred is performed on the display element 10.
[0017]
On the other hand, as described above, when a signal corresponding to the logical value Low is output from the comparator 1 due to the occurrence of soldering peeling of the outermost peripheral pad, the input signal is the logical value Low in the microcomputer 9 and the maximum value is output. It is determined that the soldering peeling has occurred on the outer peripheral pad, and a predetermined display such as a character or a figure indicating that the soldering peeling has occurred is performed on the display element 10.
Note that the positions of the outermost peripheral pads and the inner pads of the semiconductor device S connected to the solder failure diagnostic circuit CR1 for the semiconductor device in the above-described configuration example are merely examples, and need not be limited to this. .
[0018]
In the above configuration example, the power supply voltage Vcc of the semiconductor device S is divided by the first and second resistors 3 and 4 to obtain the reference voltage Vref applied to the inverting input of the comparator 1. Of course, the reference voltage Vref is not necessarily limited to that obtained by such a configuration. That is, for example, a circuit that generates the reference voltage Vref may be provided separately and used. In this case, of course, the first and second resistors 3 and 4 in the configuration shown in FIG. 1 are unnecessary, and the output terminal of a separate circuit for generating the reference voltage is the inverting input terminal of the comparator 1. Will be connected.
[0019]
【The invention's effect】
As described above, according to the present invention, among the pads of the semiconductor device soldered to the printed circuit board, the pads located on the outermost periphery and applied with the power supply voltage, and the pads located on the outermost periphery. Unlike the conventional case, the dedicated pad and pin are used to detect the presence of soldering defects, because the configuration is such that the occurrence of soldering defects can be detected by diverting pads located on the inner side to which power supply voltage is applied. Therefore, it is possible to provide a highly versatile solder failure diagnosis circuit for a semiconductor device without providing the semiconductor device.
In addition, according to the present invention, since the circuit configuration is such that a voltage change is caused by a soldering failure, and the soldering failure can be detected by the voltage change, the soldering failure is detected with a relatively simple configuration. Therefore, it is possible to contribute to improving the reliability of the semiconductor device.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a circuit configuration example of a solder failure diagnostic circuit for a semiconductor device in an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific circuit configuration example of a notification unit that constitutes the solder failure diagnostic circuit for a semiconductor device shown in FIG. 1;
FIG. 3 is a circuit diagram showing another specific circuit configuration example of a notification unit that constitutes the solder failure diagnostic circuit for a semiconductor device shown in FIG. 1;
FIG. 4 is a schematic diagram for explaining a semiconductor device and a printed circuit board in which the solder failure diagnosis circuit for a semiconductor device according to the embodiment of the present invention is used.
FIG. 5 is a schematic diagram schematically showing a pad surface of a semiconductor device in which a solder failure diagnostic circuit for a semiconductor device according to an embodiment of the present invention is used.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Comparator 3 ... 1st resistor 4 ... 2nd resistor 5 ... 3rd resistor 15 ... Pad 101 ... Comparison circuit 102 ... Notification part

Claims (6)

A method for diagnosing a solder failure in a semiconductor device for determining whether or not a soldering failure has occurred between a semiconductor device and a printed circuit board,
The semiconductor device is provided with a plurality of pads arranged in a BGA arrangement on a surface to be soldered to the printed circuit board, and a pad located on the outermost peripheral portion of the pad surface and a pad located on the outermost peripheral portion. The pad located on the inner side is secured to supply power to the semiconductor device,
A resistor and a capacitor are connected in series between a power supply to be supplied to the semiconductor device and a ground, and a soldering failure of the pad surface of the semiconductor device is present at an end of the resistor on the power supply side. While the pad located on the outermost peripheral portion that is likely to occur first and connecting the pad for supplying power to the semiconductor device,
A connection point between the resistor and the capacitor is a pad located on the inner side of the pad located on the outermost peripheral portion of the pad surface of the semiconductor device and connected to a pad for supplying power to the semiconductor device, Using the power supply pad to detect the occurrence of soldering failure,
A method of diagnosing a solder failure of a semiconductor device, comprising: diagnosing occurrence of soldering failure between the semiconductor device and a printed circuit board by comparing a voltage at a connection point between the resistor and the capacitor with a reference voltage. . A solder failure diagnosis circuit for a semiconductor device that detects a soldering failure between a semiconductor device and a printed circuit board and performs a notification operation according to a detection result,
The semiconductor device solder failure diagnostic circuit includes a comparison circuit and a notification unit,
The semiconductor device is provided with a plurality of pads arranged in a BGA arrangement on a surface to be soldered to the printed circuit board, and a pad located on the outermost peripheral portion of the pad surface and a pad located on the outermost peripheral portion. The pad located on the inside is secured to supply power to the semiconductor device,
The comparison circuit includes a first resistor and a second resistor connected in series between a power source supplied to the semiconductor device and a ground, and an end portion on the power source side of the first resistor While the pad located at the outermost peripheral portion where the defective soldering of the pad surface of the semiconductor device is likely to occur first is connected to the pad for supplying power to the semiconductor device,
A third resistor and a capacitor are connected in series between a power source supplied to the semiconductor device and the ground, and a pad of the semiconductor device is connected to a connection point between the third resistor and the capacitor. A pad located on the inner side of a pad located on the outermost peripheral portion of the surface and connected to a pad for supplying power to the semiconductor device, and the pad for supplying power can be used for detecting occurrence of a soldering failure. Being
Using the voltage at the connection point between the first and second resistors as a reference voltage, a comparison result of the voltage at the connection point between the reference voltage and the third resistor and the capacitor is obtained. And
The notification unit is configured to perform a preset notification operation when a predetermined signal corresponding to a soldering failure between the semiconductor device and the printed circuit board is output from the comparison circuit. A solder failure diagnosis circuit for semiconductor devices. A solder failure diagnosis circuit for a semiconductor device that detects a soldering failure between a semiconductor device and a printed circuit board and performs a notification operation according to a detection result,
The semiconductor device solder failure diagnostic circuit includes a comparison circuit and a notification unit,
The semiconductor device is provided with a plurality of pads arranged in a BGA arrangement on a surface to be soldered to the printed circuit board, and a pad located on the outermost peripheral portion of the pad surface and a pad located on the outermost peripheral portion. The pad located on the inside is secured to supply power to the semiconductor device,
In the comparison circuit, a resistor and a capacitor are connected in series between a power source supplied to the semiconductor device and a ground, and a power source side end of the resistor has a pad surface of the semiconductor device. While a pad located on the outermost peripheral portion where a soldering failure is likely to occur first and a pad for supplying power to the semiconductor device is connected,
A connection point between the resistor and the capacitor is connected to a pad located on the inner side of the pad located on the outermost peripheral portion of the pad surface of the semiconductor device and for supplying power to the semiconductor device, The power supply pad can be diverted to detect the occurrence of soldering failure,
It is configured to obtain a comparison result between a voltage at a connection point between the resistor and the capacitor and a reference voltage,
The notification unit is configured to perform a preset notification operation when a predetermined signal corresponding to a soldering failure between the semiconductor device and the printed circuit board is output from the comparison circuit. A solder failure diagnosis circuit for semiconductor devices.   The notification unit is configured to turn on the lighting element when a predetermined signal corresponding to a soldering failure between the semiconductor device and the printed circuit board is output from the comparison circuit. 4. A solder failure diagnosis circuit for a semiconductor device according to 3.   The notification unit is configured to ring the ringing element when a predetermined signal corresponding to a soldering failure between the semiconductor device and the printed circuit board is output from the comparison circuit. 4. A solder failure diagnosis circuit for a semiconductor device according to 3.   The notification unit includes a microcomputer and a display element, and determines whether or not the output of the comparison circuit is a predetermined signal corresponding to a soldering failure between the semiconductor device and the printed circuit board. 4. The solder failure diagnosis circuit for a semiconductor device according to claim 2, wherein the display element is configured to perform a predetermined display when it is determined that the display device is present.

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