JP4074682B2 - Programmable polysilicon gate array structure and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates generally to the structure of complementary metal oxide semiconductor (CMOS) gate arrays and methods of manufacturing the same, and more particularly to the design of basic cells used for such gate arrays.
[0002]
[Prior art]
A gate array is one type of integrated circuit (IC) comprising an array in which the same basic cells are repeatedly arranged in the core region of a semiconductor chip. Each basic cell includes a predetermined number and arrangement of MOS transistors. As with all MOS ICs, each transistor has two source / drain diffusion regions separated by a channel region and a gate disposed on the channel region in a silicon substrate. . Each gate has a thin gate oxide film sandwiched between the polysilicon gate electrode and the channel region of the substrate.
[0003]
The gate array master slice structure does not include a specific circuit in advance, but includes only unconnected MOS transistors that form a circuit by being wire-connected to each other in the future. Thus, transistor level gate array designs have the flexibility to allow for the formation of many different types of integrated circuits, eg, memory chips, logic chips. The final design of such a gate array integrated circuit is the back-end process used (i.e., the process for forming and patterning the metallization layer and these processes are formed on the basic cell. This is determined by the process of wire-connecting a number of available transistors. The arrangement of these interconnects defines the circuit configuration that appears on a particular gate array integrated circuit. Because of this flexibility, gate arrays are widely used to create application specific integrated circuits (ASICs).
[0004]
FIG. 1 shows a basic gate array structure 10 including a core region 24 provided on a semiconductor chip 23 and having an array of identical basic cells, such as basic cells 20. As shown in the figure, the basic cells are generally rectangular and are repeatedly arranged in the row direction and the column direction. Each basic cell includes a number of transistors (not shown). A first metal line 21 and another first metal line 22 are applied to each column of basic cells in the core region 24 over the length of the core region in the column direction. The metal line 22 is used to supply a power supply voltage (Vdd) to each basic cell in the column direction in the array, and the metal line 21 is used to supply a ground voltage (Vss) to each basic cell in the column direction. It is done. The gate array 10 also has a Vdd metal line 18 for supplying a power supply voltage to the metal line 22 and a Vss metal line 16 for supplying a ground voltage to the metal line 21 around the core. is doing.
[0005]
The gate array structure 10 further includes input / output (I / O) pads 12 and I / O slots 14 along the periphery of the chip 23 outside the core region 24. These pads form contact areas for connecting the IC circuit to external elements by wire bonds or other electrical connection means. The I / O slot 14 includes a transistor and other elements used for connection to an external element to which the chip 23 is connected. Generally, the slot 14 includes an electrostatic discharge (ESD) protection circuit, a pre-driver, an input / output buffer, and the like.
[0006]
One suitable basic cell design for the gate array has been developed and is used by LSI Logic Corporation, located in Milpitas, California. This design uses eight MOS transistors consisting of four n-type and four p-type transistors, all of approximately the same dimensions. This design is described in FIG. As shown in the figure, for example, a basic cell 50 corresponding to the basic cell 20 in FIG. 1 is formed on a p-type substrate 64 and includes an n-type transistor surface 54 and a p-type transistor surface 52. The p-type transistor surface 52 has an n-well 56 in which four p-type transistors 53a, 53b, 53c and 53d are formed, all of which are arranged in parallel to a single axis. As shown, each p-type transistor has the same size and shape. All or some of these transistors are connected to each other or to other transistors by a back-end process to form a circuit.
[0007]
Focusing on the p-type transistor 53 d, a polysilicon gate electrode 67 is provided between the source diffusion region 59 and the drain diffusion region 57. The gate electrode 67 is terminated with two polysilicon contacts (polyheads) 58a and 58b. A tap 69 is provided between transistor 53b and transistor 53c to provide a contact to the Vdd supply voltage supply line.
[0008]
The n-type transistor surface 54 includes four n-type transistors 55a, 55b, 55c, and 55d arranged in parallel with the transistors on the p-type transistor surface 52. As illustrated, the n-type transistor 55d includes a gate electrode 66 having the same size and shape as the gate electrode 67, for example. In addition, a tap 68 is provided between n-type transistor 55b and n-type transistor 55c to provide a contact to the Vss ground voltage supply line.
[0009]
The gate array design as shown in FIGS. 1 and 2 should be distinguished from the “cell-based” design. In a cell design, rather than repeatedly providing a single basic cell in the core region of the chip, it includes many different basic cells. In general, individual basic cells have different dimensions, shapes, transistor arrangements, etc., and are arranged based on the design of a particular integrated circuit. In general, cellular integrated circuits make more efficient use of available chip space than gate array integrated circuits, since the design and layout of the basic cells are dictated by the design of the integrated circuit. However, cellular technology is generally unsuitable for use with ASICs that do not produce sufficient quantities, as additional development costs incurred in connection with the cellular design process must be compensated. There are many cases. For this reason, gate array designs continue to find wide application in ASIC designs.
[0010]
Gate array designers continue to tackle the challenge of simplifying on-chip routing. To achieve this challenge, designers are improving chip space utilization efficiency and at the same time simplifying the manufacturing process. The term routing means an electrical connection formed between individual transistors to form a circuit in an IC. These connections are formed by vertically interconnecting between the transistors on the IC substrate surface and the metallization layer located on the substrate. The insulator layer electrically insulates the metal coating layer from other metal coating layers and the substrate. Each metal coating layer is patterned to form various metal lines that electrically couple a plurality of transistors and device elements to form an IC circuit. Due to the complexity of current gate arrays, two or more metallization layers are generally required. Unfortunately, each additional metallization layer adds significant cost and further complicates the gate array fabrication process.
[0011]
Most of the wiring provided in the gate array design functions to form individual circuits that form the IC. Such a circuit can be a simple logic gate such as a NAND gate as well as a more complex circuit configuration such as a multiplexer, a flip-flop with multiple input terminals. In addition to such basic circuit level routing, ICs also use many “chip level routings” that connect individual circuits together to form functional ICs. Such chip level routing is formed by metal lines that may have to pass through many basic cells. Since circuit level routing occupies space on a particular metallization layer level, that space cannot be used for chip level routing. In fact, if circuit level routing takes up too much space, other metallization layers must be used for some or all chip level routing. Accordingly, the design of the gate array that reduces the amount of routing at the circuit level in the first and second metallization layers can significantly reduce the cost of the IC.
[0012]
FIG. 3 illustrates a basic cell 80 in which several individual basic cells 82a-82d are assembled. The first metallization layer (metal-1) is not shown to show how circuit level routing in the second metallization layer (metal-2) is generally performed. For example, when a complicated flip-flop circuit is formed on the plurality of basic cells 82a to 82d, metal-1 cannot completely wire-connect the flip-flop in itself. Therefore, metal-2 jumpers 84, 86, 88, 90 and 92 are required to complete the necessary transistor interconnections. Via contacts such as contacts 81a, 81b are used to provide an interlayer connection.
[0013]
[Problems to be solved by the invention]
However, as shown, the metal-2 jumpers 84, 86, 88, 90, and 92 leave significant space in the left and center areas of the base cell, but these spaces are not available for chip level routing. It is. In some instances, there is also the problem that additional metal lines from the third metallization layer (metal-3) must be formed.
[0014]
The present invention has been made to solve the above-mentioned problems of the prior art and reduce the gate array manufacturing process, and reduces the circuit level routing amount at the first and / or second metallization layer level. An object is to provide a master slice of an array.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, a gate array structure according to the invention described in claim 1 is formed on a semiconductor substrate and has an array of the same basic cells in a core region.
Each basic cell is
A plurality of transistors each having a gate electrode;
One or more gate connection strips formed on the substrate and electrically connected to selected gate electrodes of two or more of the transistors;
The plurality of transistors are:
A first transistor group each comprising a transistor having a first gate width and having a first conductivity characteristic;
A second transistor group consisting of transistors each having a second gate width substantially equal to the first gate width and having a second conductivity characteristic opposite to the first conductivity characteristic;
Each having a third gate width narrower than the first and second gate widths, and a third transistor group comprising transistors having the first conductive characteristics;
The transistors of the first and second transistor groups all have gates arranged parallel to the first axis;
All of the transistors of the third transistor group have gates arranged parallel to a second axis substantially perpendicular to the first axis.
[0016]
The gate array structure according to the invention of claim 2 is
The gate array structure of claim 1,
The gate connection strip is formed of the same material as the selected gate electrode, and is connected integrally with the selected gate electrode,
The gate array structure according to the invention of claim 3
The gate array structure according to claim 2,
The gate connection strip and the gate electrode are made of polysilicon.
[0017]
The gate array structure according to the invention of claim 4 is:
The gate array structure of claim 1,
At least one of the gate connection strips is arranged substantially perpendicular to the at least one of the gate electrodes;
The gate array structure according to the invention of claim 5 is:
The gate array structure of claim 1,
The first transistor group includes four transistors, and the second transistor group includes four transistors.
[0018]
The gate array structure according to the invention of claim 6 is:
The gate array structure of claim 1,
The transistor of the first transistor group includes at least one transistor set including two transistors connected in series sharing a source / drain region,
The gate array structure according to the invention of claim 7 is:
The gate array structure of claim 1 further comprises:
A tap is provided for connecting the power supply voltage supply line or the ground voltage supply line to the transistor having the first conductive characteristic in the vicinity.
[0019]
The gate array structure according to the invention of claim 8 is
The gate array structure of claim 1,
The second transistor group includes at least one transistor set including two transistors connected in series sharing a source / drain region,
The gate array structure according to the invention of claim 9 is
The gate array structure of claim 1 further comprises:
A tap is provided for connecting the power supply voltage supply line or the ground voltage supply line to the adjacent second transistor group.
[0020]
The gate array structure according to the invention of claim 10 is:
The gate array structure of claim 1,
The transistors of the first transistor group are NMOS transistors;
The gate array structure further includes:
A tap provided proximate to the first transistor group for connection to a source voltage metal line;
And a tap provided close to the second transistor group for connection to a drain voltage metal line.
[0021]
A manufacturing method of a gate array structure according to the invention of claim 11
A manufacturing method of a gate array structure formed on a semiconductor substrate,
Identical basis having transistors each having a gate electrode and one or more gate connection strips formed on the substrate and electrically connected to selected gate electrodes of two or more of the transistors Forming an array of cells in the core region of the gate array structure;
Patterning the gate connection strip to maintain an electrical connection between at least two of the selected gate electrodes;
The plurality of transistors each include a first transistor group including transistors having a first gate width and a first conductive characteristic, and each of the plurality of transistors having a second gate width substantially equal to the first gate width and the first gate width. A second transistor group comprising transistors having a second conductivity characteristic opposite to the first conductivity characteristic, and transistors each having a third gate width narrower than the first and second gate widths and having the first conductivity characteristic A third transistor group comprising: gates disposed in parallel with the first axis, and the transistors of the third transistor group are all configured with the first axis. And a gate disposed parallel to a second axis substantially perpendicular to the first axis.
[0022]
A manufacturing method of a gate array structure according to the invention of claim 12
The method of manufacturing a gate array structure according to claim 11,
Forming the same basic cell array is forming the same basic cell having a polysilicon gate electrode connected integrally with a polysilicon gate connection strip;
A manufacturing method of a gate array structure according to the invention of claim 13
The method of manufacturing a gate array structure according to claim 11,
The step of forming an array of the same basic cells is a step of forming a first transistor group including four transistors and a second transistor group including four transistors. .
[0023]
A method for manufacturing a gate array structure according to the invention described in claim 14 comprises:
The method of manufacturing a gate array structure according to claim 13,
The step of forming an array of the same basic cells includes a plurality of basic units in which the first and second transistor groups each include at least one transistor set including two transistors connected in series sharing a source / drain region. A step of forming a cell,
A manufacturing method of a gate array structure according to the invention of claim 15 includes:
The method of manufacturing a gate array structure according to claim 13,
The step of forming the array of the same basic cells includes a first tap adjacent to the first transistor group including four transistors and a second tap adjacent to the second transistor group including four transistors. One of the first and second taps is provided for connection to a power supply voltage supply line, and the other of the first and second taps is provided for connection to a ground voltage supply line. A step of forming a plurality of basic cells.
[0024]
A method for manufacturing a gate array structure according to the invention of claim 16 comprises:
The method for manufacturing a gate array structure according to claim 15 further comprises:
Forming a first metal coating layer covering a portion of the core region;
Patterning the first metallization layer to form electrical connections between at least some of the transistors, and
A method for manufacturing a gate array structure according to the invention of claim 17 comprises:
The method of manufacturing a gate array structure according to claim 16, further comprising:
Forming a second metal coating layer covering at least a portion of the first metal coating layer;
Patterning said second metallization layer to provide further electrical connections.
[0025]
A method for manufacturing a gate array structure according to the invention of claim 18 comprises:
The method of manufacturing a gate array structure according to claim 16, further comprising:
Producing an integrated circuit from the array of basic cells.
[0026]
The gate array structure according to the invention of claim 19 is
In a gate array structure formed on a semiconductor substrate and having an array of the same basic cells in the core region,
Each of the basic cells is
A plurality of transistor means each including a gate electrode at a first level above the substrate and below any metallization layer;
Means for connecting selected gate electrodes of two or more of said transistor means disposed at said first level;
The plurality of transistor means includes a first transistor means group each having a first gate width and having a first conductivity characteristic, and each of the first transistor means having a second gate width substantially equal to the first gate width and the first gate width. A second transistor means group having a second conductive characteristic opposite to the conductive characteristic; and a second transistor means group each having a third gate width substantially narrower than the first and second gate widths and having the first conductive characteristic. 3 transistor means groups, all the transistor means of the first and second transistor means groups have gates arranged parallel to the first axis, and all the transistor means of the third transistor means group are the first transistor means group. And a gate disposed parallel to a second axis substantially perpendicular to the axis.
[0027]
The gate array structure according to the invention of claim 20 is
The gate array structure of claim 19,
The gate electrode and the means for connecting the selected gate electrode are both made of polysilicon and connected together as one piece,
The gate array structure according to the invention of claim 21 is
The gate array structure of claim 19,
The first group of transistor means is composed of four n-type transistor means, and the second group of transistor means is composed of four p-type transistor means.
[0028]
The gate array structure according to the invention of claim 22
The gate array structure of claim 21,
The four n-type transistor means are grouped into two n-type transistor means groups including two n-type transistor means connected in series, and the four p-type transistor means are two connected in series. It is classified into two p-type transistor means groups including p-type transistor means,
The gate array structure according to the invention of claim 23 is
The gate array structure of claim 19,
The transistor means is at least partially covered with a silicide layer.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, some embodiments of the present invention will be described with reference to FIGS.
First, the arrangement of basic cells will be described. FIG. 4 illustrates a basic cell 100 formed on a p-type semiconductor substrate and comprising a first transistor group 102 that is an NMOS device and a second transistor group 104 that is a PMOS device. The PMOS transistors of the second transistor group 104 are formed in the n-well 106. In addition, four polysilicon gate electrodes 110a, 110b, 110c, and 110d for the first transistor group 102 and four polysilicon gate electrodes 111a, 111b, 111c, and 111d for the second transistor group 104 are illustrated. ing. These individual gate electrodes are electrically connected to other gate electrodes through “unprogrammed” polysilicon gate connection strips 108a, 108b, 108c of the master slice. These will later be programmed (patterned) to form some “first level” circuit routing. Of course, this is not possible with the basic cell 50 shown in FIG. 2 in which the bifurcated polysilicon head gate electrode is not connected to the adjacent gate electrode.
[0030]
In general, the gate connection strip used in the present invention is formed in the same process as the polysilicon gate electrode, such that the gate electrode and the gate connection strip form one continuous monolithic structure. In other words, the gate connection strips 108a, 108b, and 108c are integrally connected to the first and second group transistors 102 and 104.
[0031]
Looking at the first transistor group 102, the first MOS transistor includes an n-type source / drain diffusion region 112, an n-type source / drain diffusion region 114, a polysilicon gate electrode 110d, and a gate dielectric (shown). Not). The second transistor of the first transistor group 102 is connected in series with the first transistor via the source / drain region 114 that also acts as the source / drain region of the second transistor. The second transistor also includes an n-type source / drain diffusion region 120, a gate 110c, and a gate dielectric (not shown) under the gate electrode. Further, the second transistor group 102 includes a second transistor set connected in series. In particular, the third transistor includes an n-type drain diffusion region 122, an n-type source diffusion region 124, a gate 110b, and a gate dielectric (not shown) under the gate electrode. The source / drain region 124 functions as the source / drain region of the fourth transistor of the first transistor group 102. The transistor also includes an n-type source diffusion region 125, a gate 110a, and a gate dielectric (not shown) under the gate electrode.
[0032]
A tap contact 130 exists between two sets of transistor sets of two transistors and is a high density p-type dopant in the p-type silicon substrate to act as an ohmic contact with a ground voltage (Vss) supply line (not shown). Has an area. As described above with reference to FIG. 1, the Vss line formed from the first metallization layer provides ground contacts for a number of individual basic cells in the basic cell column of the gate array. That is, due to the interconnection with tap 130, the Vss line provides a contact to ground. A corresponding tap 131 is provided in the second transistor group for connection to a supply voltage (Vdd) supply line (not shown). Like tap 130, tap 131 includes a region in the n-well where the dopant concentration (in this case, n-type) is increased to provide an ohmic connection to the Vdd line.
[0033]
The second transistor group 104 is a mirror image of the first transistor group 102 but has the opposite conductivity characteristics (conductivity type) (ie, the second group of transistors are PMOS transistors). The first transistors in the second group 104 include a p-type source / drain diffusion region 133, a p-type source / drain diffusion region 135, a gate 111d, and a gate dielectric (not shown) under the gate electrode. The second transistors in the second group 104 include a diffusion region 137 as a source / drain region, a p-type source / drain diffusion region 135, a gate 111b, and a gate dielectric (not shown) under the gate electrode. Accordingly, the first and second transistors of the second group 104 are connected in series via the diffusion region 135.
[0034]
The second transistor set in the second group 104 includes a p-type source / drain diffusion region 140, a p-type source / drain diffusion region 142, a gate 111b, and a third transistor having a gate dielectric (not shown) under the gate electrode. It has. The diffusion region 142 also acts as the source / drain region of the fourth transistor, so that the third and fourth transistors of the second group 104 are connected in series. The fourth transistor of the second group 104 also includes a diffusion region 144 and a gate 111a.
[0035]
In the first transistor group 102, the gate connection strips 108a, 108b provide an electrically conductive connection between the gates 110a, 110b, 110c, 110d. Similarly, in the second transistor group 104, the gate connection strips 108c, 108d provide an electrically conductive connection between the gates 111a, 111b, 111c, 111d. It should be noted that the gate connection strip 108b also provides an electrical connection between the gate electrodes of the first transistor group 102 and the second transistor group 104. This is possible because, as can be seen in the figure, the gate connection strip extends over the entire length of the basic cell and is arranged substantially perpendicular to the gate electrode. Further, if the basic cell 100 is considered to be one of the basic cells repeated in the row and column directions in the gate array structure, the gate electrodes of the transistors in adjacent basic cells are also connected by the gate connection strips 108a, 108b, 108c. It will be connected as one. As will become apparent in the following description, these features allow the gate connection strip to be patterned such that the gate connection strip forms routing lines between the various gate electrodes in the basic cell.
[0036]
In a particularly preferred embodiment of the invention, the NMOS gate electrode of the basic cell has a gate width of about 5.6 μm and the PMOS gate electrode has a gate width of about 6.2 μm (in the gate connection strip). Does not contain any material). The gate lengths of the p-type and n-type transistors are both 0.40 μm. As is well known by those skilled in the art, the metal lines interconnecting the gate arrays are arranged with reference to the grid space on the basic cells. The grid space in the embodiment of the present invention is about 1.4 μm long and about 1.4 μm wide, which allows an increase in routing density. One basic cell has dimensions of 13 grid points (18.20 μm) in the X direction and 8 grid points (11.20 μm) in the Y direction. Therefore, the area of the basic cell region is 203.84 μm. ² It is.
[0037]
The power supply voltage and the ground voltage are supplied to the circuit formed on the basic cell by the respective metal-1 metal lines (not shown) passing through the upper portions of the taps 131 and 130 and extending from the upper end to the lower end of the basic cell. Is done. In particular, in the first transistor group 102, the ground voltage supply line (Vss) is in contact with the tap 130 and in contact with various source / drain diffusion regions. Further, in the second transistor group 104, the power supply voltage supply line (Vdd) is in contact with the tap 131 and in contact with various source / drain diffusion regions. Such power supply and ground voltage supply lines generally form line segments that span the entire column direction of the basic cells in the gate array, as illustrated by lines 21 and 22 in FIG. Should be understood. In a particularly preferred embodiment of the invention, the power supply voltage supply line Vdd and the ground voltage supply line Vss have a width of about 1.4 μm, and the Vdd metal line is connected to a power source of 3.3V. .
[0038]
FIG. 5 illustrates an embodiment of the second invention according to the present invention. A basic cell 150 formed on a p-type semiconductor substrate includes an n-type first transistor group 154, a p-type second transistor group 152, and an n-type third transistor group 171. The second transistor group 152 has four PMOS transistors formed in the n well 164. The first transistor group 154 has four NMOS transistors, and the third transistor group 171 has two or more NMOS transistors. The third group of transistors differs from the first and second groups of transistors primarily in terms of their dimensions and orientation within the basic cell 150. As shown in the figure, the transistors of the third group 171 have gate widths substantially narrower than the gate widths of the transistors of the first group 154 and the second group 152. This basic cell arrangement is particularly useful in the field of circuit design where one or more small transistors can be used.
[0039]
The gate connection strip 160 (a) connects the transistors of the first transistor group 154 and the second transistor group 152, and the basic cell is arranged along a direction perpendicular to the gate width direction of the transistors in these groups. 150 extends to both edges. The gate connection strip 160 (b) connects the transistors of the second transistor group 152 to each other and connects to the adjacent basic cells on the three sides of the basic cell 150. The gate connection strip 160 (c) connects the four transistors in the first group 154 to each other and to two adjacent basic cells. Finally, the gate connection strip 174 connects the third transistor group 171 to each other, and connects to one basic cell and the gate connection strip 160 (c) that are close to each other.
[0040]
Looking at the first transistor group 154, the first MOS transistor has an n-type source / drain diffusion region 168, an n-type source / drain diffusion region 176, and a gate 156. The second transistor of the first group is connected in series with the first transistor via a source / drain region 176 that also acts as the source / drain of the second transistor. The second transistor has an n-type source / drain diffusion region 178 and a gate 177. Further, the first transistor group 154 has a second transistor set connected in series. In particular, the third transistor includes an n-type source / drain diffusion region 179, an n-type source / drain diffusion region 181, and a gate 180. Source / drain region 181 also acts as the drain for the first group of fourth transistors. The transistor includes an n-type source / drain diffusion region 182 and a gate 195.
[0041]
Finally, in the first transistor group 154, a tap contact 161 comprising a high concentration p-type dopant region in the n-type silicon substrate to act as an ohmic contact for the ground voltage supply line Vss (not shown), Exists between two sets of two transistors. In the second transistor group 152, a corresponding tap 162 is provided to contact a power supply voltage supply line Vdd (not shown). Similar to tap 161, tap 162 has a high dopant concentration region (in this case n-type) in the n-well to provide an ohmic contact to the Vdd line.
[0042]
The transistors in the second transistor group 152 are mirror images of the transistors in the first transistor group 154, but have opposite conductivity characteristics (ie, the transistors in the second transistor group are p-type transistors). . In particular, the first transistor in the second transistor group 152 includes a p-type source / drain diffusion region 166, a p-type source / drain diffusion region 183, and a gate 158. The second transistor of the second transistor group includes a diffusion region 183 as a source / drain region, a gate 184, and a p-type source / drain diffusion region 185. Therefore, the first transistor and the second transistor of the second group 152 are connected in series via the diffusion region 183. The second transistor set in the second transistor group 152 includes a third transistor having a p-type source / drain diffusion region 186, a gate 187, and a p-type source / drain diffusion region 188. The diffusion region 188 also acts as the source / drain region of the fourth transistor, so that the third transistor and the fourth transistor of the second transistor group 152 are connected in series. The fourth transistor of the second transistor group 152 also includes a gate 189 and a source / drain diffusion region 190.
[0043]
Finally, the third transistor group 171 includes a first NMOS transistor having source / drain diffusion regions 170 and 191 divided by a gate 172. The third group 171 also includes a second NMOS transistor having source / drain diffusion regions 192 and 194 divided by the gate 193. The gates of the two NMOS transistors of the third group 171 are connected to each other by a gate connection strip 174.
[0044]
There are various differences between the transistors of the third group 171 and the transistors of the first group 154 and the second group 152. For example, unlike the transistors in the first group 154 and the second group 152, the two transistors in the third group 171 are not connected in series. Further, the transistors of the third group 171 are arranged substantially perpendicular to the transistors of the first group 154 and the second group 152. That is, all the transistors in the first group 154 and the second group 152 have gates arranged in parallel to the first axis, and all the transistors in the third group 171 are substantially in relation to the first axis. And a gate arranged parallel to a second axis perpendicular to the first axis. As a result, a space is secured in the basic cell. If the third group 171 transistors are not used in the integrated circuit, the top space of these transistors serves as a convenient routing path for the conductors on the first metallization layer. Thus, in some designs, all or most circuit level routing is completed on the first metal layer (metal-1). This reduces the need for a metal jumper on the second metal layer (metal-2), thus increasing the usefulness of routing at the second metal layer level.
[0045]
The relatively small size transistors of the third group 171 also have certain advantages. Since the gate capacity of the relatively small transistors is smaller than the gate capacity of the relatively large transistors in the first group 154 and the second group 152, the capacity of the circuit is reduced as long as such transistors can be used. Furthermore, since a relatively small transistor uses a relatively small current, a wide current wiring is not necessary, and a space is secured on the obtained integrated circuit, and the usable gate density is dramatically increased.
[0046]
In a particularly preferred embodiment of the invention, the gate electrodes (eg, gate electrode 156) of the transistors in the first transistor group 154 have a gate width of about 5.7 μm, whereas the second transistor group 152 The transistor gate electrode (eg, gate electrode 158) has a gate width of about 5.9 μm. The gate electrodes (eg, gate electrode 193) of the transistors in the third transistor group 171 have a narrower gate width and a gate width of only about 3.65 μm. In the embodiment of the present invention, the gate width does not include the width of the polysilicon head (for example, the polyheads 160a and 160b). The gate lengths of the p-type and n-type transistors are both 0.40 μm. As is well known by those skilled in the art, the metal lines interconnecting the gate arrays are arranged with reference to the grid space on the basic cells. The grid space in the embodiment of the present invention has a length of about 1.4 μm and a width of about 1.4 μm, and one basic cell has 15 grid points (21 μm) in the X direction and 8 grid points (11 in the Y direction). .20 μm). Accordingly, the area of the basic cell region is 235.20 μm. ² It is.
[0047]
FIG. 6 illustrates the gate array after the gate connection strip has been patterned to form a first level (ie, polysilicon level) routing between selected gate electrodes in four adjacent basic cells 200. Fig. 4 illustrates a first level of a master slice. Although no specific circuit is shown, the polysilicon structure illustrated in FIG. 6 is similar to flip-flops, multiplexers, or other circuits that require multiple transistors interconnected through multiple basic cells. Shall be.
[0048]
The array section 200 is composed of four representative basic cells 202, 204, 206 and 208. In each basic cell, an NMOS transistor is provided on the left side and a PMOS transistor is provided on the right side. Thus, for example, in the basic cell 202, the polysilicon gate electrodes 218, 220, 222, 224 are used for NMOS transistors, and the polysilicon gate electrodes 210, 212, 214, 216 are used for PMOS transistors.
[0049]
Assume that the circuit design requires a connection between the gate electrode 224 and the gate electrode 220. Polysilicon connection line 232 may be formed by patterning one gate connection strip. Similarly, if the circuit design requires a connection between the gate electrode 224 and the gate electrode 216, the polysilicon connection line 226 can be formed from another gate connection strip. As is known, these routings are usually performed at the metal-1 layer. By moving such routing to the polysilicon layer, for example, chip-level routing can be freed up and the available gate density can be increased.
[0050]
If connections are required between the gate electrodes of adjacent basic cells, according to the invention, these connections can be made at the polysilicon level. For example, polysilicon lines 205, 234, 236 and 237 provide their connection. Of course, not all connections to the gate electrode are completed at the polysilicon level. In such a case, the vertical connection needs to be extended from metal-1 to the underlying polysilicon level. In accordance with the applied design rules, a polysilicon “port region” may be formed from the gate connection strip to ensure sufficient space for these contacts. Such ports are illustrated in polysilicon structures 228, 230, 238, 239, 240, 241, 242, and 243. In particular, it should be noted that the polyport 240 is formed on a polysilicon line connecting the NMOS transistor gate electrode and the PMOS transistor gate electrode of the basic cell 204.
[0051]
Unlike the basic cell shown in FIG. 2, there is no unnecessary polysilicon head on the left side of the basic cell. Accordingly, the gate capacitance can be reduced, and as a result, the performance can be improved.
[0052]
Next, an embodiment of the invention relating to a method for manufacturing a programmable polysilicon gate array according to the present invention will be described. A general process flow 300 for fabricating a gate array integrated circuit according to the present invention is illustrated in FIG. The process starts at 301 and at step 302 a master slice of the gate array is formed. The master slice has a programmable polysilicon level as illustrated in the basic cell of FIG. After this structure is formed, in step 304, the polysilicon level (specifically, a collection of polysilicon gate connection strips) is used to form several polysilicon level routing lines between the gate electrodes of adjacent transistors. Is patterned. Next, in step 306, a silicide layer is deposited over the patterned polysilicon and diffusion regions to improve the conductivity of the resulting structure. Finally, in step 308, one or more suitable metallization layers are formed and patterned. The process ends at 309.
[0053]
This process has in particular two distinct features. First, the step of patterning polysilicon to form polysilicon level routing (step 304) has not been employed in conventional gate array fabrication processes. This step requires an additional mask and etch step, but has the advantage that some circuit level metal lines and associated vertical contacts can be eliminated. At least this frees up space on the metal-1 layer for additional routing. It also eliminates the need for an additional metallization layer and the cost of saving far exceeds that of the polysilicon patterning process. Another notable feature in process 300 is the silicide step 306. This step improves the conductivity of individual MOS device components.
[0054]
As is the case with many IC manufacturing processes, the gate array manufacturing process according to the present invention can generally be divided into front-end and back-end steps. The front end steps typically include the steps necessary to form the actual transistor elements such as source / drain regions, gates, and isolation regions. The back-end step typically includes the processing steps necessary to configure the circuit by wire-connecting the various transistors formed by the front-end step. When applied to a gate array, the front end step results in an array in which the basic cells having the transistor arrangement described above are repeatedly arranged. In contrast, the back-end step provides a wire connection to form a circuit from the basic cell transistors.
[0055]
In the front end step, an element active region is first formed and electrically insulated on the single crystal semiconductor substrate. Thereafter, a gate oxide film may be formed on the substrate. A polysilicon film is then formed on the gate oxide, typically by chemical vapor deposition (CVD). The resulting polysilicon film is doped, masked and etched by ion implantation to form gate electrodes and gate connection strips. The resulting gate electrode / gate connection strip arrangement is characterized by an array of repeating basic cells. For example, an array or the like having a basic cell arrangement, each according to the design shown in FIG. After the gate is formed, source / drain regions are formed by two or more ion implantation steps. Of these ion implantation steps, at least one step forms the n-type source / drain region of the NMOS device, and some other steps form the p-type source / drain region of the PMOS device. In general, the NMOS transistor region is masked during p-type ion implantation and the PMOS transistor region is masked during n-type ion implantation. In this method, the p-type transistor group and the n-type transistor group are separately formed in the basic cell. At this point, step 302 of process 300 is complete. Then, as described above, the polysilicon layer is patterned at step 304.
[0056]
After the source / drain regions are formed, a silicide layer (silicide) is formed on the polysilicon and substrate surfaces to form lower resistance regions (step 306). Finally, for example, a passivation film of borophosphosilicate glass (BPSG) is deposited over the entire gate array structure. At this point, the front end step is finished and the gate array structure is partially wired by the patterning of step 304.
[0057]
The back end step in the present invention will be described. These steps are shown collectively as step 308 of process 300. First, a contact mask (contact mask) for defining a region in contact with an element on a substrate and an associated gate electrode is formed on the passivation film. Subsequently, the passivation film is etched (typically by plasma etching) to form a vertical contact hole through the passivation film to level 1 (underlying substrate and polysilicon layer). A diffusion boundary film (sometimes called a glue film) made of a titanium nitride film or the like is formed at this point in order to protect the device element near the contact hole from the entry of metal atoms during the subsequent deposition of the metal film. . In some processes, the contact hole is plugged with a tungsten plug according to procedures known to those skilled in the art. Regardless of whether or not the tungsten plug is formed, the deposition of the first metal film is performed. The first (and all subsequent) metal films may be formed from various industrially used metals such as aluminum (Al), aluminum copper (AlCu), or aluminum silicon copper (AlSiCu). These films are conventionally deposited by sputtering known to those skilled in the art.
[0058]
After the first metal film is deposited, the first metal film is patterned to form lines that connect the various device elements. The exact line placement is determined by the specific ASIC design. Patterning is performed by first depositing a mask, such as a photoresist, and then exposing the photoresist to light to define a pattern of metal lines to be generated in a subsequent etching step. Then, the first metal film under the mask is etched by a plasma etching process such as reactive ion etching (RIE).
[0059]
After the first metal film is etched, the photoresist is removed and an insulating film is deposited over the first metal film to insulate the metal film from the subsequent metal film (ie, the second metal film). In general, an oxide film or borophosphosilicate glass is used as an insulating film, but other insulating films such as a nitride film and a polyimide film (formed by spin coating) can also be used. The insulating coating is then planarized using any suitable technique. After the insulating film is formed and planarized, a via mask is formed on the surface of the insulating film as described above. The via mask defines a via or region in which an interconnection between the first metal film and the second metal film is to be formed. Then, in order to form an actual via in the insulating film, plasma assist etching is performed again. After the via is formed in the insulating film, the next metal film (metal-2) is deposited and patterned as described above.
[0060]
In some cases, further metal film formation and patterning may be required to complete the wire connection of the gate array IC. However, as a result of practicing the present invention, since at least some of the interconnects are completed at the polysilicon level, the overall number of metallization layers is usually less than expected.
[0061]
As mentioned above, although this invention was demonstrated based on some embodiment of an invention, it should be understood that a various change improvement is possible in the range which does not deviate from the meaning of this invention. The above-described embodiments and examples are used for explaining the present invention, and should not be used for interpreting the present invention in any way.
[0062]
【The invention's effect】
As described above, according to the programmable polysilicon gate array structure and the manufacturing method thereof according to the present invention, several routing lines are formed from the metal coating layer of the gate array to the polysilicon layer (first metal coating layer) on the substrate. Therefore, the circuit level routing amount at the first and / or second metallization layer level can be reduced. As a result, the number of lines dedicated to circuit routing on the metallization layer can be reduced, and more area can be utilized for chip level routing on the metallization layer. In addition, the number of steps in the gate array manufacturing process can be reduced.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a conventional gate array master slice having an array of repetitive basic cells in a core region.
FIG. 2 is a configuration diagram showing transistor arrangement for a conventional basic cell used in a gate array.
FIG. 3 is an explanatory diagram showing how a composite circuit (in this case, a flip-flop) can require a jumper in a second metallization layer to wire connect the circuit.
FIG. 4 is a schematic diagram of a basic cell according to the present invention comprising 8 transistors having 8 gate electrodes connected to other gate electrodes by polysilicon connection strips.
FIG. 5 is a schematic diagram of a basic cell according to the present invention comprising 10 transistors having 10 gate electrodes connected to other gate electrodes by polysilicon connection strips.
FIG. 6 is an illustration showing how a polysilicon connection strip is programmed (patterned) to provide circuit level routing at the polysilicon level of the gate array.
7 is a flowchart of a method of forming a gate array IC from the basic cell in FIG.
[Explanation of symbols]
10 ... Gate array structure
12 ... Input / output (I / O) pad
14 ... I / O slot
16 ... Vss metal wire
18 ... Vdd metal wire
20 ... Basic cell
21, 22 ... 1st metal wire
23 ... Semiconductor chip
24 ... Core region
50 ... Basic cell
52 ... p-type transistor surface
53a, 53b, 53c, 53d ... p-type transistor
54 ... n-type transistor surface
55a, 55b, 55c, 55d ... n-type transistor
56 ... n-well
57 ... Drain diffusion region
58a, 58b ... polysilicon contact (polyhead)
59 ... Source diffusion region
64 ... p-type substrate
66 ... Gate electrode
67 ... Polysilicon gate electrode
68, 69 ... tap
80, 82a, 82b, 82c, 82d ... basic cells
81a, 81b ... contact
84, 86, 88, 90, 92 ... Jumper
100 ... Basic cell
102. First transistor group
104 ... Second transistor group
106 ... n-well
108a, 108b, 108c... Polysilicon gate connection strip
110a, 110b, 110c, 110d ... polysilicon gate electrode
111a, 111b, 111c, 111d ... gate
112, 114, 120, 122, 124, 125 ... n-type source / drain diffusion regions
130, 131 ... tap
133, 135, 137, 140, 142, 144... P-type source / drain diffusion region
150 ... Basic cell
152 ... Second transistor group
154: First transistor group
171 ... Third transistor group
156, 158, 172, 177, 180, 184, 187, 189, 193, 195 ... gate
160 (a), 160 (b), 160 (c), 174... Gate connection strip
161, 162 ... Tap contacts
164 ... n-well
166, 183, 185, 186, 188, 190 ... p-type source / drain diffusion region
168, 176, 178, 179, 181, 182, 170, 191, 192, 194 ... n-type source / drain diffusion regions
200 ... Array section
202, 204, 206, 208 ... basic cells
210, 212, 214, 216, 218, 220, 222, 224 ... polysilicon gate electrode
205, 226, 232, 234, 236, 237 ... polysilicon connection lines
228, 230, 238, 239, 240, 241, 242, 243 ... port area
Vss ... Ground voltage supply line
Vdd: power supply voltage supply line

Claims (23)

In a gate array structure formed on a semiconductor substrate and having an array of the same basic cells in a core region, each basic cell is formed on the substrate with a plurality of transistors each having a gate electrode. And one or more gate connection strips electrically connected to selected gate electrodes of two or more of the transistors, each of the plurality of transistors having a first gate width, and a first transistor group consisting of transistors having a first conductivity characteristics, with each having a second gate width is equal to the previous SL first gate width, a transistor of a second conductivity characteristics opposite to the first conductivity characteristics A second transistor group, each having a third gate width narrower than the first and second gate widths; A third transistor group consisting of transistors having the first conductive characteristics, and the transistors of the first and second transistor groups all have gates arranged parallel to the first axis, transistor has a gate which is arranged parallel to the second axis of vertical and to all the first axis, a gate array structure.   2. The gate array structure according to claim 1, wherein the gate connection strip is formed of the same material as the selected gate electrode and is integrally connected to the selected gate electrode.   3. The gate array structure according to claim 2, wherein the gate connection strip and the gate electrode are made of polysilicon. In a gate array structure according to claim 1, at least one of said gate connection strip, a gate array structure which is directly arranged vertical in respect to at least one of said gate electrode.   2. The gate array structure according to claim 1, wherein the first transistor group includes four transistors, and the second transistor group includes four transistors.   2. The gate array structure according to claim 1, wherein the transistors of the first transistor group include at least one transistor set including two transistors connected in series sharing a source / drain region.   2. The gate array structure according to claim 1, further comprising a tap for connecting a power supply voltage supply line or a ground voltage supply line to a transistor having the first conductive property in the vicinity.   2. The gate array structure according to claim 1, wherein the second transistor group includes at least one transistor set including two transistors connected in series sharing a source / drain region.   2. The gate array structure according to claim 1, further comprising a tap for connecting a power supply voltage supply line or a ground voltage supply line to the adjacent second transistor group.   2. The gate array structure according to claim 1, wherein the transistors of the first transistor group are NMOS transistors, and the gate array structure is further adjacent to the first transistor group for connection to a source voltage metal line. And a tap provided adjacent to the second transistor group for connection to a drain voltage metal line. A method of manufacturing a gate array structure formed on a semiconductor substrate, each having a gate electrode, and electrically formed with the selected gate electrode of two or more of the transistors formed on the substrate Forming in the core region of the gate array structure an array of identical basic cells having one or more gate connection strips connected thereto, and electrical connection between at least two of the selected gate electrodes and a step of patterning the gate connection strip so as to maintain the connection, the plurality of transistors, a first transistor group consisting of transistors having a first conductivity characteristics with each having a first gate width, are each opposite to the first conductivity characteristics and having a second gate width is equal to the previous SL first gate width A second transistor group composed of transistors having second conductivity characteristics; and a third transistor group composed of transistors each having a third gate width narrower than the first and second gate widths and having the first conductivity characteristics; the a, has a first and a gate which is arranged parallel to all transistor has a first axis of the second transistor group, the second of the third transistor group of the transistor is for all the first axis vertical A method for manufacturing a gate array having gates arranged parallel to two axes.   12. The method of manufacturing a gate array structure according to claim 11, wherein the step of forming the array of the same basic cells includes the step of forming the same basic cells having polysilicon gate electrodes connected integrally with the polysilicon gate connection strip. A method for manufacturing a gate array structure.   12. The method of manufacturing a gate array structure according to claim 11, wherein the step of forming the array of the same basic cells includes a first transistor group including four transistors and a second transistor including four transistors. A method of manufacturing a gate array structure, which is a step of forming a transistor group.   14. The method of manufacturing a gate array structure according to claim 13, wherein the step of forming an array of the same basic cells includes two first and second transistor groups connected in series sharing a source / drain region. A method of manufacturing a gate array structure, which is a step of forming a plurality of basic cells each having at least one transistor set including the above transistors.   14. The method of manufacturing a gate array structure according to claim 13, wherein the step of forming the array of the same basic cells includes a first tap adjacent to the first transistor group including four transistors and four transistors. And a second tap adjacent to the second transistor group, wherein one of the first and second taps is provided for connection to a power supply voltage supply line, and the other of the first and second taps is A method of manufacturing a gate array structure, which is a step of forming a plurality of basic cells provided for connection to a ground voltage supply line.   The method of manufacturing a gate array structure according to claim 15, further comprising: forming a first metallization layer covering a part of the core region; and forming an electrical connection between at least some transistors. And patterning the first metal cover layer.   17. The method of manufacturing a gate array structure according to claim 16, further comprising: forming a second metal coating layer covering at least a part of the first metal coating layer; and providing the second metal coating layer to provide further electrical connection. Patterning the metal coating layer. A method of manufacturing a gate array structure.   17. The method for manufacturing a gate array structure according to claim 16, further comprising a step of manufacturing an integrated circuit from the array of basic cells. In a gate array structure formed on a semiconductor substrate and having an array of the same basic cells in the core region, each of the basic cells is above the substrate, and any a plurality of transistors data including the gate electrode at the first level than the metallization layer present beneath the disposed first level, two or more of said transistors other selected means for connecting the gate electrode with the door, said plurality of transistors data, together with each having a first transistor tag loop and, second gate width correct equal and each said first gate width having a first conduction characteristic has a first gate width wherein a second transistor tag loop having a second conductivity characteristics opposite to the first conductive characteristics, the third gate narrow small than each said first and second gate width And a third transistor tag loop having a first conductive property and having a transistor capacitor of the first and second transistor tag loop has a gate which is arranged parallel to the first axis all, the third gate array structure having a gate which is arranged parallel to the transistor motor all the first axis and the vertical of the second axis of transistor tag loop.   20. The gate array structure according to claim 19, wherein the gate electrode and the means for connecting the selected gate electrode are both made of polysilicon and are integrally connected to each other. In a gate array structure of claim 19, wherein the transistor capacitor of the first group is composed et or four n-type transistors data, transistor capacitor of the second group of four p-type transistors data that consists of the gate Array structure. In a gate array structure of claim 21, wherein the four n-type transistors data is classified into two n-type transistors tag loop comprising two n-type transistors motor connected in series, the four p-type transistor capacitor gate array structure which is classified into two p-type transistor tag loop comprising two p-type transistor capacitor connected in series. In a gate array structure of claim 19, wherein the transistor capacitor, a gate array structure in which at least a portion of which is covered by a silicide layer.

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