JP4076330B2 - Digital broadcast receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a terrestrial digital television broadcast receiver and a terrestrial digital audio broadcast receiver.
[0002]
[Prior art]
Currently, digitalization of television broadcasts and radio broadcasts is being promoted, and terrestrial digital television broadcasts and terrestrial digital audio broadcasts will be realized following the digitization of satellite broadcasts.
[0003]
The broadcasting system of terrestrial digital television broadcasting and terrestrial digital audio broadcasting is described in “Technical Conditions for Terrestrial Digital Television Broadcasting” in the report of the Digital Broadcasting System Committee of the Telecommunications Technology Council, and the Telecommunications Technology Deliberation. It is common to comply with the “technical conditions of terrestrial digital audio broadcasting system” reported at the meeting.
[0004]
FIG. 18 is a diagram illustrating an example of the above-described general broadcasting terrestrial digital television broadcast receiver. This block diagram is illustrated in, for example, the Journal of the Institute of Image Information and Media Studies Vol. 54, no. 6). p. 905 corresponds to a detailed representation of the configuration of the OFDM (Orthogonal Frequency Division Multiplex) receiver described in 905.
[0005]
In FIG. 18, the digital television broadcast tuner 1 receives the band of the broadcast channel desired by the user from the VHF band (about 90 MHZ to about 200 MHZ) or the UHF band (about 470 MHZ to about 770 MHZ). And a received wave is converted into IF (Intermediate Frequency) which makes 57 MHz a center frequency, for example.
[0006]
The output of the SAW filter 2 is given to the IF conversion circuit 3, and the IF conversion circuit 3 converts the IF into a local frequency having a center frequency of, for example, 4.1 MHz.
[0007]
The low-pass filter 4 removes harmonic noise and the like mixed in the received signal from the output signal of the IF conversion circuit 3 in a processing stage after the SAW filter 2. The output of the low-pass filter 4 is converted into a digital signal by the AD converter 6 and input to the time domain processing unit 8 in the OFDM demodulation unit 7.
[0008]
The time domain processing unit 8 is a block that performs signal processing on the received wave expressed in the time domain. For example, timing detection or adjustment is performed from a guard interval signal in the received wave. Further, the time domain processing unit 8 performs synchronization control of a VCXO (Voltage Controlled Xtal Oscillator) 19 using the detected timing of the received wave. The control signal to the VCXO 19 is converted from a digital signal to an analog signal by the DA converter 18. The VCXO 19 can generate a 32.5 MHz clock signal that is four times the terrestrial digital television broadcasting standard clock (512/63) MHZ = 8.12 MHZ.
[0009]
The clock signal CLK1 generated by the VCXO 19 is input to the time domain processing unit 8, the FFT (Fast Fourier Transform) unit 9, the frequency domain processing unit 10, the deinterleaving unit 11, and the error correction / decoding block 12, and the operation of each unit Become a clock.
[0010]
The output of the time domain processing unit 8 is given to the FFT unit 9, and is subjected to fast Fourier transform processing for calculating the frequencies and signal strengths of a plurality of carriers (carrier waves) included in the output to be a frequency domain signal. .
[0011]
The output of the FFT unit 9 is given to the frequency domain processing unit 10. In the frequency domain processing unit 10, a shift in the frequency of the carrier in the received wave converted into the frequency domain is detected and corrected using a PLL circuit or the like. Further, the frequency domain processing unit 10 also performs OFDM synchronization / differential demodulation processing.
[0012]
The output of the frequency domain processing unit 10 is given to the deinterleaving unit 11 where deinterleaving processing is performed. The output of the deinterleaving unit 11 is given to the error correction / decoding block 12, where error correction processing and decoding processing are performed. In the above regulations concerning digital television broadcasting, it is possible to set up to three layers as a transmission method, and the depth of deinterleaving, the convolutional coding rate in error processing, etc. are set in each layer. It is possible to convert correspondingly.
[0013]
In the error correction / decoding block 12, a TS (Transport Stream) packet is first reproduced by the TS packet reproduction unit 13 (TS packet reproduction means). For reproduction of TS packets, the input signal is accumulated for each layer as described above until it corresponds to the data amount of one TS packet, and when the accumulation of signals for one TS packet is completed, the signal is output to the Viterbi composite unit 14 at the subsequent stage. During a period until data for one TS packet is accumulated, a null (invalid) TS packet is created and output. Normally, an information bit indicating that the TS packet is a TS null packet is inserted into the TS null packet, and meaningless data such as “0” is inserted into the data area.
[0014]
The Viterbi decoding unit 14 performs Viterbi decoding of the input signal and performs error correction. The Viterbi-decoded data is converted from symbols to bytes and output to the byte deinterleave unit 15 (byte deinterleave means).
[0015]
The byte interleaving unit 15 performs convolutional byte deinterleaving independently on the input TS packet for each layer. The TS null packet created by the TS packet reproduction unit 13 is not deinterleaved.
[0016]
The output of the byte deinterleave unit 15 is given to the energy despreading unit 16 (energy despreading means). The energy despreading unit 16 also performs energy despreading independently on the input TS packet for each layer in the same manner as the byte deinterleaving unit 15, and the energy despreading is performed on the TS null packet created by the TS packet reproduction unit 13. Do not process.
[0017]
The TS packet output from the energy despreading unit 16 is given to an RS (Reed Solomon) decoding unit 17 (RS decoding means). The RS decoding unit 17 can correct an error of up to 8 bytes for the input TS packet.
[0018]
FIG. 19 is a diagram showing an internal circuit block of the RS decoding unit 17 of FIG. The data of the input TS packet is given to the memory 106 and the syndrome calculation circuit 100 (syndrome calculation means). The memory 106 delays the data until the RS decoding process is completed and the packet data can be corrected. The syndrome calculation circuit 100 calculates an error syndrome value from the data of the input TS packet.
[0019]
The error syndrome calculated by the syndrome calculation circuit 100 is given to the error position polynomial calculation unit 101 and the error value polynomial calculation unit 102 in the error calculation circuit 107 (error calculation means). The error position polynomial calculation unit 101 calculates a polynomial in which a value indicating an error position is a solution using a given error syndrome. On the other hand, the error value polynomial calculation unit 102 calculates a polynomial whose error magnitude (numerical value) is a solution using the given error syndrome. The error position polynomial calculated by the error position polynomial calculation unit 101 is output to the error position calculation unit 103. The error value polynomial calculated by the error value polynomial calculation unit 102 is given to the error value calculation unit 104.
[0020]
The error position calculation unit 103 calculates a solution of a given error position polynomial, and specifies an error position. Error position information which is a solution of the error position polynomial is given to the error numerical value calculation unit 104.
[0021]
Based on the error value polynomial given from the error value polynomial calculation unit 102 and the error value information given from the error position calculation unit 103, the error value calculation unit 104 determines the error magnitude for each of the plurality of error positions. Is calculated. The calculated error magnitude (error numerical value) and error position information are output to the error correction output circuit 105.
[0022]
The error correction output circuit 105 reads the delayed data from the memory 106 and corrects and outputs the data in the TS packet indicated by the error position information calculated in the previous stage according to the calculated error value.
[0023]
[Problems to be solved by the invention]
The terrestrial digital television broadcast and terrestrial digital audio broadcast receivers configured as described above include a plurality of byte deinterleaving units 15 and energy despreading units 16 in the error correction / decoding block 12. It is necessary to perform processing independently for the transmission layer.
[0024]
In addition, since it is necessary to make the processing independent for each of the plurality of hierarchies, one set of byte deinterleave unit and energy despreading unit is provided for each hierarchy. In terrestrial digital television broadcasting, a total of three hierarchies are provided. In order to perform processing, as shown in FIG. 18, three sets of interleave units and energy despreading units in parallel are required.
[0025]
By the way, the TS packets output from the TS packet reproducing unit 13 are time-multiplexed and output one TS packet at a time. FIG. 20 is a diagram illustrating an example of a TS packet that is time-multiplexed and output from the TS packet reproducing unit 13. As shown in FIG. 20, TS null packets 203 and 205 for time adjustment are multiplexed in the time multiplexed output of TS packets mixed with TS packets 201, 202, and 204 belonging to any layer.
[0026]
For this reason, during the period when TS packets belonging to any layer are output from the TS packet reproduction unit 13, the interleave unit and the energy despreading unit for TS packets belonging to layers other than the corresponding layer perform processing. There is no need.
[0027]
Further, during the period in which the TS null packet is output from the TS packet reproducing unit 13, all circuit parts arranged in the subsequent stage of the TS packet reproducing unit 13, that is, the byte deinterleave unit 15, the energy despreading unit 16, The RS decoding unit 17 does not need to perform processing.
[0028]
For example, in the terrestrial digital broadcasting system, the TS null packet output period from the TS packet reproduction unit 13 may correspond to about 7/8 of the entire period when there are many periods.
[0029]
Normally, an enable signal is used to stop and execute such processing, and the processing operation is stopped by the enable signal during a period when processing is not required. However, even if the processing operation is stopped by the enable signal, if the clock signal is supplied, the power is consumed in each circuit unit even during the period when the processing is not required. It does not mean that power is used effectively.
[0030]
In this way, even during a period in which processing is not necessary, since the clock is supplied, there is a problem that wasteful power is consumed, and there is room for reducing the power.
[0031]
Further, the syndrome calculation circuit 100 in the RS decoding unit 17 can determine whether or not error data is included in the received TS packet, but when it is determined that the TS packet does not include an error, The subsequent error value polynomial calculation unit 102, error position polynomial calculation unit 101, error value calculation unit 104, and error position calculation unit 103 do not need to perform any processing. Since it is determined that there is no error in this way, there is a problem that wasteful power is consumed during a period in which processing is not necessary, and there is room for reducing power.
[0032]
The present invention has been made to solve the above-described problem, and is a digital broadcast receiver capable of reducing power during a period in which a TS null packet is reproduced or a period in which RS decoding processing is not required. And a digital broadcast receiver capable of reducing the power of circuits that do not need to process other layers during the period when TS packets of different layers are being reproduced. Yes.
[0033]
[Means for Solving the Problems]
In order to achieve the above-described object, a digital broadcast receiving apparatus according to the present invention described in claim 1 is configured to perform error correction and demodulation on a demodulated output of a received signal of digital television broadcast or digital audio broadcast by receiving a clock signal. An error correction / decoding block for performing decoding processing is provided. The error correction / decoding block is a digital broadcast receiving apparatus having TS packet reproducing means for classifying and reproducing TS packets having a plurality of layers for each layer. When the TS packet to be reproduced is a TS null packet for time adjustment, the TS packet reproducing means outputs a null TS signal indicating the packet, and is subsequent to the TS packet reproducing means in the error correction / decoding block. Installed on the supply path of the clock signal used in at least one circuit part, and receive the null TS signal When, characterized in that it comprises a clock signal supply stop means for stopping the supply of the clock signal.
[0034]
Further, in the present invention described in claim 2, in the digital broadcast receiving apparatus described in claim 1, the error correction / decoding block includes RS decoding means for performing error correction of the data of the reproduced TS packet, and the clock The signal supply stop means is installed on a supply path of a clock signal used in at least a part of the RS decoding means.
[0035]
According to a third aspect of the present invention, in the digital broadcast receiving apparatus according to the second aspect, the RS decoding unit includes a syndrome calculation unit that calculates an error syndrome, and the clock signal supply stop unit is included in the syndrome calculation unit. It is installed on the supply path of the clock signal used.
[0036]
According to a fourth aspect of the present invention, in the digital broadcast receiving apparatus according to the second aspect, the RS decoding means includes error calculation means for calculating an error position and an error numerical value, and the clock signal supply stop means is an error signal. It is provided on a supply path of a clock signal used for the calculation means.
[0037]
According to a fifth aspect of the present invention, in the digital broadcast receiver according to the second aspect, the RS decoding means includes a memory for delaying the data of the reproduced TS packet until an error value is calculated. The clock signal supply stop means is installed on a supply path of a clock signal used for the memory.
[0038]
According to a sixth aspect of the present invention, in the digital broadcast receiving apparatus according to the first aspect, the error correction / decoding block performs byte deinterleaving for performing byte deinterleaving on the reproduced TS packet data for each layer. And the clock signal supply stopping means is installed on a clock signal supply path used in the byte deinterleaving means.
[0039]
According to a seventh aspect of the present invention, in the digital broadcast receiving apparatus according to the first aspect, the error correction / decoding block performs energy despreading for performing energy despreading on the reproduced TS packet data for each layer. And the clock signal supply stop means is installed on a clock signal supply path used in the energy despreading means.
[0040]
According to another aspect of the present invention, there is provided a digital broadcast receiving apparatus for performing error correction and decoding processing on a demodulated output of a received signal of digital television broadcast or digital audio broadcast by receiving a clock signal. / Decoding block, and the error correction / decoding block is a digital broadcast receiving device having TS packet reproducing means for classifying and reproducing TS packets having a plurality of hierarchies for each layer, wherein the TS packet reproducing means The TS layer signal indicating the layer of the TS packet to be reproduced is output, and the error correction / decoding block has byte deinterleaving means for performing byte deinterleaving for each layer on the reproduced TS packet data. Installed on the supply path of the clock signal used in each layer of the means and receives the TS layer signal. If you, supplies a clock signal only to the hierarchy specified by TS layer signals, for another layer, characterized in that it comprises a clock signal supply selecting means for stopping the supply.
[0041]
According to a ninth aspect of the present invention, there is provided a digital broadcast receiving apparatus for performing error correction and decoding processing on a demodulated output of a received signal of digital television broadcast or digital audio broadcast by receiving a clock signal. / Decoding block, and the error correction / decoding block is a digital broadcast receiving device having TS packet reproducing means for classifying and reproducing TS packets having a plurality of hierarchies for each layer, wherein the TS packet reproducing means The TS layer signal indicating the layer of the TS packet to be reproduced is output, and the error correction / decoding block includes energy despreading means for performing energy despreading on the reproduced TS packet data for each layer, and energy despreading When it is installed on the supply route of the clock signal used in each layer in the means and receives the TS layer signal, It supplies a clock signal only to the hierarchy specified by S-layer signal, for other hierarchical characterized in that it comprises a clock signal supply selecting means for stopping the supply.
[0042]
According to a tenth aspect of the present invention, there is provided a digital broadcast receiving apparatus for performing error correction and decoding processing on a demodulated output of a received signal of a digital television broadcast or a digital audio broadcast by receiving a clock signal. / Decoding block, and the error correction / decoding block includes an RS decoding unit that performs error correction of the reproduced TS packet data, a syndrome calculating unit that calculates an error syndrome, and an error that calculates an error position and an error numerical value. A digital broadcast receiving device comprising a calculating means, wherein the syndrome calculating means outputs a zero error signal indicating that there is no error in the received packet data when the calculated syndrome value is zero error; It is installed on the clock signal supply path used in the calculation means and receives the error zero signal. When, characterized in that it comprises a clock signal supply stop means for stopping the supply of the clock signal.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on illustrated embodiments.
Embodiment 1 FIG.
In the digital broadcast receiving apparatus according to the present embodiment, when a TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the clock signal supplied to the syndrome calculation circuit in the RS decoding unit is stopped. It was configured as follows.
[0044]
FIG. 1 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to Embodiment 1 of the present invention.
In the description based on FIG. 1 below, portions having the same functions as those of the error correction / decoding block in the conventional digital broadcast receiving apparatus shown in FIG. 18 and FIG. The description is omitted.
[0045]
The error correction / decoding block 12 in FIG. 1 is different from the error correction / decoding block configuration in the conventional digital broadcast receiving apparatus shown in FIG. 18 in that the TS packet reproduction unit 13a outputs a TS null packet. In the middle of the path where the null TS signal is output and the clock signal CLK1 generated by the VCXO 19 is supplied to the syndrome calculation circuit 100 in the RS decoding unit 17, the clock signal is supplied when the null TS signal is received. The clock signal supply stop unit 300 (clock signal supply stop unit) to be stopped is provided, and the clock signal CLK2 is supplied from the clock signal supply stop unit 300 when the null TS signal is not received. Other configurations are the same as those of the error correction / decoding block in the conventional digital broadcast receiving apparatus shown in FIG.
[0046]
In order to explain that the TS packet reproducing unit 13a outputs a null TS signal when outputting a TS null packet, the configuration and operation of the TS packet reproducing unit 13a will be described.
[0047]
FIG. 2A shows the configuration of the TS packet reproducing unit 13a, and FIG. 2B shows how the reproduced TS packet and TS null packet are output.
[0048]
As shown in FIG. 2 (a), the TS packet reproduction unit 13a includes a hierarchy (1) TS buffer 401 and a hierarchy (2) TS buffer 402 that accumulate received data for each of the (1) to (3) layers. The layer (3) TS buffer 403 and the TS buffer 401 to 403 are switched and output as a regenerated TS packet, and when the accumulated data in each TS buffer 401 to 403 is not sufficient, There is provided switching means 404 for outputting a TS null packet without outputting it from the TS buffer.
[0049]
As shown in FIG. 2 (b), each TS buffer 401 to 403 accumulates input received data for each layer of (1) to (3) layers, and all TS packet data of a certain layer is accumulated. In this case, all the data in the hierarchy is read from the buffer at a predetermined timing (for example, the 204-byte interval T = 1, 2, 3,... Output. Further, when all the data for the TS packet of the hierarchy is not accumulated in any buffer, the TS packet reproducing unit 13a creates and outputs a TS null (invalid) packet during the period. The TS null packet is not a TS packet composed of received data, but an invalid packet inserted for time adjustment.
[0050]
The TS packet output from the TS packet reproducing unit 13a is Viterbi-decoded by the Viterbi decoding unit 14 and supplied to the byte deinterleaving unit 15 and the energy despreading unit 16 provided independently for each layer. The energy despreading process is performed and output to the RS decoding unit 17.
[0051]
Next, in the present embodiment, when a null TS signal is received, the clock signal supply stop unit 300 stops the supply of the clock to the syndrome calculation circuit 100 in the RS decoding unit 17, but this is possible. The reason will be described.
[0052]
First, in the RS decoding unit 17, the input TS packet data is distributed and supplied to the memory 106 and the syndrome calculation circuit 100. That is, the input data remains in the memory 106 even if the syndrome calculation circuit 100 disappears.
[0053]
The syndrome calculation circuit 100 calculates an error syndrome from the input TS packet data. The syndrome value calculated by the syndrome calculation circuit 100 is an all-zero value, which is a syndrome value when there is no error when the input TS packet does not contain an error, and is all-zero when an error is included. A value other than the value is output to the error calculation circuit 107 in the next stage.
[0054]
By the way, when a null TS signal is received, that is, when a TS null packet created by the TS packet reproducing unit 13a is input to the RS decoding unit 17, error data is included in the TS null packet. Since there is no possibility, the syndrome calculated by the syndrome calculation circuit 100 is an all-zero value that is a syndrome value when there is no error. Therefore, when a null TS signal is received, that is, when a TS null packet is input, it is not necessary to calculate the syndrome value by the syndrome calculation circuit 100, and it is always zero.
[0055]
Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproduction unit 13a transmits the null TS signal NTS to the clock signal supply stop unit 300, and the clock signal supply stop unit 300 sends it to the syndrome calculation circuit 100. Stop the supplied clock signal. By stopping the supply of the clock signal, all processing operations are temporarily stopped (interrupted) in the syndrome calculation circuit 100.
[0056]
FIG. 3 is a flowchart showing the operation of stopping the clock signal supply in the first embodiment.
The clock signal supply stopping unit 300 determines whether or not the null TS signal NTS is received from the TS packet reproducing unit 13a, and the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet. Whether or not (S1).
[0057]
When the clock signal supply stopping unit 300 determines that the TS packet output from the TS packet reproducing unit 13a is a TS null packet (S1: YES), the supply of the clock signal CLK2 to the syndrome calculation circuit 100 is stopped. (S2).
[0058]
On the other hand, when the clock signal supply stopping unit 300 determines that the TS packet output from the TS packet reproducing unit 13a is not a TS null packet but a valid TS packet (S1: NO), the clock signal supply stopping unit 300 supplies the syndrome calculation circuit 100 to the syndrome calculation circuit 100. The clock signal CLK2 is supplied (S3).
[0059]
As described above, in this embodiment, when the null TS signal NTS is received, by stopping the supply of the clock signal, all the processing operations of the syndrome calculation circuit 100 can be stopped and the power consumption can be suppressed. . Therefore, the power consumption of the syndrome calculation circuit 100 during the output period of the TS null packet, which is a ratio of 7/8 at the maximum in the output period of the reproduced TS packet as described above, can be reduced. Overall power consumption can be greatly reduced.
[0060]
Embodiment 2. FIG.
In Embodiment 1 described above, when a TS null packet is output from the TS packet reproduction unit in the error correction / decoding block, the clock signal supplied to the syndrome calculation circuit in the RS decoding unit is stopped. In the second embodiment described below, when a TS null packet is output from the TS packet reproduction unit, the clock signal supplied to the error calculation circuit in the RS decoding unit is stopped.
[0061]
FIG. 4 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the second embodiment of the present invention.
The difference between the error correction / decoding block 12 in FIG. 4 and the configuration of the error correction / decoding block in the digital broadcast receiving apparatus of the first embodiment shown in FIG. 1 is that the clock signal CLK1 generated by the VCXO 19 is the RS decoding unit 17. A clock signal supply stop unit 301 (clock signal supply stop unit) that stops the supply of the clock signal CLK3 when a null TS signal is received is provided in the middle of the path supplied to the error calculation circuit 107 in the circuit. The clock signal CLK3 is supplied from the clock signal supply stop unit 301 when not received. Other configurations are the same as those of the error correction / decoding block in the digital broadcast receiving apparatus of the first embodiment shown in FIG.
[0062]
Further, as described above with reference to FIG. 19, the error calculation circuit 107 is an error calculation circuit in the RS decoding unit 12, and the error value included in the input TS packet is determined based on the syndrome value output from the syndrome calculation circuit 100. The position and the magnitude (numerical value) of the error are calculated.
[0063]
Similar to the first embodiment described above, also in this embodiment, when the TS null packet created by the TS packet reproducing unit 13a is input to the RS decoding unit 17, the TS null packet includes error data. Therefore, the error position and error value calculated by the error calculation circuit 107 are all zero values that are values when there is no error. Therefore, when a TS null packet is input, it is not necessary to calculate the error position and the error numerical value.
[0064]
Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproduction unit 13a transmits the null TS signal NTS to the clock signal supply stop unit 301, and the clock signal supply stop unit 301 sends the error calculation circuit 107 to the error calculation circuit 107. Stop the supplied clock signal. By stopping the supply of the clock signal, in the error calculation circuit 107, all processing operations are temporarily stopped (interrupted).
[0065]
FIG. 5 is a flowchart showing the operation of stopping the supply of the clock signal in the second embodiment.
The clock signal supply stopping unit 301 determines whether or not the null TS signal NTS is received from the TS packet reproducing unit 13a, and the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet. Whether or not (S11).
[0066]
When the clock signal supply stopping unit 301 determines that the TS packet output from the TS packet reproducing unit 13a is a TS null packet (S11: YES), the supply of the clock signal CLK3 to the error calculation circuit 107 is stopped. (S12).
[0067]
On the other hand, when the clock signal supply stopping unit 301 determines that the TS packet output from the TS packet reproducing unit 13a is not a TS null packet but a valid TS packet (S11: NO), the clock signal supply stopping unit 301 proceeds to the error calculation circuit 107. The clock signal CLK3 is supplied (S13).
[0068]
As described above, in this embodiment, when the null TS signal NTS is received, by stopping the supply of the clock signal, all processing operations of the error calculation circuit 107 can be stopped and the power consumption can be suppressed. . Therefore, the power consumption of the error calculation circuit 107 during the output period of the TS null packet, which is a ratio of a maximum of 7/8 in the output period of the TS packet reproduced as described above, can be reduced. Overall power consumption can be greatly reduced.
[0069]
Embodiment 3 FIG.
In the first embodiment described above, when a TS null packet is output from the TS packet reproduction unit in the error correction / decoding block, the clock signal supplied to the syndrome calculation circuit in the RS decoding unit is stopped, and the embodiment 2, the clock signal supplied to the error calculation circuit in the RS decoding unit is stopped, but in the third embodiment described below, when a TS null packet is output from the TS packet reproducing unit, the RS decoding is performed. The clock signal supplied to the internal memory is stopped.
[0070]
FIG. 6 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the third embodiment of the present invention.
The error correction / decoding block 12 in FIG. 6 differs from the error correction / decoding block configuration in the digital broadcast receiving apparatus of the first embodiment shown in FIG. 1 in that the clock signal CLK1 generated by the VCXO 19 is the RS decoding unit 17. A clock signal supply stop unit 302 (clock signal supply stop means) for stopping supply of the clock signal CLK4 when a null TS signal is received is provided in the middle of a path supplied to the internal memory 106, and the null TS signal is not received. In this case, the clock signal CLK4 is supplied from the clock signal supply stop unit 302. Other configurations are the same as those of the error correction / decoding block in the digital broadcast receiving apparatus of the first embodiment shown in FIG.
[0071]
The memory 106 according to the present embodiment is for delaying and outputting the TS packet reproduced from the received data in the RS decoding unit 17, and when the supply of the clock signal CLK4 is stopped, It is assumed that the TS packet is allowed to pass without delay (write / accumulate / read is not performed).
[0072]
In the first and second embodiments described above, when the TS null packet created by the TS packet reproducing unit 13a is input to the RS decoding unit 17, the TS null packet does not include error data. Although the error position and error value calculated by the error calculation circuit 107 have been used to be all-zero values that are values when there is no error, in this embodiment, the TS null packet is known data. It is not necessary to intentionally store and delay in the memory 106, and the fact that the TS decoding unit 17 can reproduce the TS null packet is used.
[0073]
Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproduction unit 13a transmits the null TS signal NTS to the clock signal supply stop unit 302 and supplies the null signal TSS to the memory 106 by the clock signal supply stop unit 302. Stop the clock signal. By stopping the supply of the clock signal, all processing operations are temporarily stopped (interrupted) in the memory 106, and the TS null packet is reproduced by the error correction output circuit 105.
[0074]
FIG. 7 is a flowchart showing the operation of stopping the clock signal supply in the third embodiment.
The clock signal supply stopping unit 302 determines whether or not the null TS signal NTS is received from the TS packet reproducing unit 13a, and the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet. It is determined whether or not (S21).
[0075]
When the clock signal supply stop unit 302 determines that the TS packet output from the TS packet reproduction unit 13a is a TS null packet (S21: YES), the clock signal supply stop unit 302 stops the supply of the clock signal CLK4 to the memory 106 ( S22).
[0076]
On the other hand, when the clock signal supply stopping unit 302 determines that the TS packet output from the TS packet reproducing unit 13a is not a TS null packet but a valid TS packet (S21: NO), the clock signal supply to the memory 106 is determined. The signal CLK4 is supplied (S23).
[0077]
As described above, in the present embodiment, when the null TS signal NTS is received, the supply of the clock signal is stopped, so that the processing operation of the delay (write / accumulate / read) in the memory 106 is stopped and the power consumption is reduced. Can be suppressed. Therefore, the power consumption of the memory 106 during the output period of TS null packets, which is a ratio of 7/8 at the maximum in the output period of TS packets reproduced as described above, can be reduced. Power consumption can be greatly reduced.
[0078]
Embodiment 4 FIG.
In the first to third embodiments described above, when a TS null packet is output from the TS packet reproduction unit in the error correction / decoding block, the clock signal supplied to some circuits in the RS decoding unit is stopped. However, in the fourth embodiment described below, when a TS null packet is output from the TS packet reproduction unit, the clock signal supplied to the byte deinterleave unit in the error correction / decoding block is stopped. Configured.
[0079]
FIG. 8 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the fourth embodiment of the present invention.
The difference between the error correction / decoding block 12 in FIG. 8 and the configuration of the error correction / decoding block in the digital broadcast receiving apparatus of the first embodiment shown in FIG. 1 is that the clock signal CLK1 generated by the VCXO 19 is a byte deinterleave unit. 15 is provided with a clock signal supply stop unit 303 (clock signal supply stop means) for stopping the supply of the clock signal CLK5 when a null TS signal is received in the middle of the path supplied to 15, and a clock when the null TS signal is not received. The clock signal CLK5 is supplied from the signal supply stop unit 303. Other configurations are the same as those of the error correction / decoding block in the digital broadcast receiving apparatus of the first embodiment shown in FIG.
[0080]
Further, for example, in the terrestrial digital broadcasting system, since up to three layers can be used, the convolution coding rate, the interleave length, etc. can be set independently for each layer. It is necessary to provide a plurality (three sets) of processing blocks for each layer. Therefore, the byte deinterleave unit 15 of this embodiment is also composed of a plurality of hierarchies such as the first hierarchy: (1) to the third hierarchy: (3) shown in FIG. 8, but the clock signal CLK5 is as follows. In this case, the clock signal supply stop unit 303 supplies the signals to each layer at once.
[0081]
The TS packets output from the TS packet reproducing unit 13a are time-multiplexed for each TS packet, and TS packets belonging to a plurality of layers are not output at the same time. Therefore, for each layer of the byte deinterleave unit 15, It is also conceivable to control the supply of the clock signal, but this point will be described in Embodiment 6 described later.
[0082]
As in the first and second embodiments described above, when a TS null packet created by the TS packet reproduction unit 13a is input to the byte deinterleave unit 15, this TS null packet does not include error data. Therefore, it is not necessary to perform deinterleaving in the byte deinterleaving unit 15.
[0083]
Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproduction unit 13a transmits the null TS signal NTS to the clock signal supply stop unit 303, and the clock signal supply stop unit 303 causes the byte deinterleave unit 15 to transmit. The clock signal CLK5 supplied to is stopped. By stopping the supply of the clock signal CLK5, all processing operations are temporarily stopped (interrupted) in the byte deinterleave unit 15, and the TS packet deinterleaves the byte deinterleave unit 15. The process passes through without being processed, and is input to the energy despreading unit 16.
[0084]
FIG. 9 is a flowchart showing the operation of stopping the clock signal supply in the fourth embodiment.
The clock signal supply stopping unit 303 determines whether or not the null TS signal NTS is received from the TS packet reproducing unit 13a, and the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet. Whether or not (S31).
[0085]
When the clock signal supply stop unit 303 determines that the TS packet output from the TS packet reproduction unit 13a is a TS null packet (S31: YES), the clock signal supply stop unit 303 supplies the clock signal CLK5 to the byte deinterleave unit 15. Stop (S32).
[0086]
On the other hand, when the clock signal supply stopping unit 303 determines that the TS packet output from the TS packet reproducing unit 13a is not a TS null packet but a valid TS packet (S31: NO), the byte deinterleaving unit 15 Is supplied with the clock signal CLK5 (S33).
[0087]
As described above, in the present embodiment, when the null TS signal NTS is received, the supply of the clock signal is stopped to stop the deinterleaving processing operation in the byte deinterleaving unit 15 and to pass the data as it is. Power consumption can be suppressed. Therefore, the power consumption of the byte deinterleave unit 15 during the output period of the TS null packet, which is a maximum ratio of 7/8 in the output period of the TS packet reproduced as described above, can be reduced. The power consumption of the entire apparatus can be greatly reduced.
[0088]
Embodiment 5. FIG.
In Embodiment 4 described above, when a TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the clock signal supplied to the byte deinterleave unit in the error correction / decoding block is stopped. However, the fifth embodiment described below is configured to stop the clock signal supplied to the energy despreading unit in the error correction / decoding block.
[0089]
FIG. 10 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the fifth embodiment of the present invention.
The difference between the error correction / decoding block 12 in FIG. 10 and the configuration of the error correction / decoding block in the digital broadcast receiving apparatus in the fourth embodiment shown in FIG. 8 is that the clock signal CLK1 generated by the VCXO 19 is an energy despreading unit. 16 is provided with a clock signal supply stop unit 304 (clock signal supply stop unit) for stopping the supply of the clock signal CLK6 when a null TS signal is received, and a clock when the null TS signal is not received. The clock signal CLK6 is supplied from the signal supply stop unit 304. Other configurations are the same as those of the error correction / decoding block in the digital broadcast receiving apparatus of the fourth embodiment shown in FIG.
[0090]
Further, for example, in the terrestrial digital broadcasting system, up to three layers can be used, and the convolution coding rate, the interleave length, and the like can be independently set for each layer by the byte deinterleaving unit 15 in the previous stage. Therefore, the energy despreading unit 16 also needs to provide a plurality (three sets) of processing blocks for each layer. Therefore, the energy despreading unit 16 of the present embodiment is also composed of a plurality of hierarchies such as the first hierarchy: (1) to the third hierarchy: (3) shown in FIG. In the figure, the clock signal supply stopping unit 304 supplies the data to each layer in a lump.
[0091]
The TS packets output from the TS packet reproducing unit 13a are time-multiplexed for each TS packet, and TS packets belonging to a plurality of layers are not output at the same time. It is also conceivable to control the supply of the clock signal, but this point will be described in Embodiment 7 to be described later.
[0092]
As in the first and second embodiments described above, when the TS null packet created by the TS packet reproduction unit 13a is input to the energy despreading unit 16, the TS null packet does not include error data. Therefore, it is not necessary to perform energy despreading by the energy despreading unit 16.
[0093]
Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproduction unit 13a transmits the null TS signal NTS to the clock signal supply stop unit 304, and the clock signal supply stop unit 304 causes the energy despreading unit 16 to transmit. The clock signal CLK6 supplied to is stopped. By stopping the supply of the clock signal CLK6, in the energy despreading unit 16, all processing operations are temporarily stopped (interrupted), and the TS packet causes the energy despreading unit 16 to reverse the energy. The signal is passed through without being spread and input to the RS decoder 17.
[0094]
FIG. 11 is a flowchart showing the operation of stopping the clock signal supply in the fifth embodiment.
The clock signal supply stopping unit 304 determines whether or not the null TS signal NTS is received from the TS packet reproduction unit 13a, and the reproduced TS packet output from the TS packet reproduction unit 13a is a TS null packet. Whether or not (S41).
[0095]
When the clock signal supply stopping unit 304 determines that the TS packet output from the TS packet reproduction unit 13a is a TS null packet (S41: YES), the clock signal supply stopping unit 304 supplies the clock signal CLK6 to the energy despreading unit 16. Stop (S42).
[0096]
On the other hand, when the clock signal supply stopping unit 304 determines that the TS packet output from the TS packet reproducing unit 13a is not a TS null packet but a valid TS packet (S41: NO), the energy despreading unit 16 Is supplied with the clock signal CLK6 (S43).
[0097]
As described above, in the present embodiment, when the null TS signal NTS is received, the supply of the clock signal is stopped, thereby stopping the energy despreading processing operation in the energy despreading unit 16 and allowing the data to pass as it is. , Power consumption can be suppressed. Accordingly, the power consumption of the energy despreading unit 16 during the output period of the TS null packet, which is a ratio of 7/8 at the maximum in the output period of the TS packet reproduced as described above, can be reduced. The power consumption of the entire apparatus can be greatly reduced.
[0098]
Embodiment 6 FIG.
In the first to fourth embodiments described above, when a TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the clock signal supplied to some circuits in the error correction / decoding block is In the sixth embodiment described below, for example, during the period when TS packets belonging to any one of a plurality of layers transmitted according to the terrestrial digital broadcasting system are output from the TS packet reproduction unit The clock signal is supplied only to the byte deinterleave unit of the layer to which the TS packet belongs, and the clock signal supplied to the byte deinterleave unit of the remaining layer is stopped.
[0099]
FIG. 12 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the sixth embodiment of the present invention.
The difference between the error correction / decoding block 12 in FIG. 12 and the configuration of the error correction / decoding block in the digital broadcast receiving apparatus in the fourth embodiment shown in FIG. 8 is that the TS packet reproduction unit 13b first reproduces the TS packet. As in the unit 13a, a null TS signal is not transmitted, but a TS layer signal indicating which layer the TS packet to be reproduced and output is is output, and the clock signal CLK1 generated by the VCXO 19 is sent to the byte deinterleave unit 15. A clock signal supply selection unit that supplies one clock signal from among the clock signals CLK7 to 9 and stops the supply of the remaining clock signals when a TS layer signal is received in the course of the supply, according to the instruction content 305 (clock signal supply selection means), and the clock signal supply selection unit 305 provides a bar for each layer. Clock signal supply paths to with Dinner interleave 15a~15c is the point that is set separately. Other configurations are the same as those of the error correction / decoding block in the digital broadcast receiving apparatus of the fourth embodiment shown in FIG.
[0100]
In the present embodiment, the clock signal to each layer of the byte deinterleave unit 15 that has been supplied together in the fourth embodiment is sent to the first layer: (1) byte deinterleave unit 15a, the second layer: (2) Byte deinterleaving unit 15b and third layer: (3) Byte deinterleaving unit 15c are individually supplied to only one of them.
[0101]
As described above, the TS packet output from the TS packet reproducing unit 13b is time-multiplexed for each TS packet, and TS packets belonging to a plurality of layers are not output at the same time. Power supply can be further reduced by supplying the clock signal only to the layer required for the byte deinterleave units 15a to 15c individually.
[0102]
For example, when data of the TS packet of the first layer (1) created by the TS packet reproducing unit 13b is input to the byte deinterleave unit 15a, the second layer: the byte deinterleave unit 15b of (2), or Third layer: Since no TS packet data is input to the byte deinterleave unit 15c in (3), it is not necessary to perform deinterleave in the byte deinterleave unit 15b or 15c.
[0103]
Therefore, in the present embodiment, for example, during the period in which the TS packet of the first layer: (1) is output, the TS reproduction unit 13b transmits the TS layer signal TSS to the clock signal supply stop unit 305 to supply the clock signal. The stop unit 305 outputs only the clock signal CLK7 supplied to the byte deinterleave unit 15a, and stops outputting the clock signal CLK8 supplied to the remaining byte deinterleave unit 15b and the clock signal CLK9 supplied to the byte deinterleave unit 15c. Let
[0104]
By supplying only the clock signal CLK7 and stopping the other clock signals CLK8 and CLK9, the byte deinterleave unit 15a deinterleaves the TS packet data of the first layer: (1). On the other hand, in the byte deinterleaving units 15b and 15c, all processing operations are temporarily stopped (interrupted) (first layer: during the period when the TS packet of (1) is output). Is done.
[0105]
Similarly, during the period when the TS packet of the second layer: (2) is output, the clock signal CLK8 is supplied only to the byte deinterleave unit 15b, and the clock signal is supplied to the other byte deinterleave units 15a and 15c. During the period when the TS packet of the third layer: (3) is output, the clock signal CLK9 is supplied only to the byte deinterleave unit 15c and the supply of the clock signal to the other byte deinterleave units 15a and 15b is stopped. Is done.
[0106]
FIG. 13 is a flowchart showing the operation of stopping the clock signal supply in the sixth embodiment.
The clock signal supply stopping unit 305 determines the layer indicated by the TS layer signal TSS from the TS packet reproducing unit 13b, so that the reproduced TS packet output from the TS packet reproducing unit 13b is the first layer: (1 ), Second layer: TS packet of (2), or third layer: TS packet of (3) (S51).
[0107]
When the clock signal supply stopping unit 305 determines that the TS packet output from the TS packet reproducing unit 13b is the TS packet of the first layer: (1) (S51: N = 1), the byte deinterleaving unit Only the clock signal CLK7 to 15a is supplied, and the clock signals CLK8 and CLK9 are stopped (S52).
[0108]
When the clock signal supply stopping unit 305 determines that the TS packet output from the TS packet reproducing unit 13b is a TS packet of the second layer: (2) (S51: N = 2), the byte deinterleaving unit Only the clock signal CLK8 to 15b is supplied, and the clock signals CLK7 and CLK9 are stopped (S53).
[0109]
When the clock signal supply stopping unit 305 determines that the TS packet output from the TS packet reproducing unit 13b is a TS packet of the third layer: (3) (S51: N = 3), the byte deinterleaving unit Only the clock signal CLK9 to 15c is supplied, and the clock signals CLK7 and CLK8 are stopped (S54).
[0110]
That is, in this embodiment, only one TS packet is processed at a certain time, and the byte deinterleave unit used for the process is the byte deinterleave unit 15a to 15c corresponding to the TS packet hierarchy. Since it is only one of them, the clock signal is supplied only to the byte deinterleave unit of the layer where the processing is performed, and the clock signal is not supplied to the byte deinterleave unit of the other layer. ing.
[0111]
As described above, in the present embodiment, only the byte deinterleave unit of the layer (N) (N is a positive integer: 1, 2, 3,...) Required by receiving the TS layer signal TSS is clocked. By supplying a signal and stopping the clock signal to the byte deinterleave unit of the other layer, the processing operation such as deinterleave in the byte deinterleave unit of the unnecessary layer is stopped, thereby suppressing the power consumption. it can. From this, the power consumption during the output period of the TS packet reproduced as described above can be reduced to a ratio of 1/3 in the case of three layers as in the case of terrestrial digital television broadcasting, for example. Further, in the case of two layers like terrestrial digital audio broadcasting, the ratio can be reduced to ½. Therefore, in this embodiment, the power consumption of the entire digital broadcast receiving apparatus can be greatly reduced.
[0112]
Embodiment 7 FIG.
In the above-described sixth embodiment, for example, during a period in which a TS packet belonging to any one of a plurality of layers transmitted according to the terrestrial digital broadcasting system is output from the TS packet reproduction unit, the layer to which the TS packet belongs The clock signal is supplied only to the byte deinterleave unit and the clock signal supplied to the byte deinterleave unit in the remaining layer is stopped. This is the same as in the fifth embodiment with respect to the fourth embodiment. In addition, the present invention can be applied to an energy despreading unit. In the following Embodiment 7, during the period in which the TS packet belonging to any one layer is output from the TS packet reproducing unit, the clock signal is supplied only to the energy despreading unit of the layer to which the TS packet belongs, A configuration for stopping the clock signal supplied to the energy despreading unit of the hierarchy will be described.
[0113]
FIG. 14 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the seventh embodiment of the present invention.
The error correction / decoding block 12 in FIG. 14 differs from the error correction / decoding block configuration in the digital broadcast receiving apparatus in the fifth embodiment shown in FIG. 10 in that the TS packet reproduction unit 13b first reproduces the TS packet. The TS layer signal indicating which layer the TS packet to be reproduced and output is transmitted is not transmitted as in the unit 13a, and the clock signal CLK1 generated by the VCXO 19 is sent to the energy despreading unit 16. A clock signal supply selection unit that supplies one clock signal from among the clock signals CLK10 to CLK12 and stops the supply of the remaining clock signals when a TS layer signal is received in the course of the supply, according to the instruction content 306 (clock signal supply selection means), and the clock signal supply selection unit 306 provides an error for each layer. Clock signal supply path to the Energy despreader 16a~16c is the point that is set separately. Other configurations are the same as those of the error correction / decoding block in the digital broadcast receiving apparatus of the fifth embodiment shown in FIG.
[0114]
In the present embodiment, the clock signal to each layer of the energy despreading unit 16 that has been supplied together in the fifth embodiment is used as the first layer: (1) energy despreading unit 16a, the second layer: The case where the energy despreading unit 16b of (2) and the third layer: the energy despreading unit 16c of (3) are individually supplied to only one is shown.
[0115]
As described above, the TS packet output from the TS packet reproducing unit 13b is time-multiplexed for each TS packet, and TS packets belonging to a plurality of layers are not output at the same time. Power supply can be further reduced by supplying the clock signal only to the layers required individually for the energy despreading units 16a to 16c.
[0116]
For example, when the data of the TS packet of the first layer: (1) created by the TS packet reproduction unit 13b is input to the energy despreading unit 16a, the energy despreading unit 16b of the second layer: (2), or Third layer: Since no TS packet data is input to the energy despreading unit 16c in (3), it is not necessary to perform energy despreading in the energy despreading unit 16b or 16c.
[0117]
Therefore, in the present embodiment, for example, during the period when the TS packet of the first layer: (1) is output, the TS reproduction unit 13b transmits the TS layer signal TSS to the clock signal supply stop unit 306, and supplies the clock signal. Only the clock signal CLK10 supplied to the energy despreading unit 16a is output by the stop unit 306, and the output of the clock signal CLK11 supplied to the remaining energy despreading unit 16b and the clock signal CLK12 supplied to the energy despreading unit 16c is stopped. Let
[0118]
By supplying only the clock signal CLK10 and stopping the other clock signals CLK11 and CLK12, the energy despreading unit 16a performs energy despreading on the data of the TS packet of the first layer: (1). In contrast, in the energy despreading units 16b and 16c, all processing operations are temporarily stopped (interrupted) (first period: during the period when the TS packet of (1) is output). Is done.
[0119]
Similarly, during the period when the TS packet of the second layer: (2) is output, the clock signal CLK11 is supplied only to the energy despreading unit 16b, and the clock signal is supplied to the other energy despreading units 16a and 16c. During the period when the TS packet of the third layer: (3) is output, the clock signal CLK12 is supplied only to the energy despreading unit 16c and the supply of the clock signal to the other energy despreading units 16a and 16b is stopped. Is done.
[0120]
FIG. 15 is a flowchart showing the operation of stopping clock signal supply in the seventh embodiment.
The clock signal supply stopping unit 306 determines the layer indicated by the TS layer signal TSS from the TS packet reproducing unit 13b, so that the reproduced TS packet output from the TS packet reproducing unit 13b is the first layer: (1 ), Second layer: TS packet of (2), or third layer: TS packet of (3) (S61).
[0121]
When the clock signal supply stopping unit 306 determines that the TS packet output from the TS packet reproducing unit 13b is the TS packet of the first layer: (1) (S61: N = 1), the energy despreading unit Only the clock signal CLK10 to 16a is supplied, and the clock signals CLK11 and CLK12 are stopped (S62).
[0122]
When the clock signal supply stopping unit 306 determines that the TS packet output from the TS packet reproducing unit 13b is a TS packet of the second layer: (2) (S61: N = 2), the energy despreading unit Only the clock signal CLK11 to 16b is supplied, and the clock signals CLK10 and CLK12 are stopped (S63).
[0123]
When the clock signal supply stopping unit 305 determines that the TS packet output from the TS packet reproducing unit 13b is a TS packet of the third layer: (3) (S61: N = 3), the energy despreading unit Only the clock signal CLK12 to 16c is supplied, and the clock signals CLK10 and CLK11 are stopped (S64).
[0124]
That is, in this embodiment, only one TS packet is processed at a certain time, and the energy despreading unit used for the processing is the energy despreading unit 16a-c corresponding to the TS packet hierarchy. Since it is only one of them, the clock signal is supplied only to the energy despreading unit of the layer where the processing is performed, and the clock signal is not supplied to the energy despreading unit of the other layer. ing.
[0125]
As described above, in the present embodiment, only the energy despreading unit of the layer (N) (N is a positive integer: 1, 2, 3,...) Required by receiving the TS layer signal TSS is clocked. By supplying a signal and stopping the clock signal to the energy despreading unit in the other layer, it is possible to stop the despreading processing operation in the energy despreading unit in the unnecessary layer and suppress the power consumption. . From this, the power consumption during the output period of the TS packet reproduced as described above can be reduced to a ratio of 1/3 in the case of three layers as in the case of terrestrial digital television broadcasting, for example. Further, in the case of two layers like terrestrial digital audio broadcasting, the ratio can be reduced to ½. Therefore, in this embodiment, the power consumption of the entire digital broadcast receiving apparatus can be greatly reduced.
[0126]
Embodiment 8 FIG.
In Embodiment 2 described above, when a TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the TS null packet is supplied to the error calculation circuit 107 of the RS decoding unit 17 in the error correction / decoding block. Although the clock signal has been stopped, for example, it is possible to detect that an error-free TS packet has been output by the output of the syndrome calculation circuit arranged in the preceding stage of the error calculation circuit 107.
[0127]
This is because, for example, in the terrestrial digital broadcasting system, error correction processing is performed by Viterbi decoding and RS decoding, but TS packet data having errors in the TS packet reproduction unit is converted to Viterbi in the next stage. In some cases, all errors included in the received data can be corrected only by the processing of the decoding circuit. In this case, the processing of the RS decoding unit is not necessary. In such a case, since a TS null packet is not output from the TS packet reproducing unit, it is important to detect a TS packet having no error by the output of the syndrome calculation circuit.
[0128]
Therefore, in the eighth embodiment described below, the clock signal supplied to the error calculation circuit 107 is stopped during the period in which the TS null packet is detected by the syndrome calculation circuit.
[0129]
FIG. 16 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the eighth embodiment of the present invention.
In the error correction / decoding block 12 of FIG. 16, the difference from the configuration of the error correction / decoding block in the digital broadcast receiving apparatus of the second embodiment shown in FIG. Instead, the syndrome calculation circuit 100a outputs the error syndrome value calculated from the input TS packet to the clock signal supply stop unit 307. When the clock signal CLK1 generated by the VCXO 19 receives an error syndrome value that can be determined not to include error data in the course of being supplied to the error calculation circuit 107 in the RS decoding unit 17, the supply of the clock signal CLK13 is stopped. A clock signal supply stop unit 307 (clock signal supply stop unit) that receives the error syndrome value (error zero syndrome value EZS) that can be determined not to include error data. This is a point where CLK13 is supplied. Other configurations are the same as those of the error correction / decoding block in the digital broadcast receiving apparatus of the second embodiment shown in FIG.
[0130]
Similar to the second embodiment described above, even in this embodiment, when the error zero syndrome value EZS is output to the TS packet input from the syndrome calculation circuit 100a, no error data is included in the TS packet. The error position and the error numerical value calculated by the error calculation circuit 107 are all zero values that are values when there is no error. Therefore, when a TS packet having an error zero syndrome value EZS is input by the syndrome calculation circuit 100a, it is not necessary to calculate the error position and the error numerical value.
[0131]
Therefore, in the present embodiment, during the period in which the TS packet of the error zero syndrome value EZS is output from the syndrome calculation circuit 100a, the error zero syndrome value EZS is transmitted from the syndrome calculation circuit 100a to the clock signal supply stop unit 307, The signal supply stop unit 307 stops the clock signal supplied to the error calculation circuit 107. By stopping the supply of the clock signal, in the error calculation circuit 107, all processing operations are temporarily stopped (interrupted).
[0132]
FIG. 17 is a flowchart showing the operation of stopping the clock signal supply in the eighth embodiment.
The clock signal supply stop unit 307 determines whether or not the regenerated TS packet output from the syndrome calculation circuit 100a has the error zero syndrome value EZS by determining whether or not the error zero syndrome value EZS has been received from the syndrome calculation circuit 100a. It is determined whether the packet is a TS packet (S71).
[0133]
When the clock signal supply stop unit 307 determines that the TS packet output from the syndrome calculation circuit 100a is a TS packet with an error zero syndrome value EZS (S71: YES), the clock signal to the error calculation circuit 107 is determined. The supply of CLK13 is stopped (S72).
[0134]
On the other hand, when the clock signal supply stopping unit 307 determines that the TS packet output from the syndrome calculation circuit 100a is not a TS packet having the error zero syndrome value EZS but a TS packet including an error (S71: NO). Then, the clock signal CLK13 is supplied to the error calculation circuit 107 (S73).
[0135]
As described above, in the present embodiment, when the TS packet output from the syndrome calculation circuit 100a is a TS packet with the error zero syndrome value EZS, the supply of the clock signal is stopped, whereby all of the error calculation circuit 107 The processing operation can be stopped and power consumption can be suppressed. Therefore, for example, even when all errors included in the received data can be corrected only by Viterbi decoding, the processing of the error calculation circuit of the RS decoding unit can be stopped, and the error calculation circuit in the TS packet processing period can be stopped. Since power consumption can be reduced, the power consumption of the entire digital broadcast receiving apparatus can be greatly reduced.
[0136]
In each of the above-described embodiments, a method for reducing power consumption by stopping or selecting clock supply to each individual circuit is described. However, a method for each individual circuit described in each embodiment is described. It is also possible to implement in any combination.
[0137]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0138]
According to the digital broadcast receiving apparatus of claim 1, the clock signal supplied to at least one circuit of the error correction / decoding block is stopped during the period in which the TS null packet is output from the TS packet reproducing unit. Therefore, during the input period of TS null packets that do not need to be processed, all processing operations of the circuit are stopped, power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving apparatus can be reduced. Can do.
[0139]
According to the digital broadcast receiving apparatus of the second aspect, the clock signal supplied to the RS decoding unit is stopped during the period in which the TS null packet is output from the TS packet reproducing unit. During the input period of unnecessary TS null packets, all processing operations of the RS decoding unit can be stopped, power consumption can be suppressed, and power consumption of the entire digital broadcast receiving apparatus can be reduced.
[0140]
According to the digital broadcast receiving apparatus of the third aspect, the clock signal supplied to the syndrome calculation circuit is stopped during the period in which the TS null packet is output from the TS packet reproducing unit, so that the processing is performed. During the input period of unnecessary TS null packets, all the processing operations of the syndrome calculation circuit are stopped, power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving apparatus can be reduced.
[0141]
According to the digital broadcast receiving apparatus of the fourth aspect, the clock signal supplied to the error calculation circuit is stopped during the period in which the TS null packet is output from the TS packet reproduction unit, so that the processing is performed. During the input period of unnecessary TS null packets, all processing operations of the error calculation circuit are stopped, power consumption can be suppressed, and power consumption of the entire digital broadcast receiving apparatus can be reduced.
[0142]
According to the digital broadcast receiving apparatus of the fifth aspect, the clock signal supplied to the memory is stopped during the period in which the TS null packet is output from the TS packet reproducing unit. During the input period of no TS null packet, all processing operations of the memory are stopped, power consumption can be suppressed, and power consumption of the entire digital broadcast receiving apparatus can be reduced.
[0143]
According to the digital broadcast receiver of claim 6, the clock signal supplied to the byte deinterleave unit is stopped during the period in which the TS null packet is output from the TS packet reproduction unit. During the input period of TS null packets that do not need to be performed, all processing operations of the byte deinterleave unit are stopped, power consumption can be suppressed, and power consumption of the entire digital broadcast receiving apparatus can be reduced.
[0144]
According to the digital broadcast receiving apparatus of the seventh aspect, the clock signal supplied to the energy despreading unit is stopped during the period in which the TS null packet is output from the TS packet reproducing unit. During the input period of TS null packets that do not need to be performed, all processing operations of the energy despreading unit are stopped, power consumption can be suppressed, and power consumption of the entire digital broadcast receiving apparatus can be reduced.
[0145]
According to the digital broadcast receiving apparatus of claim 8, only the clock signal supplied to the byte deinterleave unit that byte deinterleaves the TS packet of the layer output from the TS packet reproduction unit is supplied to the other layer. Since the clock signal supplied to the byte deinterleaving unit for byte deinterleaving the TS packets of the TS is stopped, only the byte deinterleaving unit of the layer that needs to be processed operates and the layer that does not need to be processed All processing operations are stopped in the byte deinterleave unit to which the TS packet is input, power consumption can be suppressed, and power consumption of the entire digital broadcast receiving apparatus can be reduced.
[0146]
According to the digital broadcast receiving apparatus of claim 9, only the clock signal supplied to the energy despreading unit for despreading the energy of the TS packet of the layer output from the TS packet reproduction unit is supplied to the other layer. Since the clock signal supplied to the energy despreading unit that despreads the TS packet of the current is stopped, only the energy despreading unit of the layer that needs to be processed operates and the layer that does not need to be processed In the energy despreading unit to which the TS packet is input, all processing operations are stopped, power consumption can be suppressed, and power consumption of the entire digital broadcast receiving apparatus can be reduced.
[0147]
According to the digital broadcast receiving apparatus of claim 10, when the syndrome value output from the syndrome calculation circuit of the RS decoding unit is a value indicating that the input TS packet does not include an error, an error occurs. Since the clock signal supplied to the calculation circuit is stopped, all processing operations of the error calculation circuit are stopped during the period in which an error-free TS packet that does not need to be processed is input, and power consumption is reduced. The power consumption of the entire digital broadcast receiving apparatus can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an error correction / decoding block in a digital broadcast receiving apparatus according to a first embodiment of the present invention.
FIG. 2A is a diagram illustrating a configuration of a TS packet reproduction unit, and FIG. 2B is a diagram illustrating a state in which reproduced TS packets and TS null packets are output.
FIG. 3 is a flowchart showing an operation of stopping supply of a clock signal in the first embodiment.
FIG. 4 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the second embodiment of the present invention.
FIG. 5 is a flowchart showing an operation of stopping the supply of a clock signal in the second embodiment.
FIG. 6 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the third embodiment of the present invention.
FIG. 7 is a flowchart showing an operation of stopping the supply of a clock signal in the third embodiment.
FIG. 8 is a block diagram showing a configuration of an error correction / decoding block in a digital broadcast receiving apparatus according to a fourth embodiment of the present invention.
FIG. 9 is a flowchart showing an operation of stopping clock signal supply in the fourth embodiment.
FIG. 10 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the fifth embodiment of the present invention.
FIG. 11 is a flowchart showing an operation of stopping clock signal supply in the fifth embodiment.
FIG. 12 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the sixth embodiment of the present invention.
FIG. 13 is a flowchart showing the operation of stopping the clock signal supply in the sixth embodiment.
FIG. 14 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus according to the seventh embodiment of the present invention.
FIG. 15 is a flowchart illustrating an operation of stopping clock signal supply in the seventh embodiment.
FIG. 16 is a block diagram showing a configuration of an error correction / decoding block in a digital broadcast receiving apparatus according to an eighth embodiment of the present invention.
FIG. 17 is a flowchart showing an operation of stopping clock signal supply in the eighth embodiment.
FIG. 18 is a diagram illustrating an example of a general broadcasting digital terrestrial television broadcast receiver.
FIG. 19 is a diagram showing an internal circuit block of the RS decoding unit in FIG. 18;
FIG. 20 is a diagram illustrating an example of a TS packet that is time-multiplexed and output from a TS packet reproduction unit.
[Explanation of symbols]
1 tuner, 2 SAW filter, 3 IF conversion circuit, 4 low-pass filter, 6 AD converter, 7 OFDM demodulator, 8 time domain processor, 9 FFT, 10 frequency domain processor, 11 deinterleaver, 12 error correction block 13 TS packet recovery unit, 14 Viterbi decoding unit, 15 byte deinterleaving unit, 16 energy despreading unit, 17RS decoding unit, 18 DA converter, 19 VCXO (clock signal supply unit), 100 syndrome calculation circuit, 101 error position Polynomial calculation unit, 102 error value polynomial calculation unit, 103 error position calculation unit, 104 error value calculation unit, 105 error correction output circuit, 106 memory, 107 error calculation circuit, CLK1 clock signal, NTS null TS signal, TSS TS layer signal .

Claims (14)

A demodulated output of a received signal of digital television broadcast or digital audio broadcast is provided with an error correction / decoding block that receives a clock signal and performs error correction and decoding processing. The error correction / decoding block has a plurality of layers A digital broadcast receiving device having TS packet reproducing means for classifying and reproducing reproduced TS (Transport Stream) packets for each layer,
When the TS packet to be reproduced is a TS null (invalid) packet for time adjustment, the TS packet reproducing means outputs a null TS signal indicating the packet,
Installed on the supply path of the clock signal used in at least one circuit section subsequent to the TS packet reproduction means in the error correction / decoding block, and stops supplying the clock signal when the null TS signal is received A digital broadcast receiving apparatus comprising: clock signal supply stopping means for performing The error correction / decoding block has RS (Reed-Solomon) decoding means for performing error correction of the data of the reproduced TS packet,
The digital broadcast receiving apparatus according to claim 1, wherein the clock signal supply stop unit is installed on a clock signal supply path used in at least a part of the RS decoding unit. The RS decoding means includes syndrome calculating means for calculating an error syndrome,
The digital broadcast receiving apparatus according to claim 2, wherein the clock signal supply stopping unit is installed on a supply path of a clock signal used for the syndrome calculating unit. The RS decoding means includes error calculating means for calculating an error position and an error numerical value,
The digital broadcast receiving apparatus according to claim 2, wherein the clock signal supply stop unit is installed on a supply path of a clock signal used for the error calculation unit. The RS decoding means includes a memory for delaying the reproduced TS packet data until an error value is calculated,
The digital broadcast receiving apparatus according to claim 2, wherein the clock signal supply stopping unit is installed on a supply path of a clock signal used for the memory. The error correction / decoding block has byte deinterleaving means for performing byte deinterleaving on the data of the reproduced TS packet for each layer,
The digital broadcast receiving apparatus according to claim 1, wherein the clock signal supply stopping unit is installed on a clock signal supply path used by the byte deinterleaving unit. The error correction / decoding block includes energy despreading means for despreading the data of the regenerated TS packet for each layer,
The digital broadcast receiving apparatus according to claim 1, wherein the clock signal supply stopping unit is installed on a clock signal supply path used in the energy despreading unit. A demodulated output of a received signal of digital television broadcast or digital audio broadcast is provided with an error correction / decoding block that receives a clock signal and performs error correction and decoding processing. The error correction / decoding block has a plurality of layers A digital broadcast receiving apparatus having TS packet reproducing means for classifying and reproducing the TS packets that have been classified for each layer,
The TS packet reproducing means outputs a TS layer signal indicating the layer of the TS packet to be reproduced,
The error correction / decoding block has byte deinterleaving means for performing byte deinterleaving for each layer on the data of the reproduced TS packet,
Installed on the supply path of the clock signal used in each layer in the byte deinterleave means, and when receiving the TS layer signal, supply the clock signal only to the layer specified by the TS layer signal, A digital broadcast receiving apparatus comprising clock signal supply selection means for stopping supply of the hierarchy. A demodulated output of a received signal of digital television broadcast or digital audio broadcast is provided with an error correction / decoding block that receives a clock signal and performs error correction and decoding processing. The error correction / decoding block has a plurality of layers A digital broadcast receiving apparatus having TS packet reproducing means for classifying and reproducing the TS packets that have been classified for each layer,
The TS packet reproducing means outputs a TS layer signal indicating the layer of the TS packet to be reproduced,
The error correction / decoding block has energy despreading means for performing energy despreading on the data of the regenerated TS packet for each layer,
Installed on the supply path of the clock signal used in each layer in the energy despreading means, when receiving the TS layer signal, supply the clock signal only to the layer specified by the TS layer signal, A digital broadcast receiving apparatus comprising clock signal supply selection means for stopping supply of the hierarchy. A demodulated output of a received signal of a digital television broadcast or a digital audio broadcast is provided with an error correction / decoding block that receives a clock signal and performs error correction and decoding processing. The error correction / decoding block is reproduced A digital broadcast receiving apparatus comprising: a syndrome calculating means for calculating an error syndrome; and an error calculating means for calculating an error position and an error numerical value in an RS decoding means for correcting an error of data of a TS packet,
If the calculated syndrome value is zero error, the syndrome calculation means outputs a zero error signal indicating that there is no error in the received packet data,
A digital broadcast receiver comprising clock signal supply stopping means that is installed on a clock signal supply path used by the error calculation means and stops the supply of the clock signal when the error zero signal is received. . In a digital broadcast receiving apparatus that demodulates and outputs a reception signal of digital television broadcast or digital audio broadcast, the digital broadcast reception apparatus includes a step of performing error correction and decoding processing upon receiving a clock signal, and the error correction / decoding step includes a plurality of steps. A reception method for performing a process of classifying and reproducing layered TS packets for each layer,
In the TS packet reproduction process, when the TS packet to be reproduced is a TS null (invalid) packet for time adjustment, a null TS signal indicating the packet is output,
When the null TS signal is received, a process of stopping supply of a clock signal used for at least one process after the TS packet reproduction process in the error correction / decoding step is performed.
A receiving method for a digital broadcast receiving apparatus. A digital broadcast receiving apparatus that demodulates and outputs a received signal of digital television broadcast or digital audio broadcast, and has a step of performing error correction and decoding processing upon receipt of a clock signal, the error correction / The decoding step is a receiving method for performing a process of classifying and reproducing TS packets having a plurality of layers for each layer,
In the TS packet reproduction process, a TS layer signal indicating the layer of the TS packet to be reproduced is output,
In the error correction / decoding step, byte deinterleaving processing is performed on the data of the reproduced TS packet for each layer,
When the TS layer signal is received, the clock signal used in each layer in the byte deinterleaving process is clocked only in the layer specified by the TS layer signal. A lock signal is supplied, and the processing for stopping the supply is performed for other levels.
A receiving method for a digital broadcast receiving apparatus. In a digital broadcast receiving apparatus that demodulates and outputs a reception signal of digital television broadcast or digital audio broadcast, the digital broadcast reception apparatus includes a step of performing error correction and decoding processing upon receiving a clock signal, and the error correction / decoding step includes a plurality of steps. A reception method for performing a process of classifying and reproducing layered TS packets for each layer,
In the TS packet reproduction process, a TS layer signal indicating the layer of the TS packet to be reproduced is output,
In the error correction / decoding step, energy despreading processing is performed on the data of the reproduced TS packet for each layer,
When the TS layer signal is received, in the clock signal supply path used in each layer in the energy despreading process, the clock signal is supplied only to the layer specified by the TS layer signal, and for other layers Implement processing to stop supply
A receiving method for a digital broadcast receiving apparatus. A digital broadcast receiving apparatus that demodulates and outputs a received signal of a digital television broadcast or a digital audio broadcast has a step of performing error correction and decoding processing upon receipt of a clock signal, and reproduction is performed in the error correction / decoding step. A reception method for performing a process of calculating an error syndrome and performing a process of calculating an error position and an error numerical value during an RS decoding process for correcting an error of the data of the TS packet,
In the error syndrome calculation process, when the calculated syndrome value is zero error, an error zero signal indicating that there is no error in the received packet data is output,
When the error zero signal is received, a process of stopping the supply of the clock signal is performed in the supply path of the clock signal used in the error position and numerical value calculation process.
A receiving method for a digital broadcast receiving apparatus.

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