JP4078091B2 - Imaging apparatus and imaging method - Google Patents

Description

[0001]
[Prior art]
Usually, when displaying or recording a still image or a moving image captured by a solid-state imaging device such as a CCD, the optical black of the imaging device (optical black, hereinafter referred to as OB) is used as a reference for the brightness of the imaging signal. Note) levels are used. OB refers to a pixel output that is shielded from light in the light receiving pixel portion of the image sensor and does not depend on incident light.
[0002]
FIG. 4 shows an example of a device configuration of a feedback clamp system generally used in a video camera or the like in a DC component reproducing (clamping) circuit using the OB level as a black reference of an imaging signal, and main operation waveforms are shown in FIG. The operation will be briefly described.
[0003]
In FIG. 4, there is a solid-state imaging device 101 such as a CCD, for example. An imaging signal output from the imaging device 101 is input to a circuit 102 called a CDS (correlated double sampling) circuit, and reset noise is removed. After that, a predetermined offset voltage is added to the offset addition circuit 103 and the offset addition output is input to the variable amplifier 104.
[0004]
The CDS circuit 102 forms a CDS circuit that uses the predetermined reference voltage VREF input from the terminal 106 as a reference for the feedthrough portion of the imaging signal. Similarly, the variable amplifier 104 images the reference voltage VREF. This constitutes a direct current amplifier that is used as a reference for direct current signal amplification.
[0005]
The variable amplifier 104 is a gain variable means for correcting the output sensitivity variation of the CCD 101 and switching the sensitivity setting of the image pickup apparatus. Hereinafter, in order to explain the clamping operation of the image pickup apparatus simply and clearly, the gain 1 It shall be handled simply as a double.
[0006]
The amplified output signal from the variable amplifier 104 is input to an image processing / recording / display circuit (not shown) on the one hand, and is input to the sample hold circuit 107 on the other hand and reads out the OB pixel input from the terminal 109. The OB level sampled and held by the OB clamp pulse synchronized with the timing is input to the integrating amplifier 105.
[0007]
The integrating amplifier 105 has a predetermined integration time constant by a capacitor 105b and a resistor 105c, and a differential voltage (clamp error voltage) between the sampled and held OB level and a predetermined reference voltage VREF input from the terminal 106. ) Is integrated with the integration time constant, and the output (deviation amount from the voltage VREF) is input to the offset addition circuit 103 and subtracted, and negative feedback control is configured.
[0008]
FIG. 5 shows how the OB level of the output signal 11C of the variable amplifier 104 is clamped to the DC voltage level VREF and converges, and the operation waveforms of each part at that time.
[0009]
A signal waveform 11A is an output waveform of the CDS 102, and has a OB pixel output for a predetermined period for each horizontal line read from the image sensor 101, and a timing signal for sample-holding a part of this OB pixel output period. Is the OB clamp pulse 11D.
[0010]
The OB pixel output of the signal waveform 11A is maintained at a DC voltage that is relatively close to the reference voltage VREF by the action of the CDS (correlated double sampling) circuit 102. A difference component (CCD offset) from the signal component and a dark current component depending on the temperature of the image sensor are superimposed to have an offset error (usually several millimeters to several tens of millivolts).
[0011]
This offset error varies for each image sensor, and varies depending on the temperature. Then, this offset error is amplified by the variable amplifier 104 and finally outputted as the black level fluctuation VERR of the imaging signal.
[0012]
The black level fluctuation VERR is detected as a difference of the VREF voltage by the sample hold circuit 107 and the integrating amplifier 105, integrated and output as an integrated output signal 11B shown in FIG. 5, and the deviation amount of the output 11B from the voltage VREF is Subtracted from the output signal 11A of the CDS circuit 102.
[0013]
By repeating this operation for each output of the OB clamp pulse 11D, the integration output 11B and the OB pixel output of the output signal of the variable amplifier 104 converge to the reference voltage VREF as in the signal waveform 11C.
[0014]
By the way, in such a feedback type OB clamp circuit, the integration time constant in the case of integrating the black level fluctuation VERR and performing negative feedback is very important.
[0015]
If the time constant is short, the follow-up response to the VREF voltage of the output OB level for each horizontal line will be faster, but the amount of fluctuation (fluctuation frequency) for each clamping operation will increase accordingly, and horizontal streak-like noise will likely occur. Become.
[0016]
Therefore, the time constant must be set to a predetermined length so that the horizontal streak noise does not cause a problem in image quality.
[0017]
[Problems to be solved by the invention]
In such a conventional feedback type OB clamp circuit, the offset error due to the CCD offset and dark current component of the image sensor is assumed as the main factor of the fluctuation amount of OB, and these offset error components are corrected. The main design is made.
[0018]
Originally, these offset error components are not so large as 1/10 or less (several millimeters to several tens of millivolts) of the full range (up to 1 volt) of the imaging signal.
[0019]
By the way, when strong light such as direct sunlight is incident on a solid-state imaging device such as a CCD, a phenomenon called so-called blooming occurs in which charge overflows in the photoelectric conversion unit. When blooming occurs, the overflowed charge may flow into and accumulate in the OB pixel portion that is originally shielded in the light receiving pixel portion and does not depend on incident light.
[0020]
In this case, unlike the offset error component, the OB level cannot be an accurate black reference, but also reaches a full range level change (CCD saturation level VSAT) of the imaging signal for intense blooming.
[0021]
FIG. 6 shows operation waveforms of respective parts for explaining a clamping operation when blooming occurs. The OB output of the CDS output 11A rapidly reaches the CCD saturation level VSAT as blooming occurs. The OB output of the PGA output 11C is gradually lowered to the reference voltage VREF with respect to an erroneous OB level that has risen to the CCD saturation level VSAT with a response time based on the time constant set by the integrating amplifier 105.
[0022]
As described above, the conventional clamp circuit configuration has a problem that when blooming occurs, it follows an erroneous black level that greatly deviates from an appropriate OB level, and the entire image pickup signal causes blackening.
[0023]
In addition, as a result of following an erroneous black level that greatly deviates from the proper OB level, it takes a very long time to return to the normal OB level even after the blooming of the image sensor is resolved. There was a problem that the condition continued.
[0024]
The present invention has been made under such circumstances, and provides an image pickup apparatus and an image pickup method for the image pickup apparatus that do not cause a problem that blackout occurs in an image pickup signal by following an OB output to a largely incorrect black level. It is intended to do.
[0025]
[Means for Solving the Problems]
  In order to achieve the above object, according to the present invention, an imaging apparatus is provided as the following (1)., (2) And the imaging method of the imaging device is as follows (3)Configure as follows.
  (1) An imaging unit that optically forms an object on an image sensor, an image sensor that converts an optical image of the object into an electrical signal, and a direct current with respect to an electrical signal after photoelectric conversion by the image sensor An offset adding means for adding voltage, an amplifying means for amplifying with a variable gain, an optical black level included in the imaging signal with respect to the imaging signal after the offset addition processing by the offset adding means and the amplification processing by the amplifying means Sample hold means for sample-holding, negative feedback signal generation means for generating the DC voltage as a negative feedback signal based on a difference between a predetermined reference value and the optical black level held by the sample hold means, Feedback limiting means provided in a negative feedback signal generating means for limiting the DC voltage added in the offset adding means. In the imaging device,
The imaging apparatus in which the feedback limiting unit varies a feedback limiting level for a negative feedback signal according to a gain of the amplification unit.
(2) Imaging means for optically imaging a subject on an image sensor, an image sensor for converting an optical image of the subject into an electrical signal, and direct current with respect to an electrical signal after photoelectric conversion by the image sensor An offset adding means for adding a voltage; an amplifying means for amplifying with a variable gain; an offset adding process by the offset adding means; and an AD converting means for converting an analog imaging signal after the amplification process by the amplifying means into a digital signal; Optical black level extraction means for extracting an optical black level included in a digital signal obtained by the AD conversion means, and a difference between a predetermined reference value and the optical black level extracted by the optical black level extraction means And a negative feedback signal generating means for generating the DC voltage as a negative feedback signal, and the negative feedback signal generating means. In the image pickup apparatus and a feedback limiting means for limiting the DC voltage to be added in unit,
The imaging apparatus in which the feedback limiting unit varies a feedback limiting level for a negative feedback signal according to a gain of the amplification unit.
(3) An imaging apparatus comprising an amplifying unit for amplifying an electric signal from the imaging element and a feedback type OB clamp circuit including the amplifying unit, and limiting the amplitude of the negative feedback signal in the OB clamp circuit to a predetermined value or less. An imaging method of
An imaging method for an imaging apparatus, wherein the predetermined value is changed according to a gain to be set when the gain of the amplification means is variably set.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to examples of the imaging apparatus. The present invention is not limited to the form of the apparatus, and can be carried out in the form of a method supported by the description of the embodiments.
[0037]
【Example】
(Example 1)
FIG. 1 is a block diagram illustrating a configuration of a feedback-type OB clamp circuit that is a main part of the “imaging device” according to the first embodiment.
[0038]
First, the configuration of FIG. 1 will be described.
[0039]
Reference numeral 1 denotes a CCD (CCD image sensor) that converts an optical image of a subject into an electrical signal. An imaging signal output from the CDD 1 is input to a circuit 2 called a CDS (correlated double sampling) circuit, and reset noise is generated. After being removed, the signal is input to the offset addition circuit 3 to add a predetermined offset voltage, and the offset addition output is input to the variable amplifier 4.
[0040]
The CDS circuit 2 is a CDS circuit that uses a predetermined reference voltage VREF input from the terminal 6 as a reference for the feedthrough portion of the imaging signal. Similarly, the variable amplifier 4 images the reference voltage VREF. This constitutes a direct current amplifier that is used as a reference for direct current signal amplification.
[0041]
The variable amplifier 4 is a gain variable means for correcting the output sensitivity variation of the CCD 1 and switching the sensitivity setting of the image pickup apparatus. Hereinafter, in this embodiment, the clamp operation of the image pickup apparatus will be described simply and clearly. Therefore, it is assumed that the gain is simply handled as 1 time.
[0042]
The amplified output signal from the variable amplifier 4 is input to an image processing / recording / display circuit (not shown) on the one hand, and is input to the sample hold circuit 7 on the other hand and reads out the OB pixel input from the terminal 9. The OB level sampled and held by the OB clamp pulse synchronized with the timing is input to the integrating amplifier 5 (corresponding to the negative feedback signal generating means in the claims).
[0043]
The integrating amplifier 5 forms a predetermined integration time constant by a capacitor 5b and a resistor 5c, and a differential voltage (clamp error) between the sampled and held OB level and a predetermined reference voltage VREF input from the terminal 6 is used. Voltage) is integrated with the integration time constant, and the output (deviation amount from the voltage VREF) is input to the offset addition circuit 3 as a subtraction value to be subtracted.
[0044]
Further, the integrating amplifier 5 is configured such that the amplitude limiting diodes 5e and 5f are respectively connected in parallel with the capacitor 5b with the anode and cathode having opposite polarities, so that the clamp error voltage input to the integrating amplifier 5 is reduced. It functions to limit the output of the integrating amplifier 5 with a constant voltage amplitude (the forward voltages of the diodes 5e and 5f are reversed in direction).
[0045]
The state when the OB level of the output signal 1C of the variable amplifier 4 is clamped to the DC voltage level VREF and converges is exactly the same as the example shown in FIG. 5 of the conventional example, and is not shown here.
[0046]
The OB pixel output of the CCD output 1A is maintained at a DC voltage relatively close to the reference voltage VREF by the action of the CDS (correlated double sampling) circuit 2, but in reality, the feed-through component and signal component of the CCD 1 Difference component (CCD offset) and a dark current component depending on the temperature of the image sensor are superimposed to have an offset error (usually several millimeters to several tens of millivolts).
[0047]
This offset error varies for each image sensor, and varies depending on the temperature. Then, this offset error is amplified by the variable amplifier 4 and finally outputted as the black level fluctuation VERR of the imaging signal.
[0048]
The black level fluctuation VERR is detected as a difference of the VREF voltage by the sample hold circuit 7 and the integrating amplifier 5, integrated and output as the integrated output signal 1B, and the deviation amount from the voltage VREF of the output 1B is the amount of the CDS circuit 2 Subtracted from the output signal 1A.
[0049]
At this time, the diode elements 5e and 5f having a forward voltage larger than this are selected so as not to limit the voltage with respect to the integrated output due to the offset error.
[0050]
As a result, this operation is repeated for each output of the OB clamp pulse 1D, whereby the integrated output 1B and the OB pixel output of the variable amplifier 4 converge to the reference voltage VREF.
[0051]
Next, a clamp operation when blooming occurs in this embodiment will be described.
[0052]
FIG. 2 shows operation waveforms of respective parts for explaining a clamping operation when blooming occurs in this embodiment.
[0053]
The OB output of the CDS output 1A rises rapidly with the occurrence of blooming and reaches the CCD saturation level VSAT. The OB output of the PGA output 1C starts to rise in accordance with the rise of the OB output of the CDS output 1A, is input to the integration amplifier 5 through the sample hold circuit 7, and is a response time based on the time constant set by the integration amplifier 5. Thus, the CDS output 1A increases so that it gradually decreases to the reference voltage VREF with respect to the OB level.
[0054]
However, the OB fluctuation VSAT input to the integrating amplifier 5 is not integrated as it is with respect to the OB output that has rapidly increased to the CCD saturation level VSAT, and is determined by the amplitude limiter constituted by the diodes 5e and 5f. The amount of subtraction to the offset adder 3 is limited by the voltage VCLIP.
[0055]
For this reason, the integrated output 1B and the OB pixel output of the output signal of the variable amplifier 4 do not converge to the reference voltage VREF but converge to the amplitude limit voltage VCLIP as in the normal clamping operation.
[0056]
At this time, the OB output of the variable amplifier 4 is clamped to the reference voltage VREF when the OB output is increased by the VCLIP voltage with respect to the original correct OB output level. Only the result will be black sinking. Therefore, by setting the VCLIP voltage appropriately, it is possible to suppress the darkening of the image pickup signal after clamping.
[0057]
After the CCD blooming is eliminated, the OB output of the variable amplifier 4 is raised to the reference voltage VREF by the variation of the VCLIP voltage increased by blooming with respect to the original correct OB output level. Therefore, by appropriately setting the VCLIP voltage, it is possible to shorten the time required for the image signal after clamping to return to the correct OB output level.
[0058]
For example, when the CCD saturation level VSAT is 1V, if the VCLIP voltage is set at 0.2V, the amount of black sink and the recovery time can be suppressed to about 1/5 during blooming.
[0059]
Further, in order to briefly explain the basic operation of the clamp, in this embodiment, the gain of the variable amplifier 4 is treated as one time, but the offset correction amount in the offset adding circuit 3 is set by the gain setting of the variable amplifier 4. Needless to say, an appropriate VCLIP voltage is determined in consideration of the gain setting value.
[0060]
(Example 2)
By the way, in the feedback limiting means using the element characteristics (diode forward voltage) of the diode shown in the first embodiment, the voltage level (VCLIP voltage) to be limited depends on the element characteristics, and is adjusted with high accuracy. Can not do it.
[0061]
Also, the VCLIP voltage appropriate for limiting the OB fluctuation due to blooming depends on the set gain of the variable amplifier.
[0062]
Thus, by switching the VCLIP voltage according to the set gain of the variable amplifier, the configuration and operation are devised so that the same effect can be obtained in all ranges from low gain to high gain, which is the sensitivity variable width of the imaging device. This is the second embodiment to be described.
[0063]
FIG. 3 is a block diagram illustrating a configuration of a main part of the “imaging device” according to the second embodiment.
[0064]
The configuration of FIG. 3 will be described.
[0065]
Reference numeral 31 denotes a CCD (CCD image sensor) that converts an optical image of a subject into an electrical signal. An imaging signal output from the CDD 32 is input to a circuit 32 called a CDS (correlated double sampling) circuit, and reset noise is generated. After the removal, the signal is input to the offset addition circuit 35, a predetermined offset voltage is added, and the offset addition output is input to the variable amplifier 38.
[0066]
The CDS circuit 32 forms a CDS circuit that uses the predetermined reference voltage VREF input from the terminal 33 as a reference for the feedthrough portion of the imaging signal. Similarly, the variable amplifier 38 images the reference voltage VREF. This constitutes a direct current amplifier that is used as a reference for direct current signal amplification.
[0067]
The variable amplifier 38 is a gain variable means for correcting the output sensitivity variation of the CCD 1 and switching the sensitivity setting of the imaging apparatus.
[0068]
The amplified output signal from the variable amplifier 38 is input to the A / D converter 39 and converted into a digital signal. The imaging signal converted into a digital signal is input to an image processing / recording / display circuit (not shown) on the one hand, and on the other hand, an OB level included in the digital signal is input to the digital arithmetic circuit 42. The extracted current is converted into an analog current value via a current DAC 40 (D / A converter) and output.
[0069]
The digital arithmetic circuit 42 and the current DAC 40 are supplied with an OB clamp pulse synchronized with the readout timing of the OB pixel from the terminal 43, whereby the OB level is extracted and the current DAC 40 is driven.
[0070]
The output of the current DAC 40 is connected to a capacitor 37 that is grounded at one end. By charging and discharging the output current to and from the capacitor 37, the extracted OB level has a predetermined time constant constituted by the current value and the capacitor 37. And the output is input to the offset addition circuit 35 through the buffer circuit 36 as a subtraction value and subtracted to be subtracted.
[0071]
Further, a voltage limiting circuit 34 is connected to the output of the current DAC 40. The voltage limiting circuit 34 includes an NPN transistor 34b, a PNP transistor 34d, and a resistor 34c, and an emitter follower buffer formed by complementary transistors 34b and 34d is connected to the subordinate, and the output thereof is a current DAC 40. Connected to the output.
[0072]
The limit voltage VCLIP applied from the terminal 34a is transmitted to the output of the DAC 40 in such a manner that the voltage temperature drift due to the transistor is canceled.
[0073]
When the output current of the current DAC 40 and the voltage integrated and output by the capacitor 37 are smaller than the limit voltage VCLIP, the transistor 34d is cut off and almost no current flows through the emitter of the transistor 34d. Therefore, when the current is separated from the output of the current DAC 40 and is larger than the limit voltage VCLIP, the current is drawn from the capacitor 37 through the emitter of the transistor 34d, whereby the output of the current DAC 40 is limited by the limit voltage VCLIP.
[0074]
The manner in which the OB level of the output signal of the variable amplifier 38 is clamped to the DC voltage level VREF and converges is exactly the same as the example shown in FIG.
[0075]
The OB pixel output of the CCD output is maintained at a DC voltage that is relatively close to the reference voltage VREF by the action of the CDS (correlated double sampling) circuit 32. In practice, however, the feed-through component and the signal component of the CCD 1 The difference component (CCD offset) and the dark current component depending on the temperature of the image sensor are superimposed to have an offset error (usually several millimeters to several tens of millivolts).
[0076]
This offset error varies for each image sensor, and varies depending on the temperature. Then, this offset error is amplified by the variable amplifier 38 and finally outputted as the black level fluctuation VERR of the imaging signal.
[0077]
The black level fluctuation VERR is detected by the digital arithmetic circuit 42 and the current DAC 40, integrated, and subtracted from the output signal of the CDS circuit 32 through the buffer circuit 36 as an integrated output signal.
[0078]
By repeating this operation every time an OB clamp pulse is output, the black level fluctuation VERR approaches zero, and the OB output of the CDS circuit 32 approaches the reference voltage VREF. The OB level also converges to a predetermined target value.
[0079]
Here, the limit voltage VCLIP given from the terminal 34a is a control voltage supplied by a DA converter for system voltage control (not shown), and can be variably set according to the gain setting value of the amplifier 38.
[0080]
That is, the limit amount of amplitude fluctuation with respect to the reference voltage VREF when the gain setting value is 1 is A, and the limit amount A of amplitude fluctuation with respect to the reference voltage VREF when the gain setting value is 1 is the imaging element. Is set to a limit amount that does not exceed the offset error, i.e., does not limit the amount of variation due to the offset error.
[0081]
At this time,
The limit voltage VCLIP when the gain setting value is 1 is VREF + A
The limit voltage VCLIP when the gain setting value is double is VREF + A / 2
The limit voltage VCLIP when the gain setting value is 4 times is VREF + A / 4.
In other words, the limited amount of amplitude variation is set in inverse proportion to the gain setting value.
[0082]
By setting the limit voltage VCLIP in such a manner, the limit voltage corresponding to the output side of the variable amplifier 38 can be set even when the gain setting value of the variable amplifier 38 is 1, 2 or 4 times. A constant voltage A can be maintained.
[0083]
Next, a clamp operation when blooming occurs in this embodiment will be described.
[0084]
The operation waveforms of each part for explaining the clamping operation when blooming occurs are almost the same as the state of FIG. 2 used in the description of the first embodiment, and therefore FIG. 2 is used (including the differences). ) Described below.
[0085]
The 1A OB output, which is the output of the CDS 31, rises rapidly with the occurrence of blooming and reaches the CCD saturation level VSAT. The 1C OB output, which is the output of the PGA 38, first starts to rise in accordance with the OB output rise of the CDS output 1A. Thus, the integrated output 1B functions as a gradual drop to the reference voltage VREF with respect to the increased OB level of the CDS output 1A, with a response time based on a time constant set by the current DAC 40 and the capacitor 37.
[0086]
However, the current value input to the capacitor 37 is integrated as it is with respect to the OB output that rapidly rises to the CCD saturation level VSAT, and the voltage does not rise to the OB fluctuation VSAT. The amount of subtraction to the offset adder 35 is limited by VCLIP.
[0087]
Therefore, the integrated output 1B and the OB pixel output of the output signal of the variable amplifier 38 do not converge to the reference voltage VREF but converge to the amplitude limit voltage VCLIP as in the normal clamping operation.
[0088]
At this time, the OB output of the variable amplifier 38 is clamped to the reference voltage VREF when the OB output rises by about the VCLIP voltage with respect to the original correct OB output level. Only results in reduced black sun. Therefore, by setting the VCLIP voltage appropriately, it is possible to suppress the darkening of the image pickup signal after clamping.
[0089]
After the CCD blooming is eliminated, the OB output of the variable amplifier 38 is raised to the reference voltage VREF by the variation of the VCLIP voltage increased by blooming with respect to the original correct OB output level. Therefore, by appropriately setting the VCLIP voltage, it is possible to shorten the time required for the image signal after clamping to return to the correct OB output level.
[0090]
For example, when the CCD saturation level VSAT is 1V, if the (VCLIP-VREF) voltage is set at 0.2V, the amount of black sinking and the recovery time can be suppressed to about 1/5 during blooming.
[0091]
And as already explained, the (VCLIP-VREF) voltage is
Since the constant amplitude limit amount A is set regardless of the gain of the variable amplifier 38, the black sink amount and the recovery time can also achieve a constant effect regardless of the gain of the variable amplifier 38.
[0092]
In the first and second embodiments, in order to compare with the device configuration in the conventional example, the signal processing configuration in the order of the image pickup device, the CDS circuit, the offset adder, and the gain variable amplifier is based on the device configuration of the conventional example. In the present invention, the offset addition to the offset adder is limited, i.e., with respect to the negative feedback signal that deviates from the element variation of the image pickup means, the temperature characteristics, and the fluctuation amount due to the amplification means. Therefore, the order of signal processing is not necessarily limited to the above-described configuration.
[0093]
【The invention's effect】
As described above, according to the present invention, even if an OB level fluctuation that greatly deviates from the appropriate level occurs in the CCD output due to the occurrence of the blooming of the CCD, the feedback limiting means suitable for the feedback signal of the feedback clamp circuit. Since the amount of offset addition is limited by providing the OB output, it is possible to obtain an imaging signal that does not cause a problem that blackout occurs in the imaging signal by following the OB output to a largely incorrect black level.
[0094]
In addition, even after the CCD blooming is eliminated, the normal OB level can be quickly restored, so that an imaging signal with excellent responsiveness can be obtained.
[0095]
According to the fourth, eighth, and tenth aspects of the present invention, the feedback limit level for the negative feedback signal is varied according to the gain of the variable amplifying means. An imaging signal with a stable effect independent of sensitivity can be obtained in the entire range from low gain to high gain, which is a variable sensitivity range.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main configuration of a first embodiment.
FIG. 2 is an explanatory diagram of a clamping operation when blooming occurs
FIG. 3 is a block diagram showing a main configuration of the second embodiment.
FIG. 4 is a block diagram showing a configuration of a conventional example
FIG. 5 is an explanatory diagram of the clamping operation.
FIG. 6 is an explanatory diagram of a clamping operation when blooming occurs in a conventional example.
[Explanation of symbols]
1 CCD
2 CDS circuit
3 Offset addition circuit
4 Variable amplifier
5 Integration amplifier
5e, 5f Amplitude limiter
6 Reference voltage VREF
7 Sample hold circuit

Claims (3)

An imaging means for optically imaging the subject on the imaging device, an imaging device for converting the optical image of the subject into an electrical signal, and a DC voltage added to the electrical signal after photoelectric conversion by the imaging device samples and offset adding means, and amplifying means for amplifying with variable gain, the optical black level included in the image pickup signal to the image pickup signal after amplification by the offset addition processing and the amplification means by said offset adding means for a sample-and-hold means for holding a negative feedback signal generating means based on the difference of the held optical black level by the sample-and-hold means with a predetermined reference value, to generate the DC voltage as a negative feedback signal, before Kimake provided feedback signal generating means, shooting with a feedback limiting means for limiting the DC voltage to be added before Symbol offset adding means, In the device,
The imaging apparatus according to claim 1, wherein the feedback limiting unit varies a feedback limiting level for a negative feedback signal according to a gain of the amplification unit . An imaging means for optically imaging the subject on the imaging device, an imaging device for converting the optical image of the subject into an electrical signal, and a DC voltage added to the electrical signal after photoelectric conversion by the imaging device offset adding means for, amplifying means for amplifying with variable gain, an AD converter for converting an analog image pickup signal after amplification by the offset addition processing and the amplifying means according to said offset addition means into a digital signal, the AD conversion Optical black level extraction means for extracting an optical black level contained in the digital signal obtained by the means, and based on a difference between a predetermined reference value and the optical black level extracted by the optical black level extraction means. Te, a negative feedback signal generating means for generating the DC voltage as a negative feedback signal, is provided in the negative feedback signal generating means, said offset addition means In the imaging apparatus having a feedback limiting means for limiting said DC voltage Oite added, the,
The imaging apparatus according to claim 1, wherein the feedback limiting unit varies a feedback limiting level for a negative feedback signal according to a gain of the amplification unit . Amplifying means for amplifying the electric signal from the imaging element, the imaging of the imaging device for limiting a OB clamp circuit of the feedback type which includes the amplifying means, the amplitude of the negative feedback signals before Symbol OB clamp circuit to a predetermined value or less A method,
An imaging method for an imaging apparatus, wherein when the gain of the amplifying unit is variably set, the predetermined value is changed according to the gain to be set .

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