JP4080902B2 - Semiconductor device analysis apparatus and analysis method - Google Patents

Description

【００３５】
電子ビームの照射により発生する基板電流Ｉは、入射電子数ｍ１から二次電子数ｍ２を差し引いた量に比例することから、上式（１６）を用いて下式（１７）が得られる。

上式（１７）を一般化すると、下式（１８）が得られ、この式（１８）は、ホール２４０の内壁が二次電子で帯電した場合の基板電流Ｉを表し、上式（２）で表される補正項Ｉｄを与える。
Ｉ＝α−βｓｄ^２・exp(−γ・ｓ・ｄ)＝Ｉｄ ・・・（１８）
以上で、上式（２）の補正項Ｉｄが導出された。
【００３６】
上式（２）または上式（１８）において、定数α、β、γは、いわゆるフィッティングパラメータであって、補正項Ｉｄで与えられる基板電流が実測値と合うように適切に設定される。図７に、定数α、β、γがフィッティングされた補正項Ｉｄの特性の一例を示す。同図において、縦軸は補正項Ｉｄであり、横軸はホール径ｘであり、点線が補正項Ｉｄを示し、プロット点が実測値を示す。この例では、横軸をホール径ｘとしているが、ホールの深さｄが一定と考えれば、ホール径ｘはアスペクト比ｓに置き換えられ、Ｉ＝α＋β・ｘ・exp(−γ・ｘ)を得る。同図から理解されるように、上式（２）を採用することにより、アスペクト比ｓに対する基板電流の変動が適切に表現され、上式（１）に示すように、式（２）で与えられる補正項Ｉｄを基板電流Ｉｋから減じれば、アスペクト比ｓの影響が排除された基板電流Ｉｈを得ることができる。従って、上式（１）により得られる基板電流Ｉｈから膜厚を的確に評価することが可能になる。
【００３７】
なお、ホールを形成する際にエッチングを十分行ったとしても、実際には自然酸化膜が形成されるため、ホール底部の残膜の膜厚をゼロにすることは困難である。従って、上述の補正項Ｉｄは残膜の影響を含んだものになり、ホール側壁部の帯電現象による変動分を正確に把握することはできない。従って、膜厚測定結果からべた膜を形成したときの基板電流を算出し、上述の近似の結果とべた膜を形成したときに期待される基板電流との差から、補正量（補正項Ｉｄ）を求める必要がある。しかし、アスペクト比ｓをゼロ（ホール径ｘを無限大）とおいた場合の膜厚は、ウエハに均質に形成されたべた膜の膜厚を表すことから、式（２）においてｓをゼロとすることにより、αの値から自然酸化膜の膜厚の影響を逆に推定することができる。
【００３８】
次に、図８および図９を参照して、補正処理部１０８による他の補正処理を説明する。上述の例では、補正項Ｉｄとして、ホール側壁部の帯電効果を反映させて導出した式（２）を採用したが、これに代えて、ホール径ｘを変数とする一次関数を用いる。具体的に説明する。まず、補正の基準となる半導体基板の基板電流を測定する。即ち、ホール底部に残膜が存在しないように充分なエッチングを行い、半導体基板にホール（凹部）を形成する。実際には、十分なエッチングを行ったとしても、ホール底部に自然酸化膜が形成されるが、その膜厚が一定（既知）であって均一であればよい。続いて、このホールを電子ビームで走査し、このホール径ｘと基板電流Ｉを実測する。このホール径ｘと基板電流Ｉの実測値とから、これらの関係を表す特性を近似する近似式を求める。
【００３９】
図８に、実測値のプロット点を外挿する特性線を示す。この特性線を近似する近似式として、「Ｉ＝１．６７０１−７．３０９５ｘ」なるホール径ｘの一次関数を得る。この近似式における各項の係数は、実測値と整合するように適切に選ばれる。そして、この近似式を用いて、上述の基板電流測定装置により測定された基板電流Ｉｋを同様に補正する。
なお、この例では、補正項Ｉｄとして一次関数を用いたが、これに限らず、ホール径ｘを変数とする二次関数や三角関数など、公知の任意の関数を用いることができる。また、近似式については、ホール径について図８の特性線を複数の区間に分割し、各区間毎に設定してもよい。
【００４０】
図９に、上述の補正項Ｉｄとして、ホール径ｘを変数とする二次関数を採用した例を示す。この例では、ホール径ｘについて４つの区間に分割し、各区間特性を二次関数により近似している。この例における各区間での近似式は次のとおりである。
ホール径ｘが０．１６〜０．２の区間；
Ｉ＝５．４３４２−３７．１６９ｘ＋４９．８０２ｘ^２
ホール径ｘが０．２〜０．３の区間；
Ｉ＝２．１３５−１０．８７７ｘ−６．９９６５ｘ^２
ホール径ｘが０．３〜０．３８の区間；
Ｉ＝−８１．７８４＋４９３．４３ｘ−７４９．８９ｘ^２
ホール径ｘが０．３８以上の区間；
Ｉ＝２２．２１６−１０８．５９ｘ＋１２５．６１ｘ^２
この例では、近似式として一次関数よりも二次関数を用いることにより、各区間での実測値に対して高い相関度が得られ、実測値に則した近似が可能となる。
以上で補正処理部１０８による補正処理を説明した。
【００４１】
ここで、説明を図１に戻す。同図に示す演算処理部１０９は、参照データベース１１０を参照し、以下に説明するように、補正処理部１０８により得られた基板電流Ｉｈに基づき残膜２０５の膜厚を求める。この場合、上述の位置検出動作で得られた微細構造の境界で区分される各領域について、基板電流Ｉｈに基づき、各領域に存在する残膜の膜厚を推定する。
なお、この例では、補正された基板電流Ｉｈを用いて膜厚を推定するが、ホールのアスペクト比による基板電流の変動分が無視できる場合には、補正前の基板電流Ｉｋ（基板電流測定装置１００で測定された値）を用いてもよい。
まず、膜厚の導出原理を説明する。図１０に示すように、電子ビームの照射に伴って発生する基板電流は、膜厚の増減に対してピーク値を有する特性を示す。このため、基板電流の測定値から膜厚を一義的に特定することはできない。そこで、この実施形態では、電子ビームの照射エネルギーを変えると、ピーク値を示す膜厚の値が移動する傾向があることに着目し、基板電流を測定する際の電子ビームの照射エネルギーを少なくとも２種類の値に設定し、各照射エネルギーに対して得られる基板電流特性から膜厚を特定する。
【００４２】
ここで、図６に示す残膜２５０の膜厚を検出する場合を例に、膜厚の導出方法を具体的に説明する。なお、説明を簡略化するために、残膜の下層側には絶縁体２２０やゲート電極２１０が存在せず、残膜２５０は基板（図示なし）上に直接的に形成されているものとする。
まず、図１０に示すように、測定対象の残膜の種類に応じて、少なくとも２種類の照射エネルギーに対する基板電流と膜厚との特性を予め測定しておく。同図に示す例では、実線が照射エネルギーをＶ１（例えば５００Ｖ）とした場合の特性を示し、点線が照射エネルギーをＶ２（例えば１５００Ｖ）とした場合の特性を示す。これらの特性は参照データとして参照データベース１１０に格納される。
この例では、基板の上に直接的に残膜が形成されている場合の参照データが参照データベース１１０に格納されるが、この参照データベース１１０には、残膜の下層側の実際のデバイス構造が反映された参照データが記憶される。この参照データには、電子ビームの複数の所定の照射エネルギー値に対し、特定対象のホール２４０の底部をなす残膜がとり得る膜厚値と、上記複数の照射エネルギー値に対して測定されるべき基板電流値との対応関係が記述されている。
【００４３】
続いて、参照データベース１１０の各特性が得られた照射エネルギーで電子ビームを残膜２５０に照射し、そのときの基板電流Ｉｋを測定する。ここでは、照射エネルギーをＶ１としたときの基板電流をＩｋ（Ｖ１）とし、照射エネルギーをＶ２としたときの基板電流をＩｋ（Ｖ２）とする。続いて、図１０において、照射エネルギーをＶ１としたときの特性から、基板電流がＩｋ（Ｖ１）のときの膜厚Ｔ１およびＴ２を取得し、また照射エネルギーをＶ２としたときの特性から、上述の膜厚Ｔ１，Ｔ２に対する基板電流の値Ｉ１，Ｉ２を取得する。これら値Ｉ１，Ｉ２のうち、上述の測定により得られた基板電流Ｉｋ（Ｖ２）に近似する方を判別し、この判別された基板電流の値に対応する膜厚Ｔ１またはＴ２の一方を残膜２５０の膜厚として採用する。即ち、各照射エネルギーに対して測定される基板電流が図１０に示す両特性を共に満足する膜厚が残膜の２５０膜厚として採用される。以上で、残膜２５０の膜厚の導出方法が説明された。
【００４４】
次に、演算処理部１０９は、ホール底部の残膜の膜厚を視覚的に表示するための画像処理を行う。即ち、演算処理部１０９は、上述の膜厚の導出処理に加え、前述のホール位置の検出処理を行い、図１１に示すように、各走査線上の値Ｐａを求める。この例では、ホール底部に複数の断片化した残膜が散在しているために、１本の走査線上に多数の値Ｐａで表される点が存在している。そして、同図に点線で示すように、各走査線上の対応する点を結ぶ線分を表す画像データを生成する。また、同図では、各走査線上の点と点との間の区間Ａ，Ｂ，Ｃ等は、同一の縦構造を有する領域を表しており、上述の画像データには、各領域の膜厚を表すデータとして、上述の処理で求められた膜厚の値が付加される。
【００４５】
表示制御部１１１は、演算処理部１０９が生成した画像データに基づき、図１２に示すように、ホール底部の微細構造の境界と膜厚を表す画像を表示部１１２に表示させる。このように、２次元的にホールの底部を表示し、残膜の膜厚に応じた各領域を例えば色彩を変えて表示する。これにより、ホール底部の構造を立体的に把握できるようにしている。また、ＳＴＩ構造でのホール底部における絶縁膜の回転方向のずれや、絶縁膜のえぐれ（過剰なエッチング）を把握することができる。また、演算処理部１０９で得られた膜厚の値から、縦断面を生成し、ホール底部での膜厚の分布を立体的に表示するようにしてもよい。
上述の説明から理解されるように、本半導体デバイス解析装置によれば、ホールの小径化に伴ってアスペクト比が大きくなっても、ホール底部の微細構造の境界や段差、あるいは膜厚を的確に把握することが可能になる。
【００４６】
以下では、図１３〜図２６を参照して、本半導体デバイス解析装置で解析可能な他のデバイス構造の例を説明する。
図１３に示す例は、前述の図３に示すホール２４０の底部に階段状の残膜２５１が存在したものである。この場合、基板電流Ｉｋは、残膜２５１の厚さに応じた値をとる。この例では、ゲート電極２１０に相当する区間で、基板電流Ｉｋの波形が階段状となっており、基板電流Ｉｋに残膜２４０の膜厚が反映されている。従って、このような微細構造においても本半導体デバイス解析装置を用いて境界の位置や膜厚を解析することができる。
【００４７】
図１４に示す例は、前述の図３において、絶縁体２２０よりも膜厚が薄い絶縁体２２１が存在するものである。この例では、ホール底部に現れている絶縁体２２１を突き抜ける電子の数が増えるので、図３に示す構造と比較して、この絶縁体２２１に相当する区間での基板電流Ｉｋが増えるが、ゲート電極２１０に相当する区間での基板電流Ｉｋとは値が異なるので、このような微細構造においても本半導体デバイス解析装置を用いて境界を解析することができる。なお、同図に点線で示す基板電流波形は、膜厚を解析するために電子ビームの照射エネルギーを変えた場合を示している。
【００４８】
図１５に示す例は、上述の図１４において、ホール底部に現れている絶縁体２２１に対応する位置に合わせて、残膜２５２がゲート電極２１０の上に存在するものである。この場合に測定される基板電流Ｉｋの波形は、上述の図１４に示す場合と同様になるため、このままでは境界の位置について把握できても縦構造を区別することはできない。そこで、電子ビームの照射エネルギーを変えて基板電流（図１５の点線で示す波形）を測定し、このときの基板電流特性から縦構造の違いを把握する。図１６に、材質の違う部材の組み合わせによる基板電流特性の一例を示す。同図（ａ）に示す例は、シリコン（Ｓｉ）の基板上にシリコン酸化物（ＳｉＯ２）を積層した場合の特性であり、同図（ｂ）に示す例は、シリコンの基板上にＣｏＳｉを積層した場合の特性であり、各図において、点線が照射エネルギーを１５００Ｖとしたときのものであり、実線が照射エネルギーを５００Ｖとしたときのものである。
【００４９】
同図から理解されるように、同一の膜厚であっても、各照射エネルギーに対する基板電流が異なる。この特性の違いを利用することにより、図１４及び図１５に示す構造を判別することができる。具体的には、電子ビームの照射エネルギーを５００Ｖおよび１５００Ｖとして測定された基板電流をａおよびｂとすると、図１６（ａ）に示す特性では、基板電流ａ，ｂを与える同一の膜厚Ｔが存在するが、図１６（ｂ）に示す特性では存在しない。従って、この例では、測定された値から、材質の組み合わせがＳｉとＳｉＯ２との組み合わせであることが把握できる。このように、照射エネルギーを変えて測定された基板電流を必要な材質の組み合わせ分だけ用意し、これを参照データとして利用することにより、測定された基板電流の値から残膜の材質の組み合わせや膜厚を知ることができ、図１４及び図１５に示す構造を判別することができる。
【００５０】
次に、図１７に示す例は、上述の図１５において、残膜２５２に代えて、ホール底面の全体にわたって残膜２５１が均一に存在するものである。この場合、図１５に示す構造に比較して、ゲート電極２１０に相当する区間での基板電流が減少するが、基板電流の変化（段差）から絶縁体２２１とゲート電極２１０との境界の位置を把握することができる。
図１８に示す例は、ホール底部に４種の膜厚を有する残膜２５３が存在するもので、絶縁体２２１とゲート電極２１０のそれぞれに対し、残膜２５３の膜厚が２種の値をとっている。この場合も、電子ビームの照射エネルギーを変えることにより絶縁体２２１の上かゲート電極２１０の上かを切り分けられる。これにより、絶縁体２２１とゲート電極との境界位置に加え、残膜２５３の膜厚も把握することができる。
【００５１】
図１９に示す例は、ホール２４０の底部に残膜が存在せず、ホール底部の全体にわたってゲート電極２１０が現れているものである。この場合、ホール２４０に照射された電子ビームの多くがゲート電極２１０を突き抜け、ホール径に相当する区間でほぼ一定の比較的大きな基板電流Ｉｋが測定される。これにより、ホール２４０の底部に残膜が存在しないことが把握される。
図２０に示す例は、上述の図１９において、ホール２４０の底部に残膜２５１が均一に存在するもので、図１９の構造に比較して、測定される基板電流が小さくなる。従ってこの基板電流から、残膜２５１の存在を把握することができる。
図２１に示す例は、ホール２４０の底部の全体に絶縁体２２０が位置し、ホール底部に残膜２５３が存在するものである。この場合、絶縁体２２０により電子ビームが基板に到達できず、従って基板電流Ｉｋが測定されない。このことから、ゲート電極２１０がホール２４０の底部に位置していないことが把握できる。なお、この場合、基板電流が測定されないので、残膜の膜厚が変化しても把握できない。
【００５２】
図２２に示す例は、ホール２４０の底部の全体に比較的薄い絶縁体２２１が位置し、ホール底部に残膜２５１が均一に存在するものである。この場合、電子ビームが基板に到達し、基板電流Ｉｋが測定される。従って、電子ビームの照射エネルギーを変えて基板電流Ｉｋを測定することにより、残膜がゲート電極上に存在する上述の図２１に示す構造と区別することができる。
図２３に示す例は、ホール２４０の底部の全体に絶縁体２２１が位置し、ホール底部に比較的厚めの残膜２５３が不均一に存在するものである。この場合、電子ビームが残膜２５３と絶縁体２２１により基板に到達せず、基板電流Ｉｋが測定さない。従って、図２１に示す場合と同様に、ゲート電極２１０がホール２４０の底部に位置していないことが把握される。
【００５３】
図２４に示す例は、ホール２４０の底部に、アルミ（ＡＬ）、チタン（Ｔｉ）、チタンナイトライド（ＴｉＮ）の３層構造からなる配線の一部が突出しているものである。この場合、ホール２４０の底部の一部が３層構造の配線によって狭められて狭領域２４０Ａが形成され、この狭領域２４０Ａにおいて前述したアスペクト比の影響が顕著になる。このため、ホール２４０の底部側に絶縁体２２２が存在していても、基板電流Ｉｋが測定され、この基板電流から３層構造の配線の脇のエッチング量（狭領域２４０Ａの深さ）を把握できる。なお、この場合、前述の補正処理部１０８による補正処理は行わず、記憶部１０７に記憶された基板電流のデータがそのまま演算処理部１０９に供給される。なお、図２４では、ホール底部の３層構造の配線（ＴｉＮ／Ｔｉ／ＡＬ）に相当する区間での基板電流が顕著になっているが、これは、この配線が図示しない拡散層等を介して基板に接続されているからである。
【００５４】
図２５に示す例は、上述の図２４において、狭領域２０４Ａに残膜２５４が存在するものである。この場合、図２４の構造に比較して、狭領域２０４Ａに相当する区間での基板電流は減少するが、アスペクト比の影響により基板電流が発生する。従って、電子ビームの照射エネルギーを変えて基板電流を測定することにより、残膜２５４が、ホール内のＴｉＮ上に存在するものであるか、あるいは配線脇の狭領域（２４０Ａ）に存在するものであるかを把握することができる。
【００５５】
【発明の効果】
以上説明したように、本発明によれば以下の効果を得ることができる。
即ち、半導体基板の主面に形成された凹部に対して電子ビームを走査して基板電流値を測定し、この測定された基板電流値に基づき前記凹部の底部側に位置する微細構造の境界を演算して表示するようにしたので、検出信号である基板電流がアスペクト比によって弱まることがなく、従ってアスペクト比の大きなホールであっても、その底部の微細構造を的確に解析することが可能になる。
また、前記基板電流の微分量を演算することにより前記境界を与える位置情報を得るようにしたので、基板電流から微細構造の境界を特定することが可能になる。
【００５６】
また、前記境界で区分される各領域について、基板電流値に基づき膜厚を推定するようにしたので、ホールの構造を立体的に把握することが可能になる。
また、前記電子ビームの複数の照射エネルギー値に対し、前記凹部の底部をなす残膜がとり得る膜厚値と基板電流値との対応関係を表す参照データを備えたので、基板電流から膜厚を特定することが可能になる。
また、凹部の内径を測定し、前記凹部の内径を反映させて前記基板電流値を補正するようにしたので、凹部の内径に依存した基板電流の変動分を除去することが可能になる。
また、前記電子ビームの照射位置と基板電流値との関係から前記内径を得るようにしたので、凹部が小径化しても、正確にその内径を把握することが可能になる。
【００５７】
また、Ｉ＝α＋β・ｘ・exp(−γ・ｘ)なる数式を用いて、前記基板電流値の補正量を算出するようにしたので、凹部の内径に依存した基板電流の変動を的確に表現することが可能になる。
さらに、前記凹部の内径に代えて該凹部のアスペクト比を用いたので、アスペクト比に依存した基板電流の変動分を考慮して凹部の構造を解析することが可能になる。
【図面の簡単な説明】
【図１】 本発明の実施形態に係る半導体デバイス解析装置の構成図である。
【図２】 本発明の実施形態に係る補正処理部の構成図である。
【図３】 本発明の実施形態に係る微細構造の第１の例を示す断面図である。
【図４】 本発明の実施形態に係るホール位置検出の原理を説明するための図である。
【図５】 本発明の実施形態に係る微細構造の境界を検出する方法を説明するための図である。
【図６】 本発明の実施形態に係る微細構造の第２の例を示す図である。
【図７】 本発明の実施形態に係る補正処理部での補正処理に使用される補正項を説明するための特性図である。
【図８】 本発明の実施形態に係る補正処理部での他の補正処理（一次関数による近似）に使用される補正項を説明するための特性図である。
【図９】 本発明の実施形態に係る補正処理部での他の補正処理（二次関数による近似）に使用される補正項を説明するための特性図である。
【図１０】 本発明の実施形態に係る演算処理部での膜厚の導出方法を説明するための特性図である。
【図１１】 本発明の実施形態に係る表示処理を説明するための図である。
【図１２】 本発明の実施形態に係るホール底部の表示例を示す図である。
【図１３】 本発明の実施形態に係る被解析対象である微細構造の第３の例を示す図である。
【図１４】 本発明の実施形態に係る被解析対象である微細構造の第４の例を示す図である。
【図１５】 本発明の実施形態に係る被解析対象である微細構造の第５の例を示す図である。
【図１６】 本発明の実施形態に係る被解析対象である微細構造の第５の例における膜厚解析原理を説明するための図である。
【図１７】 本発明の実施形態に係る被解析対象である微細構造の第６の例を示す図である。
【図１８】 本発明の実施形態に係る被解析対象である微細構造の第７の例を示す図である。
【図１９】 本発明の実施形態に係る被解析対象である微細構造の第８の例を示す図である。
【図２０】 本発明の実施形態に係る被解析対象である微細構造の第９の例を示す図である。
【図２１】 本発明の実施形態に係る被解析対象である微細構造の第１０の例を示す図である。
【図２２】 本発明の実施形態に係る被解析対象である微細構造の第１１の例を示す図である。
【図２３】 本発明の実施形態に係る被解析対象である微細構造の第１２の例を示す図である。
【図２４】 本発明の実施形態に係る被解析対象である微細構造の第１３の例を示す図である。
【図２５】 本発明の実施形態に係る被解析対象である微細構造の第１４の例を示す図である。
【図２６】 従来技術に係る微細構造の第１の例を示す図である。
【図２７】 従来技術に係る微細構造の第２の例を示す図である。
【図２８】 従来技術に係る微細構造の第３の例を示す図である。
【符号の説明】
１００；基板電流測定装置、１０１；電子ビーム発生部、１０２；移動ステージ、１０３；電子ビーム制御部、１０４；電極、１０５；基板電流検出部、１０６；位置検出部、１０７；記憶部、１０８；補正処理部、１０８Ａ；膜厚記憶部、１０８Ｂ；ホール径算出部、１０８Ｃ；アスペクト比算出部、１０８Ｄ；補正演算部、１０９；演算処理部、１１０；参照データベース、１１１；表示制御部、１１２；表示部。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device analysis apparatus used for analyzing a fine structure formed on a semiconductor substrate, and more particularly to analyzing the position of a hole for electrically connecting an upper layer wiring and a lower layer wiring. Regarding technology.
[0002]
[Prior art]
  A semiconductor device generally has a multilayer wiring structure. In this type of device structure, a hole is formed in the intermediate insulating layer between the lower layer wiring and the upper layer wiring in order to electrically connect the lower layer wiring (lower layer wiring) and the upper layer wiring (upper layer wiring). However, a conductive member is buried in this hole. Figure26Shows an example of the peripheral structure of the hole. This figure shows a longitudinal section of a MOS transistor formed on a semiconductor substrate 800 cut in the gate width direction. 820 is an element isolation insulator, 810 is a polysilicon gate electrode, and 830 is an interlayer insulation. Insulator 840 is a hole.
Although not shown in the drawing, a conductive member is embedded in the hole 840, and an upper layer wiring is formed on the insulator 830. Thereby, the upper layer wiring and the gate electrode 810 which is the lower layer wiring are electrically connected through the conductive member in the hole.
[0003]
  Here, when the hole 840 is formed in the insulator 830, if the position of the hole 840 is shifted with respect to the gate electrode 810, electrical connection between the gate electrode 810 and the conductive member in the hole 840 cannot be secured. . For this reason,26As shown in FIG. 4, the gate electrode 810 is provided with a margin m with respect to the hole 840, and the gate electrode 810 is formed larger than the hole diameter, thereby absorbing the deviation between them with the margin m. The electrical connection between the embedded conductive member and the gate electrode 810 is stably secured.
[0004]
  However, in recent years, the miniaturization of the device structure has been promoted, and the gate electrode which is the lower layer wiring has been formed to be small, and it has become difficult to absorb the deviation of the holes by the above-described method. Therefore, in the case of such a miniaturized device structure,27As shown in FIG. 4, a method of forming a hole 940 larger than the gate electrode is employed. In this figure, 900 is a semiconductor substrate, 910 is a gate electrode, 920 is an insulator for element isolation, 930 is an insulator for interlayer insulation, and 940 is a hole.
  Figure27In the example shown in (a), the central axis J1 of the gate electrode 910 and the central axis J2 of the hole 940 coincide with each other, and there is an ideal state where there is no deviation between the hole and the gate electrode. In contrast, figure27In the example shown in (b), a deviation d exists between the gate electrode 910 and the hole 940.
[0005]
According to this method, even if there is a deviation d between the hole 940 and the gate electrode 910, if a part of the gate electrode 910 appears at the bottom of the hole 940, electrical connection is ensured. be able to. However, when the deviation d increases, the area of the gate electrode 910 that appears at the bottom of the hole 940 decreases, and the electrical resistance between the gate electrode 910 and a conductive member (not shown) in the hole 940 increases. For this reason, it is necessary to strictly manage the deviation d between the hole 940 and the gate electrode 910. This deviation d is generally grasped from the position of the boundary 950 between the gate electrode 910 and the insulator 920 by observing the bottom of the hole 940 using an electron microscope (SEM).
In addition to the electron microscope described above, an apparatus using a substrate current is known as an apparatus for analyzing a device structure such as a gate or hole shape (see Patent Document 1). This device scans the surface of the wafer with an electron beam, and the device structure such as the shape of the holes formed in the wafer and the remaining film at the bottom of the holes due to the strength of the substrate current generated in the semiconductor substrate by irradiation of this electron beam. Is to measure. According to this apparatus, the vertical structure such as the thickness of the remaining film at the bottom of the hole can be grasped.
[0006]
[Patent Document 1]
JP 2002-83849 A
[0007]
[Problems to be solved by the invention]
  By the way, with the recent miniaturization of the device structure, the hole diameter tends to decrease and the hole aspect ratio tends to increase. According to the technique using the above-described electron microscope, when the diameter of the hole 940 is reduced and the aspect ratio is increased, the number of secondary electrons emitted from the hole 940 to the outside is reduced and obtained from the secondary electrons. The S / N ratio of the detection signal decreases. For this reason, it becomes difficult to observe the bottom of the hole with the above-mentioned electron microscope, and the above-mentioned deviation d cannot be grasped. Also figure28As shown in FIG. 4, when the remaining film 960 is present at the bottom of the hole 940, even if the number of secondary electrons emitted from the hole to the outside is sufficient for observation, the gate electrode and the insulator The boundary 950 cannot be recognized, and therefore the deviation d cannot be grasped.
  On the other hand, according to the above-described conventional technique for measuring the substrate current, since the substrate current is measured, the S / N ratio of the detection signal is reduced like the secondary electrons even if the aspect ratio is increased. There is nothing. However, since the substrate current is not always constant with respect to the change in aspect ratio, there is a problem that the thickness of the remaining film at the bottom of the hole cannot be accurately grasped.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device analysis apparatus that can accurately analyze the fine structure of the hole bottom having a large aspect ratio.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configuration.
That is, the semiconductor device analysis apparatus according to the present invention scans an electron beam with respect to a recess formed in a semiconductor substrate, and measures a substrate current generated in the semiconductor substrate as the electron beam is scanned. Means, boundary calculating means for calculating boundaries of a plurality of fine structures located on the bottom side of the recess based on the substrate current measured by the current measuring means, and the boundary obtained as a calculation result of the boundary calculating means Display means for displaying.
In the semiconductor device analysis apparatus, the boundary calculation means obtains position information that gives a boundary of the fine structure by calculating a differential amount of the substrate current.
[0010]
In the semiconductor device analysis apparatus, film thickness estimation for estimating a film thickness of a residual film existing in each region based on a substrate current value measured by the current measuring unit for each region divided by the boundary of the fine structure. The apparatus further includes means.
In the semiconductor device analysis apparatus, the film thickness estimation unit may calculate a film thickness value that can be taken by a remaining film that forms a bottom of the recess and a plurality of irradiation energy values with respect to a plurality of irradiation energy values of the electron beam. A reference data storage means for storing reference data representing a correspondence relationship with a substrate current value to be measured, and the reference based on the substrate current value measured by the current measurement means for the plurality of irradiation energy values. Film thickness specifying means for specifying the film thickness of the remaining film with reference to the data.
[0011]
In the semiconductor device analysis apparatus, an inner diameter measuring unit that measures an inner diameter of the recess, and a current that corrects the substrate current value measured by the current measuring unit by reflecting the inner diameter of the recess measured by the inner diameter measuring unit. Correction means.
In the semiconductor device analyzing apparatus, the inner diameter measuring unit obtains the inner diameter of the recess from the relationship between the irradiation position of the electron beam and the substrate current value.
[0012]
In the semiconductor device analysis apparatus, the current correction unit is measured by the current measurement unit so as to cancel the fluctuation of the substrate current caused by charging of the inner wall of the concave portion with irradiation of the electron beam. The substrate current value is corrected.
In the semiconductor device analysis apparatus, when the current correction means sets the substrate current of the semiconductor substrate to I, the inner diameter of the concave portion to x, a constant to α, and positive constants to β and γ, I = The correction amount of the substrate current value measured by the current measuring means is calculated using a mathematical formula of α + β · x · exp (−γ · x).
In the semiconductor device analyzing apparatus, the aspect ratio of the recess is used instead of the inner diameter of the recess.
[0013]
In the semiconductor device analysis apparatus, the current correction unit uses an approximate expression that approximates a relationship between an inner diameter of a recess formed in a reference semiconductor substrate and a substrate current generated by scanning an electron beam with respect to the recess. Then, the substrate current measured by the current measuring means is corrected.
In the semiconductor device analysis apparatus, the approximate expression is set for each section obtained by dividing the characteristic with respect to the inner diameter.
In the semiconductor device analysis apparatus, the approximate expression is a linear function having the inner diameter as a variable.
In the semiconductor device analysis apparatus, the approximate expression is a quadratic function having the inner diameter as a variable.
[0014]
Further, the semiconductor device analysis method according to the present invention includes a step of scanning an electron beam with respect to a recess formed in the semiconductor substrate and measuring a substrate current value generated in the semiconductor substrate as the electron beam is scanned. And calculating a boundary of the fine structure located on the bottom side of the recess based on the measured substrate current value, and displaying the boundary obtained as a result of the calculation.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 shows a configuration of a semiconductor device analysis apparatus according to the first embodiment of the present invention. This semiconductor device analysis apparatus analyzes the fine structure of a recess such as a hole formed in the main surface of a semiconductor substrate. As shown in the figure, an electron beam generator 101, a moving stage 102, an electron beam control Unit 103, electrode 104, substrate current detection unit 105, position detection unit 106, storage unit 107, correction processing unit 108, arithmetic processing unit 109, reference database 110, display control unit 111, and display unit 112. . Among these, the electron beam generator 101, the moving stage 102, the electron beam controller 103, the electrode 104, the substrate current detector 105, and the position detector 106 constitute the substrate current measuring apparatus 100.
[0016]
Here, the above-described substrate current measuring apparatus 100 is based on the same principle as that disclosed in Japanese Patent Laid-Open No. 2OO2-83849, and measures the substrate current generated in the semiconductor substrate by electron beam irradiation. To do. That is, the electron beam generator 101 is fixed so as to form a predetermined irradiation angle with respect to the upper surface of the semiconductor substrate to be analyzed placed on the moving stage 102. The moving stage 102 is configured to be movable on a substantially horizontal two-dimensional plane. By moving the moving stage 102 in the horizontal direction, the electron beam output from the electron beam generating unit 101 is used to move the semiconductor substrate to be analyzed. The upper surface is scanned. The electron beam control unit 103 controls the electron beam generation unit 101 and the moving stage 102, and manages the irradiation energy, irradiation current amount, scanning speed, scanning position, and the like of the electron beam during scanning.
[0017]
An electrode 104 is attached to the upper surface of the moving stage 11 so as to be in contact with the back surface of the semiconductor substrate to be analyzed, and this electrode 104 is connected to the input unit of the substrate current detection unit 105. The substrate current detection unit 105 detects and amplifies the substrate current Ik input through the electrode 104, A / D converts it into a digital signal, and outputs it. Subsequent to the substrate current detection unit 105, as noise removal means, means for performing a Fourier transform process on the signal of the substrate current Ik, means for performing a numerical calculation of the processing result and an arbitrary function, Means is provided for performing an inverse Fourier transform process on the processing result of the numerical operation. The position detection unit 106 detects the irradiation position P of the electron beam from the position of the moving stage 102.
[0018]
The storage unit 107, the correction processing unit 108, the arithmetic processing unit 109, the reference database 110, the display control unit 111, and the display unit 112 connected to the subsequent stage of the substrate current measuring apparatus 100 are constructed on an information processing apparatus such as a workstation. The Here, the storage unit 107 stores the substrate current Ik and the electron beam irradiation position P detected by the substrate current detection unit 105 and the position detection unit 106 of the substrate current measuring apparatus 100 described above. The correction processing unit 108 corrects a measurement error caused by the aspect ratio. The arithmetic processing unit 109 executes arithmetic processing for analyzing the boundary of the fine structure at the bottom of the hole, the film thickness of the remaining film, and the like. The display control unit 109 performs control for displaying the processing result on the display unit 110. The reference database 110 stores data referred to in analyzing the film thickness. The “fine structure boundary” described above represents a concept including a step portion of the fine structure.
[0019]
FIG. 2 shows a configuration example of the correction processing unit 108. The correction processing unit 108 includes a film thickness storage unit 108A, a hole diameter calculation unit 108B, an aspect ratio calculation unit 108C, and a correction calculation unit 108D. Here, the thickness value of each layer formed on the semiconductor substrate to be measured is stored in advance in the film thickness storage unit 108A. This film thickness value is a design value determined by a manufacturing process to be used, a measurement value measured using a known film thickness measuring apparatus, or the like. The method for obtaining the film thickness value stored in the film thickness storage unit 108A is not particularly limited. The hole diameter calculation unit 108B reproduces the substrate current waveform from the substrate current Ik and the electron beam irradiation position P stored in the storage unit 107, and calculates the hole diameter (that is, the inner diameter of the hole) from the substrate current waveform. It is. The aspect ratio calculation unit 108C calculates the aspect ratio of the hole from the film thickness value and the hole diameter. The correction calculation unit 108D executes calculation processing for correcting the substrate current Ik by reflecting the hole aspect ratio. The substrate current Ih obtained by correcting the substrate current Ik is output to the arithmetic processing unit 109 in FIG. 1 together with the irradiation position P of the electron beam.
[0020]
Hereinafter, the operation of the present embodiment will be described in order of the position detection operation of the hole (concave portion) formed in the main surface of the semiconductor substrate and the residual film detection operation at the bottom of the hole.
(1) Hole position detection operation
It is assumed that the microstructure shown in FIG. 3 is formed on the main surface of the semiconductor substrate to be analyzed. In the figure, 210 is a gate electrode, 220 is an insulator for element isolation, 230 is an insulator for interlayer insulation, and 240 is a hole, respectively. The gate electrode 910, insulator 920, and insulator shown in FIG. 930 corresponds to hole 940. In this example, there is no residual film at the bottom of the hole 240, and the insulator 220 and part of the gate electrode 210 are exposed.
[0021]
Prior to analysis, the semiconductor substrate on which the above-described microstructure is formed is placed on the moving stage 102 so that the back surface is in contact with the electrode 104, and the semiconductor substrate is irradiated with an electron beam on a predetermined region. Positioning is performed. When this positioning is completed, the moving stage 102 is moved, and the surface of the semiconductor substrate in which the holes 240 are formed is scanned with an electron beam having a predetermined irradiation energy. The substrate current Ik generated inside the semiconductor substrate with the irradiation of the electron beam is measured by the substrate current measuring device 100 and A / D converted into digital data.
[0022]
At this time, the electron beam is blocked by the insulators 220 and 230, but penetrates the gate electrode 210. Therefore, the waveform of the substrate current Ik at each position on the scanning line is as shown in the lower part of FIG. It increases at a position corresponding to the gate electrode 210, and as will be described later, the position of the boundary (step) between the insulator 220 and the gate electrode 210 at the bottom of the hole is grasped from the rising edge of this waveform. In this example, the substrate current Ik at the insulator 220 at the bottom of the hole is set to zero. However, if the irradiation energy of the electron beam is adjusted, the substrate current Ik is reduced over the entire bottom of the hole as shown in FIG. Observed and the hole diameter can be grasped from the waveform at this time.
[0023]
In parallel with the measurement of the substrate current Ik described above, the position detector 106 detects the irradiation position P of the electron beam from the position of the moving stage 102. The substrate current Ik converted into digital data by the substrate current detection unit 105 and the electron beam irradiation position P detected by the position detection unit 106 are stored in the storage unit 107 in association with each other. The correction processing unit 108 reads data stored in the storage unit 107 and performs correction processing on the substrate current. The correction processing in the correction processing unit 108 is for correcting the fluctuation of the substrate current due to the aspect ratio, but is not necessarily a function necessary for detecting the position of the hole. It is assumed that there is no change in the substrate current, and the description regarding the correction process is omitted.
[0024]
When the substrate current Ih is obtained by the correction process described above, the arithmetic processing unit 109 obtains the boundary 300 between the insulator 220 and the electrode 210 that appears at the bottom of the hole from the waveform of the substrate current Ih. The principle for obtaining the boundary 300 will be described with reference to FIG. The waveform shown in the upper part of FIG. 4 represents the substrate current Ih obtained when the fine structure shown in FIG. 3 is scanned with an electron beam, and corresponds to the waveform of the substrate current Ik shown in the lower part of FIG. . However, in the example shown in FIG. 4, the irradiation energy of the electron beam is set higher than in the case shown in FIG. 3, and therefore the substrate current Ik is also in the section corresponding to the insulator 220 at the bottom of the hole. Observed.
[0025]
As shown in FIG. 4, the substrate current Ih greatly changes at the boundary of the fine structure irradiated with the electron beam. That is, in FIG. 3, when the potential beam is scanned from the left side to the right side of the drawing, the substrate current Ih is zero because the electron beam does not reach the substrate in the section where the insulator 220 and the insulator 230 are stacked. In the section where the insulator 220 appears at the bottom of the hole 240, a slight substrate current Ih (Ik) is generated because the electron beam slightly reaches the substrate. Further, in the section where the gate electrode 210 appears at the bottom of the hole 240, a large substrate current Ih (Ik) is generated because most of the electron beam reaches the substrate. Thus, a large change occurs in the substrate current Ih at the position where the vertical structure changes (fine structure boundary), and the position of the boundary 300 can be specified from the position where this change occurs. In this embodiment, the differential value Ib shown in the lower part of the figure is generated by differentiating the waveform of the substrate current Ih shown in the upper part of FIG. 4, and the irradiation position when the absolute value of the differential value Ib exceeds a certain value. A value Pa representing P is output as position information for each scanning line.
[0026]
As shown in FIG. 5, the display control unit 111 plots the value Pa output from the arithmetic processing unit 109 for each scanning line, and causes the display unit 112 to display a line connecting these points. In FIG. 5, the black circle corresponds to the position of the step portion on the inner periphery of the bottom of the hole 240, and the white circle corresponds to the boundary position between the insulator 220 and the gate electrode 210 appearing at the bottom of the hole 240. Therefore, in this example, the right side of the dotted line connecting the white circles represents the gate electrode 210, and the line connecting the black circles represents the shape of the bottom of the hole 240, from which the deviation between the hole 240 and the gate electrode 210 can be grasped. The position of the hole 240 can be detected.
As described above, in this semiconductor device analysis apparatus, the substrate current generated by the electron beam irradiation is measured, and the boundary (step) of the fine structure is specified from the substrate current. Therefore, even if the hole diameter becomes small Thus, the substrate current Ik, which is a detection signal, does not weaken, and therefore the fine structure inside the hole can be accurately grasped as compared with the case where secondary electrons are detected.
[0027]
(2) Remaining film detection operation at the bottom of the hole
Next, as shown in FIG. 6, the operation when the remaining film 250 exists at the bottom of the hole 240 will be described. In the example shown in FIG. 6, since the remaining film 250 exists at the bottom of the hole, the substrate current Ik is smaller than that in the case shown in FIG. In this residual film detection operation, in addition to the hole position detection operation (that is, the operation for obtaining the boundary 300), an operation for detecting the film thickness of the residual film 250 is performed. For example, the hole position detection operation is similar to the above-described operation, and therefore, the operation for detecting the film thickness of the remaining film 250 will be described here.
First, when the semiconductor substrate on the moving stage is positioned in the same manner as described above, the substrate current measuring apparatus 100 performs electron beam irradiation with a plurality of irradiation energies while maintaining a predetermined irradiation angle with respect to a certain measurement region including the hole 240. Are sequentially scanned to measure the substrate current Ik.
[0028]
Specifically, the irradiation energy of the electron beam generator 101 is set to V1, and the measurement region is scanned with the electron beam. The substrate current Ik generated at this time is detected by the substrate current detection unit 105 and is output to the storage unit 107 together with the irradiation position P. Subsequently, the irradiation energy of the electron beam generating unit 101 is set to V2, and the substrate current Ik detected by scanning the same region is output to the storage unit 107 together with the irradiation position P. When scanning the measurement region with the electron beam, the electron beam irradiation position P is set to be the same for all of the irradiation energy levels (V1, V2). That is, the electron beams with irradiation energy V1 and V2 are sequentially irradiated to the same irradiation position. In this way, the substrate current Ik generated when the scanning is sequentially performed with the electron beam is detected by the substrate current detection unit 105, converted into digital data, and a process for removing noise components is performed. The measurement data from which the noise component has been removed is stored in the storage unit 107.
[0029]
Here, even if the hole diameter is constant, when the hole depth is changed and the aspect ratio is increased, the number of electrons reaching the substrate side is increased, and a phenomenon that the substrate current tends to increase is known. . The inventor of the present application has clarified that this phenomenon is caused by charging of the inner wall of the hole. The correction processing unit 108 described below performs correction processing based on this elucidated mechanism, and is caused by charging the inner wall of the hole 240 with irradiation of the electron beam by reflecting the aspect ratio. The substrate current Ik is corrected so as to cancel the fluctuation amount of the substrate current.
[0030]
The correction process by the correction processing unit 108 will be specifically described. The hole diameter calculation unit 108B (FIG. 2) constituting the correction processing unit 108 calculates the inner diameter of the hole 240 from the measurement data stored in the storage unit 107 described above. That is, for example, in FIG. 3, by appropriately selecting the irradiation energy of the electron beam irradiated to the hole 240, the electron beam penetrates both the insulator 220 and the gate electrode 210 at the bottom of the hole, thereby generating a substrate current. The inner diameter of the hole 240 is calculated from the waveform of the substrate current Ik at this time. In FIG. 3, the substrate current is zero in the region of the insulator 220 located at the bottom of the hole 240, but the substrate current is generated over the entire hole diameter by appropriately setting the irradiation energy of the electron beam. .
[0031]
The aspect ratio calculation unit 108C calculates the aspect ratio s (= d) of the hole 240 from the inner diameter x of the hole 240 calculated by the hole diameter calculation unit 108B and the film thickness d of the insulating film 230 read from the film thickness storage unit 108A. / X) is calculated and output to the correction calculation unit 108D.
The correction calculation unit 108D reads the data of the substrate current Ik from the storage unit 107, and corrects the substrate current Ik to the substrate current Ih by the following equation (1). In the formula (1), Id is a correction term and represents a measured value of the substrate current when the inner wall of the hole 240 is charged with secondary electrons, and the aspect ratio s calculated by the above-described aspect ratio calculation unit 108C. Is the amount obtained from equation (2). In Equation (2), α, β, and γ are constants, d is the film thickness of the insulating film 230, and s is the aspect ratio of the hole 240.
Ih = Ik−Id (1)
Id = α−βsd²・ Exp (−γ ・ s ・ d) (2)
[0032]
Here, the process of deriving the correction term Id will be described.
In the device structure shown in FIG. 3, the emission energy E of secondary electrons emitted when the inside of the hole 240 is irradiated with an electron beam is represented by φ, the work function of the secondary electron emission source (hole bottom) being φ, When the incident energy of the beam is E0 and the potential formed by the secondary electrons charged on the inner wall of the hole 240 is V ′, the following expression (11) is obtained.
E = E0− (φ + V ′) (11)
[0033]
The potential V ′ in the above equation (11) is obtained as follows.
The potential V exerted by a certain electron on the point of distance p is expressed by equation (12), where A and B are positive constants.
V = A · exp (−B · p) (12)
The number of electrons charged on the inner wall of the hole 240 is proportional to the area of the inner wall. In this case, the area of the inner wall is “s · d²Therefore, in consideration of the number of electrons n per unit area charged on the inner wall of the hole 240, the potential V ′ is expressed by the following equation (13) using the above equation (12).
V '= nsd²・ A ・ exp (-B ・ s ・ d) (13)
Therefore, the above equation (11) is expressed as the following equation (14) using the above equation (13).
E = E0-φ-nsd²・ A ・ exp (-B ・ s ・ d) (14)
[0034]
On the other hand, the emission energy E of secondary electrons when the inner wall of the hole 240 is not charged with secondary electrons is expressed by the following equation (15).
E = E0−φ (15)
Here, when the number of secondary electrons generated when the inner wall is charged is m, and the number of secondary electrons generated when the inner wall is not charged is m2, the number of secondary electrons m and m2 is: Since it is proportional to the emitted energy, the following equation (16) is obtained from the equations (14) and (15). However, in the formula (16), A ′ = A / (E0−φ).

[0035]
Since the substrate current I generated by the electron beam irradiation is proportional to the amount obtained by subtracting the number of secondary electrons m2 from the number of incident electrons m1, the following equation (17) is obtained using the above equation (16).

When the above equation (17) is generalized, the following equation (18) is obtained. This equation (18) represents the substrate current I when the inner wall of the hole 240 is charged with secondary electrons, and the above equation (2) A correction term Id expressed as follows is given.
I = α−βsd²Exp (−γ · s · d) = Id (18)
Thus, the correction term Id of the above equation (2) is derived.
[0036]
In the above equation (2) or the above equation (18), constants α, β, and γ are so-called fitting parameters, and are appropriately set so that the substrate current given by the correction term Id matches the actually measured value. FIG. 7 shows an example of the characteristic of the correction term Id fitted with the constants α, β, and γ. In the figure, the vertical axis represents the correction term Id, the horizontal axis represents the hole diameter x, the dotted line represents the correction term Id, and the plotted points represent the actual measurement values. In this example, the horizontal axis is the hole diameter x, but if the hole depth d is considered to be constant, the hole diameter x is replaced by the aspect ratio s, and I = α + β · x · exp (−γ · x) obtain. As understood from the figure, by adopting the above equation (2), the fluctuation of the substrate current with respect to the aspect ratio s is appropriately expressed, and as shown in the above equation (1), it is given by the equation (2). If the corrected term Id is subtracted from the substrate current Ik, the substrate current Ih from which the influence of the aspect ratio s is eliminated can be obtained. Therefore, the film thickness can be accurately evaluated from the substrate current Ih obtained by the above equation (1).
[0037]
Even if the etching is sufficiently performed when forming the hole, since a natural oxide film is actually formed, it is difficult to make the film thickness of the remaining film at the bottom of the hole zero. Therefore, the correction term Id described above includes the influence of the remaining film, and the fluctuation due to the charging phenomenon of the hole side wall cannot be accurately grasped. Accordingly, the substrate current when the solid film is formed is calculated from the film thickness measurement result, and the correction amount (correction term Id) is calculated from the difference between the above approximate result and the substrate current expected when the solid film is formed. It is necessary to ask. However, since the film thickness when the aspect ratio s is zero (the hole diameter x is infinite) represents the film thickness of a solid film formed uniformly on the wafer, s is set to zero in equation (2). Thus, the influence of the film thickness of the natural oxide film can be estimated in reverse from the value of α.
[0038]
Next, another correction process by the correction processing unit 108 will be described with reference to FIGS. 8 and 9. In the above-described example, the expression (2) derived by reflecting the charging effect of the hole side wall is used as the correction term Id. Instead, a linear function having the hole diameter x as a variable is used. This will be specifically described. First, a substrate current of a semiconductor substrate that is a reference for correction is measured. That is, sufficient etching is performed so that no residual film exists at the bottom of the hole, thereby forming a hole (concave portion) in the semiconductor substrate. Actually, even if sufficient etching is performed, a natural oxide film is formed at the bottom of the hole, but the film thickness may be constant (known) and uniform. Subsequently, the hole is scanned with an electron beam, and the hole diameter x and the substrate current I are measured. From the hole diameter x and the measured value of the substrate current I, an approximate expression that approximates the characteristics representing these relationships is obtained.
[0039]
FIG. 8 shows characteristic lines for extrapolating the plot points of the actual measurement values. As an approximate expression for approximating this characteristic line, a linear function of a hole diameter x of “I = 1.671-7.3095x” is obtained. The coefficient of each term in this approximate expression is appropriately selected so as to match the measured value. Then, using this approximate expression, the substrate current Ik measured by the above-described substrate current measuring device is similarly corrected.
In this example, a linear function is used as the correction term Id. However, the present invention is not limited to this, and any known function such as a quadratic function or a trigonometric function using the hole diameter x as a variable can be used. In addition, the approximate expression may be set for each section by dividing the characteristic line of FIG. 8 into a plurality of sections for the hole diameter.
[0040]
FIG. 9 shows an example in which a quadratic function having the hole diameter x as a variable is adopted as the correction term Id. In this example, the hole diameter x is divided into four sections, and each section characteristic is approximated by a quadratic function. The approximate expression in each section in this example is as follows.
Section where hole diameter x is 0.16-0.2;
I = 5.4342-37.169x + 49.802x²
Section in which hole diameter x is 0.2 to 0.3;
I = 2.135-10.877x-6.9965x²
Section in which hole diameter x is 0.3 to 0.38;
I = −81.784 + 493.43x−749.89x²
Section where hole diameter x is 0.38 or more;
I = 22.216-108.59x + 125.61x²
In this example, by using a quadratic function rather than a linear function as an approximate expression, a high degree of correlation is obtained with respect to the actually measured values in each section, and approximation according to the actually measured values is possible.
The correction processing by the correction processing unit 108 has been described above.
[0041]
Here, the description returns to FIG. The arithmetic processing unit 109 shown in the figure refers to the reference database 110 and obtains the film thickness of the remaining film 205 based on the substrate current Ih obtained by the correction processing unit 108 as described below. In this case, the thickness of the remaining film existing in each region is estimated based on the substrate current Ih for each region divided by the boundary of the fine structure obtained by the position detection operation described above.
In this example, the film thickness is estimated using the corrected substrate current Ih. However, when the variation of the substrate current due to the aspect ratio of the hole can be ignored, the substrate current Ik (substrate current measuring device before correction) is corrected. (Value measured at 100) may be used.
First, the principle of deriving the film thickness will be described. As shown in FIG. 10, the substrate current generated with the irradiation of the electron beam exhibits a characteristic having a peak value with respect to the increase and decrease of the film thickness. For this reason, the film thickness cannot be uniquely specified from the measured value of the substrate current. Therefore, in this embodiment, focusing on the fact that when the irradiation energy of the electron beam is changed, the value of the film thickness indicating the peak value tends to move, the irradiation energy of the electron beam when measuring the substrate current is at least 2. The film thickness is specified from the substrate current characteristics obtained for each irradiation energy.
[0042]
Here, the method for deriving the film thickness will be specifically described by taking as an example the case of detecting the film thickness of the remaining film 250 shown in FIG. In order to simplify the description, it is assumed that the insulator 220 and the gate electrode 210 are not present on the lower layer side of the remaining film, and the remaining film 250 is formed directly on the substrate (not shown). .
First, as shown in FIG. 10, the characteristics of the substrate current and the film thickness with respect to at least two types of irradiation energy are measured in advance according to the type of the remaining film to be measured. In the example shown in the figure, the solid line indicates the characteristic when the irradiation energy is V1 (for example, 500 V), and the dotted line indicates the characteristic when the irradiation energy is V2 (for example, 1500 V). These characteristics are stored in the reference database 110 as reference data.
In this example, the reference data when the remaining film is formed directly on the substrate is stored in the reference database 110. In this reference database 110, the actual device structure on the lower layer side of the remaining film is stored. The reflected reference data is stored. The reference data is measured for a plurality of predetermined irradiation energy values of the electron beam and a film thickness value that can be taken by the remaining film forming the bottom of the hole 240 to be specified, and the plurality of irradiation energy values. A correspondence relationship with the power substrate current value is described.
[0043]
Subsequently, the residual film 250 is irradiated with an electron beam with irradiation energy at which each characteristic of the reference database 110 is obtained, and the substrate current Ik at that time is measured. Here, the substrate current when the irradiation energy is V1 is Ik (V1), and the substrate current when the irradiation energy is V2 is Ik (V2). Subsequently, in FIG. 10, the film thicknesses T1 and T2 when the substrate current is Ik (V1) are obtained from the characteristics when the irradiation energy is V1, and the above-described characteristics are obtained when the irradiation energy is V2. The substrate current values I1 and I2 are obtained for the film thicknesses T1 and T2. Of these values I1 and I2, the one that approximates the substrate current Ik (V2) obtained by the above measurement is determined, and one of the film thicknesses T1 or T2 corresponding to the determined substrate current value is determined as the remaining film. Adopted as a film thickness of 250. That is, a film thickness at which the substrate current measured for each irradiation energy satisfies both the characteristics shown in FIG. 10 is adopted as the remaining film thickness of 250. The method for deriving the film thickness of the remaining film 250 has been described above.
[0044]
Next, the arithmetic processing unit 109 performs image processing for visually displaying the film thickness of the remaining film at the bottom of the hole. That is, the arithmetic processing unit 109 performs the hole position detection process described above in addition to the film thickness derivation process described above, and obtains a value Pa on each scanning line as shown in FIG. In this example, since a plurality of fragmented residual films are scattered at the bottom of the hole, there are many points represented by a value Pa on one scanning line. Then, as shown by dotted lines in the figure, image data representing line segments connecting corresponding points on each scanning line is generated. Further, in the same figure, sections A, B, C, etc. between the points on each scanning line represent areas having the same vertical structure, and the above-described image data includes the film thickness of each area. As the data representing the thickness, the value of the film thickness obtained by the above-described processing is added.
[0045]
Based on the image data generated by the arithmetic processing unit 109, the display control unit 111 causes the display unit 112 to display an image representing the boundary and film thickness of the fine structure at the bottom of the hole, as shown in FIG. In this way, the bottom of the hole is displayed two-dimensionally, and each region corresponding to the film thickness of the remaining film is displayed, for example, by changing the color. Thereby, the structure of the bottom of the hole can be grasped three-dimensionally. In addition, it is possible to grasp the shift in the rotation direction of the insulating film at the bottom of the hole in the STI structure, and the insulating film squeezing (excess etching). Further, a vertical section may be generated from the film thickness value obtained by the arithmetic processing unit 109, and the film thickness distribution at the bottom of the hole may be displayed in a three-dimensional manner.
As can be understood from the above description, according to this semiconductor device analysis apparatus, even when the aspect ratio increases as the hole diameter decreases, the boundary, step, or film thickness of the fine structure at the bottom of the hole can be accurately determined. It becomes possible to grasp.
[0046]
Hereinafter, examples of other device structures that can be analyzed by the semiconductor device analysis apparatus will be described with reference to FIGS.
In the example shown in FIG. 13, a step-like residual film 251 exists at the bottom of the hole 240 shown in FIG. In this case, the substrate current Ik takes a value corresponding to the thickness of the remaining film 251. In this example, in the section corresponding to the gate electrode 210, the waveform of the substrate current Ik is stepped, and the film thickness of the remaining film 240 is reflected in the substrate current Ik. Therefore, even in such a fine structure, the position of the boundary and the film thickness can be analyzed using this semiconductor device analysis apparatus.
[0047]
In the example shown in FIG. 14, the insulator 221 having a smaller film thickness than the insulator 220 in FIG. 3 is present. In this example, since the number of electrons penetrating through the insulator 221 appearing at the bottom of the hole increases, the substrate current Ik in the section corresponding to the insulator 221 increases as compared with the structure shown in FIG. Since the value is different from the substrate current Ik in the section corresponding to the electrode 210, the boundary can be analyzed using this semiconductor device analysis apparatus even in such a fine structure. Note that the substrate current waveform indicated by a dotted line in the figure shows a case where the irradiation energy of the electron beam is changed in order to analyze the film thickness.
[0048]
In the example shown in FIG. 15, the residual film 252 exists on the gate electrode 210 in accordance with the position corresponding to the insulator 221 appearing at the bottom of the hole in FIG. 14 described above. Since the waveform of the substrate current Ik measured in this case is the same as that shown in FIG. 14 described above, the vertical structure cannot be distinguished even if the position of the boundary can be grasped as it is. Therefore, the substrate current (waveform shown by the dotted line in FIG. 15) is measured while changing the irradiation energy of the electron beam, and the difference in the vertical structure is grasped from the substrate current characteristics at this time. FIG. 16 shows an example of substrate current characteristics by a combination of members of different materials. The example shown in FIG. 11A shows the characteristics when silicon oxide (SiO 2) is stacked on a silicon (Si) substrate, and the example shown in FIG. In each figure, the dotted line indicates the characteristics when the irradiation energy is 1500V, and the solid line indicates the characteristics when the irradiation energy is 500V.
[0049]
As understood from the figure, the substrate current for each irradiation energy is different even with the same film thickness. By utilizing this difference in characteristics, the structures shown in FIGS. 14 and 15 can be determined. Specifically, when the substrate currents measured with the electron beam irradiation energy of 500 V and 1500 V are a and b, in the characteristics shown in FIG. 16A, the same film thickness T that gives the substrate currents a and b is the same. Although it exists, it does not exist in the characteristics shown in FIG. Therefore, in this example, it can be understood from the measured value that the combination of materials is a combination of Si and SiO2. In this way, the substrate current measured by changing the irradiation energy is prepared for the required combination of materials, and by using this as reference data, the combination of the material of the remaining film can be calculated from the measured substrate current value. The film thickness can be known, and the structure shown in FIGS. 14 and 15 can be determined.
[0050]
Next, in the example shown in FIG. 17, the remaining film 251 exists uniformly over the entire bottom surface of the hole in place of the remaining film 252 in FIG. 15 described above. In this case, the substrate current in the section corresponding to the gate electrode 210 is reduced as compared with the structure shown in FIG. 15. However, the position of the boundary between the insulator 221 and the gate electrode 210 is determined from the change (step) in the substrate current. I can grasp it.
The example shown in FIG. 18 has a residual film 253 having four types of film thickness at the bottom of the hole, and the film thickness of the residual film 253 has two values for each of the insulator 221 and the gate electrode 210. I'm taking it. Also in this case, it is possible to distinguish between the insulator 221 and the gate electrode 210 by changing the irradiation energy of the electron beam. Thereby, in addition to the boundary position between the insulator 221 and the gate electrode, the film thickness of the remaining film 253 can also be grasped.
[0051]
In the example shown in FIG. 19, there is no residual film at the bottom of the hole 240, and the gate electrode 210 appears over the entire bottom of the hole. In this case, most of the electron beams irradiated to the holes 240 penetrate the gate electrode 210, and a relatively large substrate current Ik that is substantially constant is measured in a section corresponding to the hole diameter. As a result, it is understood that there is no remaining film at the bottom of the hole 240.
In the example shown in FIG. 20, the remaining film 251 is uniformly present at the bottom of the hole 240 in FIG. 19 described above, and the measured substrate current is smaller than that in the structure of FIG. Therefore, the presence of the remaining film 251 can be grasped from this substrate current.
In the example shown in FIG. 21, the insulator 220 is located at the entire bottom of the hole 240, and the remaining film 253 is present at the bottom of the hole. In this case, the electron beam cannot reach the substrate by the insulator 220, and therefore the substrate current Ik is not measured. From this, it can be understood that the gate electrode 210 is not located at the bottom of the hole 240. In this case, since the substrate current is not measured, it cannot be grasped even if the film thickness of the remaining film changes.
[0052]
In the example shown in FIG. 22, a relatively thin insulator 221 is located on the entire bottom of the hole 240, and the remaining film 251 exists uniformly on the bottom of the hole. In this case, the electron beam reaches the substrate, and the substrate current Ik is measured. Therefore, by measuring the substrate current Ik while changing the irradiation energy of the electron beam, it can be distinguished from the structure shown in FIG. 21 in which the remaining film exists on the gate electrode.
In the example shown in FIG. 23, the insulator 221 is located at the entire bottom of the hole 240, and the relatively thick residual film 253 is unevenly present at the bottom of the hole. In this case, the electron beam does not reach the substrate by the remaining film 253 and the insulator 221, and the substrate current Ik is not measured. Therefore, as in the case shown in FIG. 21, it can be understood that the gate electrode 210 is not located at the bottom of the hole 240.
[0053]
In the example shown in FIG. 24, a part of wiring having a three-layer structure of aluminum (AL), titanium (Ti), and titanium nitride (TiN) protrudes from the bottom of the hole 240. In this case, a part of the bottom of the hole 240 is narrowed by a three-layer wiring to form a narrow region 240A, and the influence of the aspect ratio described above becomes significant in the narrow region 240A. For this reason, even if the insulator 222 exists on the bottom side of the hole 240, the substrate current Ik is measured, and the etching amount (depth of the narrow region 240A) on the side of the three-layer wiring is obtained from this substrate current. it can. In this case, the correction processing by the correction processing unit 108 described above is not performed, and the substrate current data stored in the storage unit 107 is supplied to the arithmetic processing unit 109 as it is. In FIG. 24, the substrate current in the section corresponding to the wiring (TiN / Ti / AL) having a three-layer structure at the bottom of the hole is prominent. This is because the wiring passes through a diffusion layer (not shown). This is because it is connected to the board.
[0054]
In the example shown in FIG. 25, the remaining film 254 exists in the narrow region 204A in FIG. 24 described above. In this case, the substrate current in the section corresponding to the narrow region 204A is reduced as compared with the structure of FIG. 24, but the substrate current is generated due to the influence of the aspect ratio. Therefore, by measuring the substrate current while changing the irradiation energy of the electron beam, the remaining film 254 exists on the TiN in the hole, or exists in a narrow region (240A) beside the wiring. You can see if there is.
[0055]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
That is, the substrate current value is measured by scanning the electron beam with respect to the concave portion formed on the main surface of the semiconductor substrate, and the boundary of the fine structure located on the bottom side of the concave portion is determined based on the measured substrate current value. Since it is calculated and displayed, the substrate current, which is the detection signal, is not weakened by the aspect ratio, so even a hole with a large aspect ratio can accurately analyze the bottom microstructure. Become.
In addition, since the position information that gives the boundary is obtained by calculating the differential amount of the substrate current, the boundary of the fine structure can be specified from the substrate current.
[0056]
In addition, since the film thickness is estimated based on the substrate current value for each region divided by the boundary, the hole structure can be grasped three-dimensionally.
In addition, since a plurality of irradiation energy values of the electron beam are provided with reference data indicating a correspondence relationship between a film thickness value that can be taken by the remaining film that forms the bottom of the concave portion and a substrate current value, the film thickness is determined from the substrate current. Can be specified.
Further, since the inner diameter of the concave portion is measured and the substrate current value is corrected by reflecting the inner diameter of the concave portion, it becomes possible to remove the fluctuation of the substrate current depending on the inner diameter of the concave portion.
Further, since the inner diameter is obtained from the relationship between the irradiation position of the electron beam and the substrate current value, it is possible to accurately grasp the inner diameter even if the diameter of the recess is reduced.
[0057]
In addition, since the correction amount of the substrate current value is calculated using the equation I = α + β · x · exp (−γ · x), the fluctuation of the substrate current depending on the inner diameter of the recess is accurately expressed. It becomes possible to do.
Further, since the aspect ratio of the recess is used in place of the inner diameter of the recess, the structure of the recess can be analyzed in consideration of the variation of the substrate current depending on the aspect ratio.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor device analysis apparatus according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a correction processing unit according to the embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a first example of a microstructure according to an embodiment of the present invention.
FIG. 4 is a diagram for explaining the principle of hole position detection according to the embodiment of the present invention.
FIG. 5 is a diagram for explaining a method of detecting a boundary of a fine structure according to an embodiment of the present invention.
FIG. 6 is a diagram showing a second example of a microstructure according to the embodiment of the present invention.
FIG. 7 is a characteristic diagram for explaining correction terms used for correction processing in the correction processing unit according to the embodiment of the present invention.
FIG. 8 is a characteristic diagram for explaining a correction term used in another correction process (approximation by a linear function) in the correction processing unit according to the embodiment of the present invention.
FIG. 9 is a characteristic diagram for explaining correction terms used for other correction processing (approximation by a quadratic function) in the correction processing unit according to the embodiment of the present invention.
FIG. 10 is a characteristic diagram for explaining a film thickness derivation method in the arithmetic processing unit according to the embodiment of the present invention.
FIG. 11 is a diagram for explaining display processing according to the embodiment of the present invention.
FIG. 12 is a view showing a display example of a hole bottom according to an embodiment of the present invention.
FIG. 13 is a diagram showing a third example of a microstructure to be analyzed according to the embodiment of the present invention.
FIG. 14 is a diagram showing a fourth example of a microstructure to be analyzed according to the embodiment of the present invention.
FIG. 15 is a diagram showing a fifth example of a microstructure to be analyzed according to the embodiment of the present invention.
FIG. 16 is a view for explaining the film thickness analysis principle in the fifth example of the microstructure to be analyzed according to the embodiment of the present invention;
FIG. 17 is a diagram showing a sixth example of a microstructure to be analyzed according to the embodiment of the present invention.
FIG. 18 is a diagram showing a seventh example of a microstructure to be analyzed according to the embodiment of the present invention.
FIG. 19 is a diagram showing an eighth example of a microstructure to be analyzed according to the embodiment of the present invention.
FIG. 20 is a diagram showing a ninth example of a fine structure to be analyzed according to the embodiment of the present invention.
FIG. 21 is a diagram showing a tenth example of a microstructure to be analyzed according to the embodiment of the present invention.
FIG. 22 is a diagram showing an eleventh example of a fine structure to be analyzed according to the embodiment of the present invention.
FIG. 23 is a diagram showing a twelfth example of a microstructure to be analyzed according to an embodiment of the present invention.
FIG. 24 is a diagram showing a thirteenth example of a fine structure to be analyzed according to an embodiment of the present invention.
FIG. 25 is a diagram showing a fourteenth example of a microstructure to be analyzed according to the embodiment of the present invention.
FIG. 26 is a diagram showing a first example of a microstructure according to a conventional technique.
FIG. 27 is a diagram showing a second example of a fine structure according to the prior art.
FIG. 28 is a diagram showing a third example of a microstructure according to a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100; Substrate current measuring apparatus, 101; Electron beam generation part, 102; Moving stage, 103; Electron beam control part, 104; Electrode, 105; Substrate current detection part, 106; Position detection part, 107; Correction processing unit 108A; film thickness storage unit 108B; hole diameter calculation unit 108C; aspect ratio calculation unit 108D; correction calculation unit 109; calculation processing unit 110; reference database 111; display control unit 112; Display section.

Claims (14)

A current measuring means for scanning a semiconductor substrate with an electron beam and measuring a substrate current generated in the semiconductor substrate as the electron beam is scanned;
An inner diameter measuring means for measuring the inner diameter of the recess formed on the semiconductor substrate;
Current correcting means for correcting the substrate current value measured by the current measuring means to reflect the inner diameter of the recess measured by the inner diameter measuring means;
Boundary calculation means for calculating a boundary of a fine structure formed on the semiconductor substrate based on the substrate current corrected by the current correction means;
Display means for displaying the boundary obtained as a calculation result of the boundary calculation means;
Equipped with,
The current correction means is
A semiconductor device characterized in that the substrate current value measured by the current measuring means is corrected so as to cancel the fluctuation of the substrate current caused by charging of the inner wall of the concave portion with the irradiation of the electron beam. Analysis device. The boundary calculation means is
2. The semiconductor device analyzing apparatus according to claim 1, wherein position information giving a boundary of the fine structure is obtained by calculating a differential amount of the substrate current.   A film thickness estimation means for estimating the film thickness of the remaining film existing in each area based on the substrate current value measured by the current measurement means for each area divided by the boundary of the fine structure. 3. The semiconductor device analysis apparatus according to claim 1, wherein the semiconductor device analysis apparatus is characterized in that The film thickness estimation means is
It represents the correspondence between the film thickness value that can be taken by the remaining film that forms the bottom of the recess and the substrate current value that should be measured for the plurality of irradiation energy values with respect to the plurality of irradiation energy values of the electron beam. Reference data storage means for storing reference data;
Based on the substrate current value measured by the current measurement means for the plurality of irradiation energy values, the film thickness specifying means for specifying the film thickness of the remaining film with reference to the reference data;
The semiconductor device analysis apparatus according to claim 3, comprising: The inner diameter measuring means is
2. The semiconductor device analysis apparatus according to claim 1 , wherein an inner diameter of the concave portion is obtained from a relationship between an irradiation position of the electron beam and the substrate current value. The current correction means is
When the substrate current of the semiconductor substrate is I, the inner diameter of the recess is x, the constant is α, and the positive constants are β and γ,
I = α + β · x · exp (−γ · x)
Using mathematical expression, a semiconductor device analyzer according to claim 1, characterized in that to calculate the correction amount of the measured substrate current value by said current measuring means. Semiconductor device simulation apparatus according to any one of claims 5 or 6 characterized by using the aspect ratio of the recess instead of the inner diameter of the recess. The current correction means is
Using an approximate expression that approximates the relationship between the inner diameter of the recess formed in the reference semiconductor substrate and the substrate current generated by scanning the electron beam with respect to the recess, the substrate current measured by the current measuring means is The semiconductor device analyzer according to claim 1 , wherein correction is performed. 9. The semiconductor device analysis apparatus according to claim 8 , wherein the approximate expression is set for each section obtained by dividing the characteristic with respect to the inner diameter. The approximate expression, the semiconductor device simulation apparatus according to any one of claims 8 or 9, characterized in that a linear function of the inner diameter as a variable. The approximate expression, the semiconductor device simulation apparatus according to any one of claims 8 or 9 characterized in that it is a quadratic function of the inner diameter as a variable. A first step of scanning the semiconductor substrate with an electron beam and measuring a substrate current value generated in the semiconductor substrate as the electron beam is scanned;
A second step of calculating an inner diameter of a hole formed on the semiconductor substrate based on the measured substrate current value;
A third step of calculating an aspect ratio of the hole using an inner diameter of the hole obtained as a result of the calculation;
A fourth step of correcting the substrate current value based on the aspect ratio;
A fifth step of evaluating a fine structure inside the hole based on the corrected substrate current value;
Only including,
In the fourth step, the correction term (Id) of the substrate current is calculated using an approximate expression having an aspect ratio (s) and a film thickness value (d) as variables . It further claims 1 comprises means for identifying a plurality of substrate current value the thickness of the residual film present on the semiconductor substrate which occurs when the electron beams at a plurality of different irradiation energy is irradiated on the semiconductor substrate 11 of The semiconductor device analysis apparatus described in any one of the items. 13. The method according to claim 12 , further comprising a step of identifying a film thickness of a remaining film existing on the semiconductor substrate from a plurality of substrate current values generated when the semiconductor substrate is irradiated with an electron beam with a plurality of different irradiation energies. Semiconductor device analysis method.

Images