JP4085201B2 - Communications system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a communication system, and more particularly to synchronization control in communication using a spread code.
[0002]
[Prior art]
Conventionally, in a communication system using a spreading code such as CDMA (code division multiplexing), the synchronization of the chip clock and the synchronization of the code phase for generating the spreading code are performed separately. That is, for the synchronization of the chip clock, a pilot signal not subjected to information modulation is transmitted and received, and the chip clock is synchronized with the transmission side by absolute phase synchronization demodulation on the reception side. The code phase is synchronized using a matched filter, a sliding correlator, or the like.
[0003]
[Problems to be solved by the invention]
In synchronization using a matched filter, there is a problem that the circuit scale on the receiving side increases. In addition, the synchronization using the sliding correlator has a problem that the burden on the control software is large.
[0004]
The present invention has been made in view of the above problems, and provides a communication system capable of realizing chip clock synchronization and code phase synchronization with a simple configuration.
[0005]
[Means for Solving the Problems]
In order to solve the above problem, a communication system according to the present invention includes a transmission device and a reception device, and the transmission device includes a transmission-side chip clock generation circuit that generates a transmission-side chip clock, and the transmission-side chip clock. A transmission-side spread signal generation circuit that generates a transmission-side spread signal whose amplitude changes in accordance with a predetermined spread code, and a modulation circuit that generates a modulation signal including the transmission-side spread signal as an amplitude component .
[0006]
In addition, the receiving device generates a receiving side chip clock generating circuit that generates a receiving side chip clock, and a receiving side that generates a receiving side spread signal whose amplitude changes corresponding to the predetermined spreading code based on the receiving side chip clock. Generating an error signal corresponding to a phase shift between the side spread signal generation circuit, the transmission side spread signal included as an amplitude component in the modulated signal received from the transmission device, and the reception side spread signal; A receiving-side chip clock control circuit that controls the receiving-side chip clock generation circuit based on the error signal.
[0007]
The reception-side chip clock control circuit is configured to generate a window signal for specifying a predetermined portion of the reception-side spread signal, the window-side generation signal based on the window signal and the transmission-side spread signal. And an error signal generation circuit that generates a signal representing a phase shift between the predetermined portion of the spread signal and the predetermined portion of the transmission side spread signal as the error signal. The predetermined portion is, for example, a rising portion or a falling portion of each spread signal.
[0008]
According to the present invention, an error signal corresponding to a phase shift between the transmission side spread signal and the reception side spread signal included in the modulation signal is generated, and the reception side chip clock is controlled based on the error signal. Thus, the synchronization of the chip clock and the synchronization of the code phase can be realized with a simple configuration.
[0009]
Further , the window signal generation circuit has a phase advance side reception spread signal whose phase is advanced by 1/2 chip from the reception side spread signal and a phase by 1/2 chip based on the reverse phase signal of the reception side chip clock. A delayed delayed phase reception side spread signal is generated, and the advanced phase received side spread signal and the delayed phase received side spread signal are respectively input to the flip-flop circuit, and the exclusive OR of the output signals of the flip-flop circuits is further input. May be generated and used as the window signal.
[0010]
In one aspect of the present invention, the modulation circuit spreads an information signal with a spread signal obtained by delaying the transmission side spread signal by a predetermined information multiplexing phase, and transmits the spread information signal to the transmission Multiplexed with the side spread signal to generate the modulated signal. A plurality of predetermined information multiplexing phases may be set, and each information signal may be spread and multiplexed with each spread signal obtained by delaying the transmission side spread signal by that phase.
[0011]
In this aspect, the modulation circuit includes the transmission side spread signal, the transmission side subspread signal obtained by delaying the transmission side spread signal by a predetermined subspread signal multiplexing phase, the spread information signal, And the reception apparatus despreads the modulation signal with the reception side spread signal and delays the reception side spread signal by the predetermined sub-spread signal multiplexing phase. The modulated signal is despread with the spread signal obtained in this way, and the reception-side chip clock control circuit limits the control of the reception-side chip clock generation circuit based on the result of the despreading in the demodulation circuit It may be.
[0012]
In this case, the predetermined sub-spreading signal multiplexing phase and the predetermined information multiplexing phase are the phase difference between the predetermined sub-spreading signal multiplexing phase and the predetermined information multiplexing phase, and the predetermined sub-spreading signal. It may be set so that the multiplexing phase does not match. The modulation circuit spreads a plurality of information signals by spreading signals obtained by delaying a plurality of predetermined information multiplexing phases corresponding to the information signals, and the spread information signals are transmitted to the transmission side. Multiplexed together with a spread signal to generate the modulated signal, and the predetermined sub-spread signal multiplexing phase and the predetermined information multiplexing phase are defined by the interval between the predetermined information multiplexing phase and the predetermined sub-spread signal multiplexing. It may be set so that the use phase does not match. In this way, even if the information signal is a direct current, it is possible to prevent the spread signal related to the information signal and the reception side spread signal from being erroneously synchronized.
[0013]
In one aspect of the present invention, the receiving device receives from the transmitting device based on a signal obtained by despreading the modulated signal including the transmitting-side spread signal based on the receiving-side spread signal. An amplitude control circuit for controlling the amplitude of the modulation signal is further included. In this way, the amplitude of the received modulation signal can be made favorable.
[0014]
In this aspect, the amplitude control circuit is based on a signal obtained by smoothing a signal obtained by despreading the modulation signal including the transmission side spread signal based on the reception side spread signal. The amplitude of the modulated signal received may be controlled. Smoothing may be performed using, for example, a low-pass filter.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.
[0016]
The communication system described below realizes the synchronization of the chip clock and the code phase between the transmitting and receiving apparatuses required when transmitting multiple channels simultaneously by CDMA (code division multiplexing) with a relatively simple configuration. .
[0017]
In this communication system, in the transmission device, the same PN code is used with different phases (delayed) to spread each information signal (information channel), and the spread information signal thus obtained is multiplexed to generate a modulated signal. Is generated. On the other hand, the receiving apparatus demodulates each information channel by despreading the modulated signal using the same PN code with different phases (delayed). That is, this communication system spreads a plurality of information channels with the same PN code, and the phase (delay amount) of the spread code is assigned to each information channel.
[0018]
In this communication system, in the transmission apparatus, one or more code phase outputs of the PN code are used as pilot signals that are not modulated with information signals. Further, the receiving apparatus uses the same PN code as the transmitting side generated by the chip clock of the receiving apparatus, compares the phase of the one or more code phase outputs with the received pilot signal, and compares them. A signal representing the result (error signal) is fed back to a voltage controlled oscillator (VCO) that forms a chip clock. As a result, the chip clock and the code phase are successfully synchronized with a simple configuration.
[0019]
(Embodiment 1)
1 and 2 are diagrams showing a configuration of a communication system according to Embodiment 1 of the present invention. FIG. 1 shows the configuration of the transmitting apparatus, and FIG. 2 shows the configuration of the receiving apparatus.
[0020]
As shown in FIG. 1, the transmission apparatus 10 includes an oscillator 12, a spread code generator 14, and a modulation circuit 26.
[0021]
The oscillator (chip clock generation circuit) 12 is a circuit that generates a transmission-side chip clock. The spread code generator 14 is a circuit that generates a transmission side spread signal based on the transmission side chip clock. The spreading code generator 14 receives the transmission side chip clock output from the oscillator 12 and outputs a transmission side spread signal. Here, the spread signal T0 related to the predetermined PN code is generated.
[0022]
The modulation circuit 26 is a circuit that generates a modulation signal S including the transmission side spread signal T0 as an amplitude component. Specifically, the modulation circuit 26 receives the information signals I1 to I3 and the spread signal T0 output from the spread code generator 14, and outputs the modulation signal S. More specifically, the modulation circuit 26 includes a shift register 16, multipliers 20-1 to 20-3, an attenuator 18, and an adder 22. A spread signal T0 output from the spread code generator 14 is input to the shift register 16, and a spread signal T1 (tap signal) obtained by delaying the spread signal T0 by a phase θ1 is delayed by a phase θ2. The spread signal T2 (tap signal) and the spread signal T3 (tap signal) delayed by the phase θ3 are output. The spread signal T0 output from the spread code generator 14 is attenuated by the attenuator 18 by an attenuation amount corresponding to the multipliers 20-1 to 20-3, and is also input to the adder 22. The multiplier 20-n receives the spread signal Tn output from the shift register 16 and the information signal In. The multiplier 20-n multiplies both signals and outputs a spread information signal In (n = 1, 2, 3). The spread information signals I1 to I3 are input to the adder 22 together with the output of the attenuator 18, that is, the attenuated spread signal T3, and are added (multiplexed) here. The output of the adder 22 is sent as a modulation signal S to a communication medium 24 such as a wire or air. The modulated signal S output from the adder 22 as described above includes a component corresponding to the PN code that is the basis of the spread signal T0 in its amplitude change (voltage change).
[0023]
As described above, phase 0 is assigned to the pilot channel and phase θn is assigned to information channel n (n = 1, 2, 3), and a plurality of information signals are spread-modulated with different phases using the same PN code. The signal is multiplexed with the pilot signal, and the modulated signal S is sent to the communication medium 24.
[0024]
On the other hand, as shown in FIG. 2, the receiving device 30 includes a chip clock generation circuit 34, a spread code generator 42, a demodulation circuit 40, a chip clock control circuit 38, and an amplitude control circuit 65. ing.
[0025]
The chip clock generation circuit 34 is a circuit that generates a reception-side chip clock, and includes a voltage-controlled oscillator 32 and a flip-flop 36. The voltage controlled oscillator 32 is an oscillator that oscillates at a frequency twice that of the oscillator 12, and controls the frequency and / or phase of the clock signal output based on the error signal E output from the chip clock control circuit 38. It is configured to be able to.
[0026]
The flip-flop 36 divides the clock signal output from the voltage-controlled oscillator 32 by 1/2, generates a clock signal having a frequency similar to that of the chip clock output from the oscillator 12 as a receiving-side chip clock, and generates a spreading code. The generator 42 is supplied. The flip-flop 36 further generates a chip clock (phase chip clock) having a phase opposite to that of the receiving-side chip clock, and supplies it to the chip clock control circuit 38.
[0027]
The spread code generator 42 is a circuit that generates the reception side spread signal T0 ′ based on the reception side chip clock output from the chip clock generation circuit 34 as described above. The reception-side spread signal T0 ′ relates to the same PN code as that on the transmission side. That is, the reception side spread signal T0 ′ includes a component corresponding to the PN code in its amplitude change (voltage change). The reception side spread signal T0 ′ thus generated is input to the demodulation circuit 40.
[0028]
The demodulation circuit 40 is a circuit that despreads the modulation signal S with a spread signal Tn ′ obtained by delaying the reception-side spread signal T0 ′ by the phase θn and demodulates the information signal In (n = 1, 2, 3). Specifically, the demodulation circuit includes a shift register 56, low-pass filters 60-1 to 60-3, and multipliers 58-1 to 58-3. A spread signal T0 ′ output from the spread code generator 42 is input to the shift register 56, and a spread signal T1 ′ (tap signal) obtained by delaying the spread signal T0 ′ by the phase θ1 and only the phase θ2. The delayed spread signal T2 ′ (tap signal) and the spread signal T3 ′ (tap signal) delayed by the phase θ3 are output. The multiplier 58-n receives the spread signal Tn ′ output from the shift register 56 and the modulation signal S received from the transmission device 10. The multiplier 58-n multiplies both signals and inputs the multiplication result to the low-pass filter 60-n. The low-pass filter 60-n extracts the low frequency component of the multiplication result to obtain the information signal In (n = 1, 2, 3).
[0029]
The chip clock control circuit 38 generates an error signal E corresponding to a phase shift between the spread signal T0 multiplexed on the modulation signal S received from the transmitter 10 and the reception-side spread signal T0 ′, and This is a circuit for controlling the chip clock generation circuit 34 based on the error signal E. Here, the error signal E is a signal whose voltage changes corresponding to the difference in rising timing between the spread signal T0 and the reception-side spread signal T0 ′.
[0030]
Specifically, the chip clock control circuit 38 includes a multiplier 44, a low-pass filter 45, a spreading code generator 52, a reset circuit 54, flip-flops 48 and 50, and an exclusive OR circuit 46. The spread code generator 52 receives the anti-phase chip clock output from the chip clock generation circuit 34, and the advanced phase spread signal whose phase has advanced by ½ chip compared to the reception side spread signal T0 ′. Ta and a delayed phase spread signal Tb whose phase is delayed by 1/2 chip are output. A reset signal is supplied to the spread code generator 52 from the reset circuit 54, and the spread code generator 52 is reset for each code cycle of the code signal generated in the spread code generator 42. . For this reason, the code phase difference between the spread code generators 42 and 52 is less than one chip clock. An example of the reset circuit 54 is shown in FIG.
[0031]
The advanced phase spread signal Ta is input to the flip-flop 48, and the flip-flop 50 generates a signal that repeats rising and falling alternately at each rising timing in the advanced phase spreading signal Ta. The delayed phase spread signal Tb is input to the flip-flop 50, and the flop flop 48 generates a signal that repeats rising and falling alternately at each rising timing in the delayed phase spreading signal Tb. An initialization signal is supplied from the flip-flop 48 to the flip-flop 50 so that both flip-flops have the same initial state (Q is set to H and inverted Q is set to L at the time of initialization).
[0032]
Both signals are input to the exclusive OR circuit 46, and the output signal of the exclusive OR circuit 46 is input to the multiplier 44 as the window signal W. This window signal W is a signal for specifying the rising portion of the reception side spread signal T0 ′, and specifically, rises before the rising half chip of the receiving side spread signal T0 ′, and before the next rising half chip. It is a signal that falls on. The multiplier 44 also receives the modulation signal S, and outputs a multiplication result Tc of the modulation signal S and the window signal W. Then, a low frequency component is extracted from the multiplication result Tc by the low-pass filter 45 and is input to the voltage controlled oscillator 32 included in the chip clock generation circuit 34 as an error signal and used for output control.
[0033]
Further, the receiving device 30 includes an amplitude control circuit 65. The amplitude control circuit 65 includes a multiplier 63, a low-pass filter 61, and an automatic gain control circuit (AGC) 59. The multiplier 63 is a circuit that despreads the modulation signal S received from the transmission apparatus 10 with the reception side spread signal T0 ′ output from the spread code generator 42. The output signal of the multiplier 63 is smoothed by the low-pass filter 61, and the control signal obtained thereby is supplied to the automatic gain control circuit 59. The automatic gain control circuit 59 controls the amplitude of the modulation signal S based on this control signal. For example, when the voltage of the control signal is higher than a predetermined reference voltage, the modulation signal S is attenuated, and when the voltage is low, the modulation signal S is amplified. When the transmission-side spread signal T0 and the reception-side spread signal T0 ′ are synchronized, a DC voltage is output from the low-pass filter 61. This DC voltage represents the amplitude of the modulation signal S. For this reason, the amplitude control circuit 65 can appropriately control the amplitude of the modulation signal S.
[0034]
FIG. 4 shows the reception side spread signal T0 ′, the lead phase spread signal Ta, the delayed phase spread signal Tb, the output signal Ta / 2 of the flip-flop 48, the output signal Tb / 2 of the flip-flop 50, the window signal W, and the multiplication result Tc. The vertical axis represents voltage amplitude and the horizontal axis represents time. In the figure, a case where a spread code having a code length of 7 is used for both transmission and reception is shown as an example. The window signal W has a constant pattern that is repeated every 7 chip clocks. When this signal and the transmission side spread signal T0 in the demodulated signal S are phase-compared and a PLL that feeds back the comparison result to the voltage controlled oscillator 32 is configured, the transmission side spread signal T0 is received side spread as shown in FIG. When synchronized with the signal T0 ′, the DC component of the multiplication result Tc becomes zero. Then, the voltage controlled oscillator 32 is in a holding state. When the transmission-side spread signal T0 and the reception-side spread signal T0 ′ are shifted, an error signal E (error voltage) having a positive and negative finite value is generated accordingly.
[0035]
Here, the phase difference between the reception-side spread signal T0 ′ and the transmission-side spread signal T0 due to the difference in frequency between the voltage-controlled oscillator 32 and the oscillator 12 has a sufficiently large loop gain of the PLL, which is a problem. It is assumed that it will not be.
[0036]
According to the communication system described above, the phase of the chip clock and the code phase can be synchronized by a PLL having a relatively simple configuration.
[0037]
(Embodiment 2)
5 and 6 are diagrams showing a configuration of a communication system according to Embodiment 2 of the present invention. FIG. 5 shows the configuration of the transmission apparatus, and FIG. 6 shows the configuration of the reception apparatus. As shown in FIG. 5, the transmission device 70 includes an oscillator 78, a spread code generator 76, and a modulator 75. The modulation circuit 75 includes a shift register 74, a multiplier group 80, and an adder 72. The transmission device 70 differs from the transmission device 10 according to the first embodiment in that two spread signals TP1 and TP2 are multiplexed in the spread information signal group in the adder 72. The spread signals TP1 and TP2 are obtained by delaying the transmission side spread signal generated by the spread code generator 76 itself or by a predetermined amount (here, the spread signal TP2 is more in phase than the spread signal TP1). The phase difference between the spread signals TP1 and TP2 does not match any difference between the phases assigned to each information signal, and the phase assigned to the spread signal TP2 and each information signal, In particular, the phase assignment for the spread signal TP1, the spread signal TP2, and the information channel is determined so as not to coincide with the difference from the one with the least delay from the spread signal TP2. Here, a signal obtained by delaying the spread signal TP1 by the phase θa is defined as a spread signal TP2, and a signal delayed by θa + n × θb is defined as a spread signal for spreading the nth information channel (θa ≠ θb).
[0038]
On the other hand, as shown in FIG. 6, the receiving apparatus 90 includes a chip clock generation circuit 109, a chip clock control circuit 111, a spread code generator 102, and a demodulation circuit 99. The chip clock generation circuit 109 includes the voltage controlled oscillator 110 and the flip-flop 108 as in the case of the first embodiment. The chip clock control circuit 111 includes a switch 112, a low-pass filter 114, a multiplier 116, an exclusive OR circuit 118, flip-flops 120 and 122, a spread code generator 106, a reset circuit 104, and an AND circuit 100. It is comprised including. Further, the demodulation circuit 99 includes a shift register 72, a multiplier group 97, multipliers 94-1 and 94-2, low-pass filters 96-1 and 96-2, and comparators 98-1 and 98-2. ing. The receiving device 90 is different from the receiving device 30 according to the first embodiment in the following points. That is, in the receiving device 90, the demodulating circuit 99 outputs the spread signal TP1 ′ and the spread signal TP2 ′ from the shift register 72, and multiplies these by the multipliers 94-1 and 94-2 to despread them. Getting a signal. Similarly to the transmission side, the shift register 72 outputs a signal obtained by delaying the spread signal TP1 ′ by the phase θa as the spread signal TP2 ′, and despreads the signal delayed by θa + n × θb on the nth information channel. Output as a spread signal (θa ≠ θb).
[0039]
From the despread signals obtained by the multipliers 94-1 and 94-2, low frequency components are taken out by the low-pass filters 96-1 and 96-2 and supplied to the chip clock control circuit 111. In the chip clock control circuit 111, a logical product of these low frequency components is generated by the AND circuit 100, and the switch 112 is controlled by the output. The switch 112 is a circuit for inputting or not inputting the error signal E to the chip clock generation circuit 109. Specifically, if there is an output of the AND circuit 100, the switch 112 is connected to the error signal E. Is input to the chip clock generation circuit 109, and if not, the error signal E is not input to the chip clock generation circuit 109 in an open state.
[0040]
Since the pilot channel is one phase output itself of the transmission side PN code, when the information channel is a DC voltage, the output is also the PN code itself of the other phase, and the synchronization by the PLL is not only the pilot channel but also the information channel. The phenomenon of locking also occurs. According to the communication system according to the second embodiment, transmission of such an information signal (DC voltage) can also be realized.
[0041]
In the present embodiment, the receiving apparatus 90 may be provided with the same configuration as that of the amplitude control circuit 65.
[0042]
【The invention's effect】
As described above, according to the present invention, chip clock synchronization and code phase synchronization can be realized with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a transmission apparatus according to Embodiment 1 of the present invention.
FIG. 2 is a diagram showing a configuration of a receiving apparatus according to Embodiment 1 of the present invention.
FIG. 3 is a diagram illustrating an example of a reset circuit.
FIG. 4 is a timing chart of each part in the communication system according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a configuration of a transmission apparatus according to Embodiment 2 of the present invention.
FIG. 6 is a diagram showing a configuration of a receiving apparatus according to Embodiment 2 of the present invention.
[Explanation of symbols]
10, 70 Transmitter, 12, 78 Oscillator, 14, 42, 52, 76, 102 Spreading code generator, 24 Transmission medium, 26, 75 Modulator, 30, 90 Receiver, 34, 109 Chip clock generator, 38 111 chip clock control circuit, 40, 99 demodulation circuit, 65 amplitude control circuit.

Claims (8)

Including a transmitting device and a receiving device,
The transmitter is
A transmission-side chip clock generation circuit that generates a transmission-side chip clock; and
A transmission-side spread signal generation circuit that generates a transmission-side spread signal whose amplitude changes in accordance with a predetermined spreading code based on the transmission-side chip clock;
A modulation circuit that generates a modulation signal including the transmission-side spread signal as an amplitude component, and
The receiving device is:
A receiving-side chip clock generation circuit for generating a receiving-side chip clock; and
A reception-side spread signal generation circuit that generates a reception-side spread signal whose amplitude changes corresponding to the predetermined spread code based on the reception-side chip clock;
An error signal corresponding to a phase shift between the transmission side spread signal included in the modulated signal received from the transmission device as an amplitude component and the reception side spread signal is generated, and based on the error signal, and the receiver chip clock control circuit for controlling the receiver chip clock generating circuit, only including,
The receiving-side chip clock control circuit is
A window signal generation circuit for generating a window signal for specifying a predetermined portion of the reception side spread signal;
An error signal generation circuit that generates a signal representing a phase shift between a predetermined portion of the reception-side spread signal and a predetermined portion of the transmission-side spread signal as the error signal based on the window signal and the transmission-side spread signal; The communication system characterized by including . The communication system according to claim 1,
The window signal generation circuit is advanced in phase by ½ chip from the reception side spread signal based on the reverse phase signal of the reception side chip clock, and is delayed in phase by ½ chip. The delayed phase reception side spread signal is generated, and the leading phase reception side spread signal and the delayed phase reception side spread signal are respectively input to the flip-flop circuit, and the exclusive OR of the output signals of the flip-flop circuits is further calculated. Window signal,
A communication system characterized by the above. The communication system according to any one of claims 1 to 2,
The modulation circuit spreads an information signal with a spread signal obtained by delaying the transmission side spread signal by a predetermined information multiplexing phase, multiplexes the spread information signal together with the transmission side spread signal, and A communication system characterized by generating a modulation signal . The communication system according to claim 3 ,
The modulation circuit multiplexes the transmission side spread signal, a transmission side subspread signal obtained by delaying the transmission side spread signal by a predetermined subspread signal multiplexing phase, and the spread information signal. Generating the modulated signal;
The receiving apparatus despreads the modulation signal with the reception side spread signal and delays the modulation signal with a spread signal obtained by delaying the reception side spread signal by the predetermined sub-spread signal multiplexing phase. Further including a despreading demodulation circuit;
The reception-side chip clock control circuit limits the control of the reception-side chip clock generation circuit based on the result of the despreading in the demodulation circuit;
A communication system characterized by the above. The communication system according to claim 4,
The predetermined sub-spreading signal multiplexing phase and the predetermined information multiplexing phase are a phase difference between the predetermined sub-spreading signal multiplexing phase and the predetermined information multiplexing phase, and the predetermined sub-spreading signal multiplexing phase. Is set so as to be inconsistent with each other . The communication system according to claim 4 or 5 ,
The modulation circuit spreads a plurality of information signals by spread signals obtained by delaying a plurality of predetermined information multiplexing phases corresponding to each information signal, and spreads the spread information signals to the transmission side spread signal. And multiplex with to generate the modulated signal,
The predetermined sub-spreading signal multiplexing phase and the predetermined information multiplexing phase are set such that an interval between the predetermined information multiplexing phase and the predetermined sub-spreading signal multiplexing phase do not match. A featured communication system. The communication system according to any one of claims 1 to 6 ,
The receiving device is:
An amplitude control circuit for controlling the amplitude of the modulation signal received from the transmission device based on a signal obtained by despreading the modulation signal including the transmission side spread signal based on the reception side spread signal; ,
A communication system characterized by the above. The communication system according to claim 7 ,
The amplitude control circuit is received from the transmission device based on a signal obtained by smoothing a signal obtained by despreading the modulation signal including the transmission side spread signal based on the reception side spread signal. Control the amplitude of the modulation signal,
A communication system characterized by the above.

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