JP4086334B2 - Impurity introduction method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for introducing impurities by adhering or depositing atoms or molecules on a solid surface at a low temperature (particularly in a region from room temperature to extremely low temperature) in the vicinity of the solid surface. Is.
[0002]
[Prior art]
Conventionally, the introduction of impurities into the surface of a silicon substrate as a solid surface includes, for example, a technique described in [Digest of technical papers 1993 symposium on VLSI technology; pp97-98].
[0003]
Specifically, first, a silicon wafer placed in a vacuum chamber is kept at a high temperature (for example, about 800 ° C.), and a gas containing hydrogen is introduced into the vacuum chamber to clean the surface of the silicon wafer. .
[0004]
Next, a gas containing a predetermined element (for example, diborane B ₂ H ₆ ) is introduced into a vacuum chamber containing a cleaned silicon wafer, and simply exposed to the gas to form desired atoms or molecules on the surface of the silicon wafer. Doping is performed by adhering or adsorbing boron. At this time, a doping gas is mainly used to promote the decomposition of the impurity introduction gas introduced into the vacuum chamber, and further promote the diffusion of the impurities in the vacuum chamber to uniformly introduce the impurities into the surface of the silicon wafer. The introduction temperature is around 900 ° C.
[0005]
Next, metal wiring is performed on the silicon wafer on which the doping layer is formed as described above, or a thin oxide film is formed in a predetermined oxidizing atmosphere, and then a gate electrode is formed by a CVD apparatus or the like, and the MOS transistor Is forming.
[0006]
[Problems to be solved by the invention]
As described above, in the conventional impurity introduction method, the surface of the silicon substrate as a solid surface is exposed to a high temperature of 800 ° C. to 900 ° C. Therefore, selective doping by using a resist (so-called novolak type resin or the like). It is impossible to do. This is because a normal resist has a heat resistance limit of about 250 ° C., and at a temperature higher than that, the resist melts and flows, and the pattern itself cannot be formed.
[0007]
In other words, if at least one of the cleaning process and the doping process is performed at a temperature higher than the heat resistant temperature of the resist, selective doping cannot be performed. In the cleaning process, the resist cannot be used if the temperature is high. Simply reducing the temperature does not react the gas (specifically, hydrogen gas) with the surface of the silicon substrate. I can't.
[0008]
More specifically, when a gas containing impurities to be introduced is introduced into a vacuum chamber, impurities are introduced if they are introduced at a low temperature without using a high temperature of 900 ° C. The surface of the substrate needs to be activated rather than simply cleaned. However, if the cleaning process is performed at a high temperature of 800 ° C. as in the prior art, selective impurity introduction using a resist cannot be performed. This is because when the cleaning process is 800 ° C., the resist cannot be used in the cleaning process, so a resist pattern is formed after cleaning, and when the resist pattern is formed, the silicon activated in the cleaning process is activated. This is because the surface of the substrate becomes inactive.
[0009]
In order to selectively introduce impurities at a low temperature at which a resist can be used, the present invention provides a method for introducing impurities that can be performed at a low temperature in which not only a cleaning process but also a doping process can be used. Objective.
[0010]
The resist is very commonly used in the VLSI manufacturing process, and when it cannot be used, it is necessary to form an anti-doping film. Since this anti-doping film (for example, a silicon nitride film) itself is selectively formed using a resist pattern, the process becomes complicated by the selective formation process of the anti-doping film. The increase in cost is inevitable. Further, since the impurity distribution formed by doping diffuses in the depth direction as the temperature increases, it is impossible to make the impurity distribution steep when the doping process is performed at a high temperature.
[0011]
It is an object of the present invention to provide an impurity introduction method that can perform an impurity doping process such as when forming a C-MOS structure at a low temperature without impairing the function of a resist and that does not require the formation of an anti-doping film.
[0012]
[Means for Solving the Problems]
In the method for introducing impurities according to the present invention, an active sample surface is exposed on the surface of a solid sample by plasma irradiation, and the gas or vapor containing the target impurity is exposed to the active sample in a state where plasma irradiation does not act. The impurity is introduced in contact with the sample surface.
[0013]
According to the present invention, the impurity doping process such as the formation of the C-MOS structure can be performed at a low temperature that does not impair the function of the resist.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
In the impurity introduction method according to claim 1, when introducing an impurity in the vicinity of the surface of the solid sample, the sample surface of the solid sample is covered with a resist leaving a portion where the impurity is introduced, and the solid sample covered with the resist is removed. An inert gas containing an inert gas or a reducing gas is introduced into the set vacuum chamber to excite the gas to generate plasma on the surface of the solid sample, and this plasma irradiation does not cover the resist. after exposing the active sample surface to the exposed surface of the solid sample, the resist gas or vapor plasma irradiation of containing said impurity in a state that does not act in contact with the active sample surface of the solid sample and introducing an impurity into the active sample surface of the solid sample exposed without being covered with.
[0018]
The impurity introduction method according to claim 2 introduces an impurity in the vicinity of the surface of the solid sample to form “N-type MOS region and / or other device” and “P-type MOS region and / or other device”. The sample surface of the solid sample is covered with a first resist while leaving a portion for introducing the first impurity, and an inert gas or a reducing gas is set in a vacuum chamber in which the solid sample covered with the first resist is set. An inert gas containing a gas is introduced to excite the gas to generate plasma on the surface of the solid sample, and this plasma irradiation activates the surface of the solid sample exposed without being covered by the first resist. A gas or vapor containing the first impurity is brought into contact with the active sample surface of the solid sample in a state where the sample surface is exposed and plasma irradiation does not act. Wherein after introducing covered the first impurity into the active surface of the sample exposed solid sample without a resist, the resist is removed, a sample of the solid sample, leaving portions for introducing a second impurity Te the surface covered with a second resist, by introducing an inert gas containing the inert gas to the vacuum chamber equipped with a said solid sample covered by the second resist or reducing gas to excite the gas the Plasma is generated on the surface of the solid sample, and the active sample surface is exposed on the surface of the solid sample exposed without being covered with the second resist by irradiation of the plasma, and the irradiation of plasma does not act on the surface. A gas or vapor containing a second impurity is brought into contact with the active sample surface of the solid sample, and the second sample is exposed to the active sample surface of the solid sample exposed without being covered with the resist. And introducing an impurity.
[0019]
(Embodiment 1)
1 to 3 show (Embodiment 1).
In FIG. 1, a silicon substrate 8 that is a target for introducing impurities is set on a holding table 4 in a vacuum chamber 2. The holding table 4 is provided with a cooling means, and the silicon substrate 8 can be kept at a low temperature.
[0020]
A microwave generation source 1 and a high frequency power source 3 are installed in the vacuum chamber 2 to generate plasma. As a gas introduction system introduced into the vacuum chamber 2, a gas feed 10 and a pump 6 that exhausts the gas in the vacuum chamber 2 are installed.
[0021]
2 and 3 show a manufacturing process of a diode using the apparatus shown in FIG.
First, as shown in FIG. 2A, prior to forming a desired impurity layer on the substrate surface 8a of the element region of the silicon substrate 8 in which the element region is separated by the insulating separation film 11, the gas feed 10 is not used. An inert gas containing an active gas (for example, helium, neon, argon, etc.) or a reducing gas (for example, hydrogen) is introduced to generate a plasma 25 on the silicon substrate 8.
[0022]
In this case, the plasma 25 is generated using both the 2.45 GHz microwave generated from the microwave generation source 1 and the high frequency generated from the 13.56 MHz high frequency power source 3. The degree of vacuum when the gas was introduced was about 3 × 10 ⁻⁴ Torr, the output power of the microwave source 1 was about 500 W, and the output power of the high frequency power source 3 was about 300 W.
[0023]
By the irradiation of the plasma thus formed, the natural oxide film on the substrate surface 8a of the silicon substrate 8 is removed, and a clean and active silicon surface is exposed.
When the clean and active silicon surface is exposed, the plasma irradiation is stopped in the next step so that the plasma irradiation does not act on the substrate surface 8a.
[0024]
Next, a gas containing the target impurity to be doped is introduced from the gas feed 10 into the vacuum chamber 2 in an environment in which plasma irradiation is stopped on the substrate surface 8a that has become clean and active as described above. Then, a gas containing impurities is brought into contact with the substrate surface 8a.
[0025]
By this gas introduction, impurities are directly attached to the clean and active substrate surface 8a, and an impurity layer 12 (having a conductivity type opposite to that of the silicon substrate 8) is formed as shown in FIG. More specifically, by stopping plasma irradiation, a shallow impurity layer can be formed by the following mechanism.
[0026]
First, since it is not a plasma gas, the energy possessed by the impurity particles does not increase too much, so that it is not deeply doped. Second, since the plasma diffusion of the impurity particles can be prevented, it is not deeply doped.
[0027]
As described above, the temperature at which the clean and active substrate surface 8a was exposed and the impurities were further introduced was as low as 40 ° C. for both.
Subsequently, as shown in FIG. 3A, an insulating layer 14 such as a CVD silicon oxide film is deposited to a thickness of 500 nm on the silicon substrate 8 into which impurities are introduced. Thereafter, an appropriate heat treatment may be performed to control the impurity distribution. In this embodiment, the heat treatment was performed at 1000 ° C. for 10 seconds. Since high-temperature heat treatment is not performed until this heat treatment is performed, impurities can be introduced shallower than those described in the related art.
[0028]
Finally, as shown in FIG. 3B, an opening 16 is formed in the insulator layer 14 using a photolithography technique and an etching technique, and then a metal single layer film or multilayer is formed to form a metal wiring. A film is formed. Then, the metal film is patterned by using a photolithography technique and an etching technique to form a metal wiring 18 and finish the formation of the diode.
[0029]
As described above, since the substrate surface 8a is exposed to the plasma containing an inert gas or hydrogen in a vacuum, impurities to be introduced to the substrate surface are easily adsorbed, and at a low temperature such as room temperature. Even if it exists, it becomes possible to dope impurities into the silicon substrate.
[0030]
More specifically, a dangling bond is exposed on the substrate surface 8a and becomes chemically very active. When an impurity-containing gas is brought into contact with the substrate surface 8a, the decomposition of the gas is promoted. .
[0031]
In addition, in the reaction at normal temperature in a non-plasma environment, no migration or diffusion of impurities occurred, so that a very shallow junction can be formed. This means that a junction with a depth of about 40 nm, which is required when a fine device of less than 0.1 μm is formed, can be formed.
[0032]
(Embodiment 2)
4 and 5 show (Embodiment 2).
This embodiment shows a process of manufacturing a CMOS semiconductor device by an impurity introduction method using patterning with a resist such as a novolac resin (for example, a photoresist) when introducing impurities.
[0033]
The basic manufacturing process is the same as that described in the above (Embodiment 1). Here, the resist pattern is formed so as to open a region where impurity diffusion is desired. In this way, selective doping can be achieved very easily if impurities are introduced by covering a region other than the region where impurity diffusion is desired with a resist.
[0034]
FIG. 4A is a process in the middle of the manufacturing process of the MOS semiconductor device, and is a stage where the insulating separation film 11 and the gate electrode 20 are formed. In this state, two adjacent MOSs are replaced with P-type MOSs. Separately made into N-type MOS. First, a region where an N-type MOS is to be formed is covered with a resist 22a, and the silicon substrate 8 in this state is set in a vacuum chamber 2 as shown in FIG.
[0035]
An inert gas containing an inert gas or a reducing gas is introduced from the gas feed 10 to form a plasma state. At this time, plasma is generated by using both a 2.45 GHz microwave and a 13.56 MHz high frequency, and the degree of vacuum when the gas is introduced is about 3 × 10 ⁻⁴ Torr. The output power of the source 1 was about 500 W, and the output power of the high frequency power source 3 was about 300 W.
[0036]
By this plasma irradiation, the natural oxide film in the P-type MOS region of the silicon substrate 8 is removed, and a clean and active surface 8a is exposed.
Next, a gas containing, for example, boron as an impurity is introduced from the gas feed 10. By introducing this gas, impurities can be directly attached to the clean and active substrate surface 8a, and an impurity layer 24a that will later become a gate electrode of a P-type MOS and an impurity layer 24b that will become a drain electrode are formed.
[0037]
Next, after removing the resist 22a, as shown in FIG. 4B, the P-type MOS region into which boron has been previously introduced in FIG. 4A is covered with the resist 22b. The procedure for introducing the impurities is the same, but this time, for example, arsenic is doped with a gas containing arsenic to form an impurity layer 26a that later becomes the gate electrode of the N-type MOS and an impurity layer 26b that becomes the drain electrode.
[0038]
Then, after removing the resist 22b, the following steps are performed.
On the silicon substrate 8 into which boron and arsenic impurities are introduced, an insulator such as a CVD oxide film is deposited to a thickness of, for example, 500 nm. Thereafter, an appropriate heat treatment may be performed to control the impurity distribution. In this embodiment, the heat treatment was performed at 1000 ° C. for 10 seconds. An opening 16 is formed in this insulator using a photolithography technique and an etching technique as shown in FIG.
[0039]
Next, in order to form a metal wiring, a metal single layer film or a multilayer film is formed, and the metal film is patterned using a photolithography technique and an etching technique, and the metal wiring is formed as shown in FIG. 18 is formed.
[0040]
In order to maintain good electrical contact between the impurity diffusion layer and the metal layer in the opening of the insulating film, an appropriate impurity distribution may be formed in the impurity layer in the contact portion by using a so-called ion implantation method. Absent. At that time, for example, boron is implanted at an energy of 15 keV and a dose of 5 × 10 ¹⁵ / cm ² into the P-type MOS region, and arsenic is implanted at an energy of 30 keV and a dose of 3 × 10 ¹⁵ / cm ^{2 as} an N-type MOS. do it. Of course, since this value varies greatly depending on the design of the semiconductor device to be manufactured, it is needless to say that an appropriate setting is required although not described in detail here.
[0041]
In each of the above embodiments, electron cyclotron resonance is used as the plasma generating means. However, the present invention is not limited to this, and inductively coupled plasma, helicon, A multi-spiral system, magnetron, dual frequency, triode, LEP (Lisajou Electron Plasma) may be used.
[0042]
In the above embodiment, the case where an N-type MOS region and a P-type MOS region are formed by introducing impurities near the surface of a solid sample has been described as an example. However, a device such as a bipolar device instead of a MOS is described. The impurity introduction method of the present invention introduces an impurity in the vicinity of the surface of the solid sample, and "N-type MOS region and other devices" and "P-type MOS region and Or other devices "may be implemented and effective.
[0043]
In each of the above embodiments, the target impurity to be brought into contact with the clean and active substrate surface 8a is introduced into the vacuum chamber 2 in a gas state, but the evaporation source of the target impurity is disposed in the vacuum chamber 2, and this Doping can be performed in the same manner by bringing the vapor evaporated from the evaporation source into contact with the clean and active substrate surface 8a.
[0044]
【The invention's effect】
As described above, according to the present invention, since the sample surface is exposed to plasma containing an inert gas or the like in a vacuum, doping of impurities can be performed at room temperature, so that an extremely shallow impurity profile can be obtained. In addition, a desired impurity layer can be easily formed only in an arbitrary region while maintaining the function of a resist having no heat resistance. In particular, an “N-type MOS region and / or other device” and a “P-type MOS region” can be formed. And / or other devices "can be made with high precision.
[Brief description of the drawings]
FIG. 1 is a block diagram of a doping apparatus used for introducing impurities according to the first embodiment. FIG. 2 is a process diagram for introducing impurities according to the first embodiment. FIG. 3 is a process for introducing impurities according to the first embodiment. FIG. 4 is a process diagram of impurity introduction in (Embodiment 2). FIG. 5 is a process diagram of impurity introduction in (Embodiment 2).
2 Vacuum chamber 4 Holding stand 6 Pump 8 Silicon substrate 8a Substrate surface 10 Gas feed 11 Insulating separation film 12 Impurity layer 14 Insulator 16 Opening 18 Metal wiring 20 Gate electrodes 22a and 22b Resist

Claims (2)

When introducing impurities near the surface of a solid sample,
Cover the sample surface of the solid sample with a resist leaving a part to introduce impurities,
Introducing an inert gas containing an inert gas or a reducing gas into a vacuum chamber in which the solid sample covered with the resist is set to excite the gas to generate plasma on the surface of the solid sample,
After exposing the active sample surface to the surface of the solid sample exposed without being covered by the resist by this plasma irradiation ,
Impurity into the active sample surface of the solid sample plasma irradiation is exposed without being covered with the resist in contact with the active sample surface of the solid sample gas or vapor containing said impurity in a state does not act Impurity introduction method. When an impurity is introduced near the surface of a solid sample to form “N-type MOS region and / or other device” and “P-type MOS region and / or other device”,
Covering the sample surface of the solid sample with the first resist, leaving a portion for introducing the first impurity,
An inert gas containing an inert gas or a reducing gas is introduced into a vacuum chamber in which the solid sample covered with the first resist is set to excite the gas to generate plasma on the surface of the solid sample. The active sample surface is exposed on the surface of the solid sample exposed without being covered with the first resist by the plasma irradiation, and the gas containing the first impurity in a state where the plasma irradiation does not act or After introducing the first impurity into the active sample surface of the solid sample exposed without being covered with the resist by bringing vapor into contact with the active sample surface of the solid sample ,
Removing the resist;
Covering the sample surface of the solid sample with the second resist leaving a portion for introducing the second impurity,
An inert gas containing an inert gas or a reducing gas is introduced into a vacuum chamber in which the solid sample covered with the second resist is set to excite the gas to generate plasma on the surface of the solid sample. The active sample surface is exposed on the surface of the solid sample exposed without being covered with the second resist by the plasma irradiation, and the gas containing the second impurity in a state where the plasma irradiation does not act or An impurity introduction method for introducing the second impurity into the active sample surface of the solid sample exposed without being covered with the resist by bringing vapor into contact with the active sample surface of the solid sample.

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