JP4093380B2 - Liquid crystal display device having display mode conversion function - Google Patents

Description

【００２６】
【表１】での解像度は常用解像度(active resolution) を示し、（ ）の中の値は総解像度(total resolution)を示す。
【００２７】
【表１】のように、例えば、６４０×４８０の解像度は１０２４×７６８の解像度に変換されるので、変換前の解像度：変換後の解像度＝１：１．６である。この変換方式によると、ホストからの５つのライン分のカラーＲ、Ｇ、Ｂ信号が８つのライン分のカラーＲ、Ｇ、Ｂ信号に変換される。
【００２８】
次に、ＳＶＧＡモード信号が本実施形態のＬＣＤ制御装置に入力される場合、垂直同期信号Ｖ_syncの周波数は同一のままで、水平同期信号Ｈ_syncの周波数及び
ドットクロック信号Ｄｃｌｋの周波数を次の【表２】で示すように約０．２５倍増加させる。これによって、入力される信号がＳＶＧＡモード信号であっても、ＬＣＤ画面上での映像はほとんどＸＧＡモードの解像度で表示できる。これを図１に示す。
【００２９】
【表２】

【００３０】
【表２】での解像度は常用解像度を示し、（ ）の中の値は総解像度を示している。
【００３１】
【表２】のように、例えば、８００×６００の解像度は１０００×７５０の解像度に変換されるので、変換前の解像度：変換後の解像度＝１：１．２８である。但しこの場合は、変換の便宜上、変換前の解像度：変換後の解像度＝１：１．２５となるようにする。この変換方式によると、ホストからの４つのライン分のカラー信号が５つのライン分のカラー信号に変換される。つまり、本発明では入力信号の解像度を変換により高くすることによって、低解像度の信号が入力されてもＬＣＤの画面一杯の映像を表示できるようにするものであり、その目的は、ドットクロック信号をアナログ入力信号の数よりも増加させることにより達成される。
【００３２】
図２はＶＧＡ又はＳＶＧＡモードの信号をＸＧＡモードの信号に変換する本発明のＬＣＤ制御装置の回路の構成を示している。
【００３３】
図２を参照すると、ホストから出力される水平同期信号Ｈ_syncと垂直同期信号Ｖ_syncはマイクロコンピューター１００に入力される。マイクロコンピューター１００は水平同期信号Ｈ_syncと垂直同期信号Ｖ_syncからホストが支援する表示モード（以下、‘ホスト支援表示モード’とする）を判別し、その結果を示す第１及び第２のモード表示信号ＭＤ１、ＭＤ２を発生する。
【００３４】
ホストの支援表示モードがＳＶＧＡモードであるときにはマイクロコンピューター１００からハイレベルの第１のモード表示信号ＭＤ１とハイレベルの第２のモード表示信号ＭＤ２が出力され、ホスト支援表示モードがＶＧＡモードである際にはローレベルの第１のモード表示信号ＭＤ１とハイレベルの第２のモード表示信号ＭＤ２が出力される。また、ホスト支援表示モードがＸＧＡモードである際にはマイクロコンピューター１００からローレベルの第２のモード表示信号ＭＤ２が出力される。この出力信号の変化により、ホストの支援表示モードを判別し、後で行うドットクロック信号増加の割合を適切なものとする。
【００３５】
また、マイクロコンピューター１００からはＸＧＡモード用の水平同期信号である水平出力信号Ｈ_out の一周期当りのドットの数を表示する第１のデータ信号ＴＡと前記水平出力信号Ｈ_out のパルス幅を示す第２のデータ信号ＰＷが提供される。
【００３６】
ドットクロック発生回路２００は二つのＰＬＬ回路２１０、２２０から構成され、ＰＬＬ回路２１０、２２０はメモリの記入動作及び読出動作のための記入ドットクロック信号（Ｗ Ｄｃｌｋ）及び読出ドットクロック信号（Ｒ Ｄｃｌｋ）をそれぞれ発生する。
【００３７】
水平出力発生回路３００はホストから提供される垂直同期信号Ｖ_syncとマイクロコンピューター１００から提供される上記第１及び第２のデータ信号ＴＡ、ＰＷに基づき水平出力信号Ｈ_out を発生する。この際、前記水平出力信号Ｈ_out は水平同期信号（Ｈ_sync：以下‘Ｈ_in’と示す）に同期して発生する。
【００３８】
図２に示すように、本発明の装置は、Ｒ、Ｇ、Ｂ信号にそれぞれ対応する３つのメモリブロック４１０ａ、４１０ｂ、４１０ｃ及び出力選択部４２０を備えたメモリ４００を含んでいる。そしてメモリブロック４１０ａ、４１０ｂ、４１０ｃのそれぞれは少なくとも３つ以上のラインメモリからなる。このラインメモリを３つ以上としたのは、出力信号を水増しするためにある瞬間に記入動作を行うメモリと、読出動作を行うメモリと及び待機中のメモリが必要だからである。尚、この点には後で詳しく触れる。
【００３９】
水平同期信号Ｈ_inとドットクロック発生回路２００及び水平出力発生回路３００の出力はメモリ管理回路５００、メモリ選択制御回路６００、及びフラグ回路７００からなるメモリ制御回路に提供される。メモリ制御回路５００、６００、７００に水平同期信号Ｈ_in及び記入ドットクロック信号Ｗ Ｄｃｌｋが入力され、これにより上記メモリ４００の記入動作が制御される。また、水平出力信号Ｈ_out 及び読出ドットクロック信号Ｒ Ｄｃｌｋがメモリ制御回路５００、６００、及び７００に入力され、これによりメモリ４００の読出動作が制御される。
【００４０】
フラグ回路(flag circuit)５００は、各メモリブロック内で、記入動作と読出動作が遂行されるラインメモリをあらかじめ決まっている順序通りに指定するためのフラグ信号を提供する。
【００４１】
メモリ選択制御回路６００は、各メモリブロックのいずれのラインメモリでも記入動作と読出動作が同時に行われないようにしながら、記入動作及び読出動作が遂行されるラインメモリをそれぞれ選択するメモリ選択信号Ｗ Ｓｅｌ、Ｒ Ｓｅｌを提供する。
【００４２】
そして、メモリ管理回路７００はメモリ選択制御回路６００の指示を受けて各メモリブロックにおけるラインメモリでの記入、読出動作としてのメモリアクセスを管理する。
【００４３】
次に、添付された図面に基づいて本発明によるＬＣＤ制御装置の実施形態を更に詳細に説明する。
【００４４】
図２に示されたように、メモリ４００は３つのメモリブロック４１０ａ、４１０ｂ、４１０ｃと、これらにそれぞれ対応する３つの３×１のマルチプレクサー４２０ａ、４２０ｂ、４２０ｃからなる出力選択回路４２０を具備している。
【００４５】
図３は、図２に示されたメモリブロック４１０ａ、４１０ｂ、及び４１０ｃと、マルチプレクサー４２０ａ、４２０ｂ、及び４２０ｃとメモリ管理回路７００の詳細な構成を示している。図３に示されていない他の二つのメモリブロックも、図面に示されたメモリブロックと同じように、メモリ管理回路７００に接続される。
【００４６】
図３を参照すると明らかなように、各メモリブロック４１０ａ、４１０ｂ、４１０ｃは、３つのラインメモリＬＭ０、ＬＭ１、ＬＭ２から構成される。そして各ラインメモリは少なくとも１３４４words ×８bitsの記憶容量(storage capacity)を有する。
【００４７】
次に、図４は図２に示された出力選択回路４２０の実施形態を示している。図４を参照すると明らかなように、３つの３×１のマルチプレクサー４２０ａ、４２０ｂ、及び４２０ｃのそれぞれの３つの入力端子は、各メモリブロック内のラインメモリＬＭ０、ＬＭ１、ＬＭ２のデータ出力ポート（図示せぬ）にそれぞれ接続される。
【００４８】
各マルチプレクサーはメモリ選択制御回路６００から提供される読出メモリの選択信号Ｒ Ｓｅｌ０、Ｒ Ｓｅｌ１に応答して各メモリブロックのラインメモリＬＭ０、ＬＭ１、ＬＭ２から入力されるデータのいずれか１つを選択して出力する。このマルチプレクサー４２０ａ、４２０ｂ、４２０ｃの出力Ｒ_out 、Ｇ_out 、Ｂ_out はＬＣＤの駆動回路に提供される。
【００４９】
再び、図３を参照する。メモリ管理回路７００は、記入／読出制御部７１０、アドレス発生部７２０、アドレス選択部７３０及び、ドットクロック選択部７４０を含んでいる。記入／読出制御部７１０はメモリ選択制御回路６００から提供される記入メモリ選択信号Ｗ Ｓｅｌに応答して各メモリブロックのラインメモリでなされる記入及び読出動作を制御する。
【００５０】
アドレス発生部７２０は水平同期信号Ｈ_in及び水平出力信号Ｈ_out に応答してメモリの読出動作及びメモリの記入動作のための記入アドレスＷ Ａｄｄ及び読出アドレスＲ Ａｄｄを発生する。アドレス選択部７３０は記入／読出制御部７１０によって制御されており、記入アドレスＷ Ａｄｄ及び読出アドレスＲ Ａｄｄを選択して各メモリブロックのラインメモリＬＭ０、ＬＭ１、ＬＭ２にそれぞれ提供する。
【００５１】
ドットクロック選択部７４０も記入／読出制御部７１０によって制御されており、記入ドットクロックＷ Ｄｃｌｋ及び読出ドットクロックＲ Ｄｃｌｋを選択して各メモリブロックのラインメモリＬＭ０、ＬＭ１、ＬＭ２にそれぞれ提供する。
【００５２】
この装置のＬＣＤの解像度より低い解像度のモード信号がホストから制御装置に提供される場合には、各メモリブロック４１０ａ、４１０ｂ、及び４１０ｃのラインメモリＬＭ０、ＬＭ１、ＬＭ２の記入及び読出動作は次のように遂行される。
【００５３】
各カラー信号と関連し、メモリの記入動作は水平同期信号Ｈ_inに同期して遂行され、またメモリの読出動作は水平出力信号Ｈ_out に同期して遂行される。メモリの記入動作は各メモリブロックのラインメモリＬＭ０から始められ、またメモリの読出動作は各メモリブロックのラインメモリＬＭ２から始められる。そして、各メモリブロッックで記入／読出動作が行われるラインメモリは循環的に(in rotation) 選択される。
【００５４】
尚、記入動作中のラインメモリの読出動作が要求される場合には、すぐ直前に読出動作が完了したラインメモリの読出動作がもう一度遂行されるようにする。これによって、同一のメモリで同時に記入動作と読出動作が行われることがないようにされる。
【００５５】
図５は、ホストからＶＧＡモードの信号がＸＧＡモードを支援する本実施形態のＬＣＤに提供される場合の、メモリブロック内で記入動作及び読出動作が遂行されるラインメモリを順序通りに時間の経過に沿って示している。
【００５６】
図５を参照すると、５ラインのＶＧＡモードのカラー信号は８ラインのＸＧＡモードのカラー信号に変換される。信号変換が始まると、ラインメモリＬＭ０では記入動作が、そしてラインメモリＬＭ２では読出動作がそれぞれ遂行される。
【００５７】
ラインメモリＬＭ２の読出動作の後にはラインメモリＬＭ０の読出動作が遂行されなければならないが、図５に示されたように、ラインメモリＬＭ２の読出動作が完了される時点ｔ１で、ラインメモリＬＭ０は記入動作の遂行中に置かれている。従って、ラインメモリＬＭ２の読出動作が完了した後に上記ラインメモリＬＭ２の読出動作がもう一度繰り返される。
【００５８】
次に、２つ目のラインメモリＬＭ２の読出動作が完了した時点ｔ２では、ラインメモリＬＭ１が記入動作の遂行中に置かれている。従って、ラインメモリＬＭ２の２つ目の読出動作が完了すると、３つ目の読出動作はラインメモリＬＭ０で遂行される。
【００５９】
次に、ラインメモリＬＭ０での３つ目の読出動作の後にはラインメモリＬＭ１の読出動作が遂行されるはずであるが、４つ目のメモリの読出動作が始められる時点ｔ３でも、ラインメモリＬＭ１の記入動作が持続される。従って３つ目の読出動作が完了した後に、前記ラインメモリＬＭ０の読出動作がもう一度繰り返されることとなる。
【００６０】
この後も、以上で説明されたように、記入動作及び読出動作が一つのラインメモリで同時に発生することのないように動作が遂行される。これによって、ｔ４の時点では、５番目のメモリの記入動作が完了し、同時に８番目のメモリの読出動作が完了する。以上の動作により、５ラインに該当するカラー信号が各メモリブロックに入力される間に、該当メモリブロックから８ラインに該当するカラー信号が出力される。このことはメモリブロックの入力信号についての出力信号の比が１．６であることを意味する。結局、メモリブロックの入力信号ＶであるＧＡモードの信号がＸＧＡモードの信号に変換されたことになる。
【００６１】
図６では、ＳＶＧＡモードの信号が本実施形態の液晶表示装置に提供される場合の、各メモリブロックで、記入動作が遂行されるラインメモリ及び読出動作が遂行されるラインメモリのそれぞれを、順序通りに時系列に沿って示している。
【００６２】
図６を参照すると、４ラインに該当するカラー信号が各メモリブロックから入力される間に、上で説明したメモリの記入／読出方法に従って、該当メモリブロックからは５ラインに該当するカラー信号が出力される。これによって、４ラインのＳＶＧＡモードのカラー信号は５ラインのＸＧＡモードのカラー信号に変換される。
【００６３】
図７は水平出力発生回路３００の実施形態を示している。図７を参照すると、水平出力発生回路３００は、ダウンカウンター(down counter)３０１と、２つの比較器３０２、３０３、そしてＪＫフリップ・フロップ３０４とを含んでいる。
【００６４】
ダウンカウンター３０１は、マイクロコンピューター１００から提供される１１ビットの第１のデータ信号ＴＡ＜１０：０＞を垂直同期信号Ｖ_syncによってロード(load)し、読出ドットクロックＲ Ｄｃｌｋのライジングエッジ(rising edge) の時点でそのつど、ロードされた値をダウンカウントする。
【００６５】
上記ダウンカウンター３０１は自分の出力値が‘０’になると自らにマイクロコンピューター１００からの第１のデータ信号ＴＡ＜１０：０＞をロードする。また、比較器３０２は第１のデータ信号ＴＡ＜１０：０＞とダウンカウンター３０１の出力が同一である場合にハイレベルの信号を出力する。この場合、ＪＫフリップ・フロップ３０４の副出力端子バーＱからは、図８に示されるように、ローレベルの信号が出力される。
【００６６】
比較器３０３は、ダウンカウンター３０１の下位３ビット (３ low order bits)の出力がマイクロコンピューター１００から提供される第２のデータ信号ＰＷ＜２：０＞と同一である場合にハイレベルの信号を出力する。この場合には、図８に示されるように、ＪＫフリップ・フロップ３０４の出力がハイレベルに反転される。
【００６７】
以後、ダウンカウンター３０１の下位３ビットの出力が第２のデータ信号ＰＷ＜２：０＞と同一となる度に、比較器３０３からハイレベルの信号が反復的に出力される。しかし、比較器３０２は第１のデータ信号ＴＡ＜１０：０＞がダウンカウンター３０１にロードされる場合のみにハイレベルの信号を出力するので、図８に示されたように、ＪＫフリップ・フロップ３０４の出力はローレベルに維持される。
【００６８】
図９は図２に示されたフラグ回路５００の実施形態を示している。図９を参照すると、記入動作のためのフラグＦａ、Ｆｂ、Ｆｃを発生する記入フラグ発生回路５１０と読出動作のためのフラグらＦｄ、Ｆｅ、Ｆｆを発生する読出フラグ発生回路５２０は同一構成を有する。すなわち、フラグ発生回路ら５１０、５２０のそれぞれは、アンドゲートと三つのＤフリップ・フロップから構成されるローテート・シフト・レジスター(rotatc shifter register) とを含む。
【００６９】
この場合、単に記入フラグ発生回路５１０のアンドゲート５１１の１つの入力端子に水平同期信号Ｈ_inが提供され、読出フラグ発生回路５２０のアンドゲート５２１の１つの入力端子に水平出力信号Ｈ_out が提供される。
【００７０】
各フラグ発生回路５１０、５２０には、アクティブハイ(active high) のイネーブル信号(Enable)とアクティブロー(active low)のリセット信号Reset がマイクロコンピューター１００からそれぞれ入力される。フリップ・フロップ５１２と５２２とのセット端子と、それ以外のフリップ・フロップ５１３、５１４、５２３、５２４のリセット端子には前記リセット信号Reset がそれぞれ提供される。
【００７１】
従って、上記リセット信号Reset がローレベルである場合には、フリップ・フロップ５１２及び５２２はそれぞれセット状態になり、それ以外のフリップ・フロップ５１３、５１４、５２３、５２４はそれぞれリセット状態になる。このとき、フラグＦａとＦｆとはハイレベルになり、それ以外のフラグＦｂ、Ｆｃ、Ｆｄ、及びＦｅはローレベルになる。
【００７２】
イネーブル信号(Enable)がハイレベルであって且つ上記リセット信号Reset がハイレベルである場合、水平同期信号Ｈ_in及び水平出力信号Ｈ_out のリーディングエッジでのフラグ発生回路５１０、５２０の出力がそれぞれローテートシフトされる。これによって、各メモリブロックでは、水平同期信号Ｈ_in及び水平出力信号Ｈ_out にそれぞれ同期しながら、記入用のラインメモリと読出用のラインメモリが循環的にそれぞれ指定される。
【００７３】
図１０は図２に示されたようにメモリ選択制御回路６００の実施形態を示している。図１０を参照すると、メモリ選択制御回路６００は、選択誤謬監視部(selection error supervisor)６１０と、循環誤謬監視部(cyclic error supervisor) ６２０及び、制御信号出力部６３０とを含む。
【００７４】
選択誤謬の監視部６１０は、水平出力信号Ｈ_out を反転させるインバーター６１１と、このインバーター６１１の出力に同期して読出フラグＦｆ、Ｆｄ、Ｆｅを受け入れこれらをそれぞれラッチするＤフリップ・フロップ６１２、６１３、６１４と、上記読出フラグＦｆ、Ｆｄ、Ｆｅと記入フラグＦａ、Ｆｂ、Ｆｃが同一であるかどうかを比較するアンドゲート６１５、６１６、６１７とノアゲート６１８とから構成される。
【００７５】
図１０に示されたように、記入フラグＦｃとＦｂは記入メモリ選択信号Ｗ Ｓｅｌ０及Ｗ Ｓｅｌ１として、そして読出フラグ信号ＦｆとＦｅは読出メモリの選択信号Ｒ Ｓｅｌ０及びＲ Ｓｅｌ１としてそれぞれ使用される。
【００７６】
この監視部６１０から出力される記入メモリ選択信号Ｗ Ｓｅｌ０、Ｗ Ｓｅｌ１と読出メモリ選択信号Ｒ Ｓｅｌ０、Ｒ Ｓｅｌ１はメモリ管理回路７００と出力選択回路４２０にそれぞれ提供される。
【００７７】
次の【表３】及び【表４】は、記入メモリ選択信号Ｗ Ｓｅｌ０、Ｗ Ｓｅｌ１と読出メモリ選択信号Ｒ Ｓｅｌ０、Ｒ Ｓｅｌ１の論理レベルに従って、各メモリブロックで、記入用のメモリ及び読出用メモリとしてそれぞれ選択されるラインメモリを示している。
【００７８】
【表３】

【００７９】
【表４】

【００８０】
一方、選択誤謬監視部６１０は、現在記入動作中であるラインメモリを監視し、また上記メモリの記入動作の完了の前にそのメモリが次の読出動作のために選択されるかどうかを予測し、そして次の読出動作のために前記メモリが選択されると判断されると読出フラグ発生回路５２０をディスエーブルさせるための読出フラグの制御信号ＲＦＣ１を発生する。
【００８１】
図１１を参照すると明らかなように、記入用のラインメモリは水平同期信号Ｈ_inのライジングエッジにより選択され、次の読出動作用のラインメモリは水平出力信号Ｈ_out のフォーリングエッジにより選択される。
【００８２】
例えば、時間区間ｔ１＜ｔ＜ｔ４の間の記入動作のためのラインメモリは時点ｔ１で決められ、時間区間ｔ３＜ｔ＜ｔ５の間の読出動作のためのラインメモリは時点ｔ２で決められる。
【００８３】
ｔ２の時点で、次の読出動作のためのラインメモリが現在記入動作の遂行されるラインメモリと一致する場合、選択誤謬監視部６１０はローレベルの読出フラグの制御信号ＲＦＣ１を発生する。これによって読出フラグ発生回路５２０がディスエーブルされその出力がローテートシフトされない。その結果、現在読出動作が遂行中であるラインメモリが次の読出動作のためにもう一度使用される。
【００８４】
一方、ｔ２の時点で、次の読出動作のためのラインメモリが現在記入動作の遂行されるラインメモリと一致しない場合、選択誤謬監視部６１０はハイレベルの読出フラグの制御信号ＲＦＣ１を発生する。これによって、読出フラグ発生回路５２０がイネーブルされ、前記回路５２０の出力がローテートシフトされる。その結果、現在読出動作が遂行中であるラインメモリの次の順序のラインメモリが次回の読出動作の際に使用される。
【００８５】
図１０に示されたように、循環誤謬監視部６２０は、Ｄフリップ・フロップ６２１、６２２、６２３からなるカウンター回路と、アンドゲート６２４とオフゲート６２５、６２６からなるカウンティング範囲の制御回路(couting range control circuit) と、アンドゲート６２７からなるリセット回路と、ノアゲート６２８からなる読出フラグ制御回路とから構成される。
【００８６】
カウンティング範囲制御回路６２４、６２５、及び６２６はマイクロコンピューター１００から提供される第１のモード表示信号ＭＤ１に応答してカウンター回路６２１、６２２、及び６２３の出力範囲を制御する。
【００８７】
リセット回路６２７にはマイクロコンピューター１００からのリセット信号Reset と第２のモード表示信号ＭＤ２とを入力して、ＸＧＡモード信号がこのＬＣＤに入力される際に上記カウンター回路６２１、６２２、６２３をリセットする。また、読出フラグ制御回路６２８は読出フラグ発生回路５２０をイネーブルさせるための読出フラグ制御信号ＲＦＣ２を発生する。
【００８８】
この実施形態のＬＣＤにＶＧＡモード信号が入力される場合に、上記カウンター回路６２１、６２２、６２３の出力が‘５’となったときに、前記読出フラグイネーブル制御回路６２８は読出フラグ発生回路５２０をイネーブルさせるための読出フラグ制御信号ＲＦＣ２を発生する。そしてＳＶＧＡモードの信号が入力される場合には、前記カウンター回路６２１、６２２、６２３の出力が‘８’となったときに、前記読出フラグのイネーブル制御回路６２８は、読出フラグの発生回路５２０をイネーブルさせるための読出フラグ制御信号ＲＦＣ２を発生する。
【００８９】
このように、循環誤謬監視部６２０は、ＶＧＡモード信号が入力される場合には上記カウンター回路６２１、６２２、６２３の出力が‘５’となる度に強制的に読出フラグ発生回路５２０をイネーブルさせる。また、ＳＶＧＡモード信号が入力される場合には、循環誤謬監視部６２０は前記カウンター回路６２１、６２２、６２３の出力が‘８’となる度に、強制的に読出フラグ発生回路５２０をイネーブルさせる。その理由は、そのタイミング毎に水平同期信号Ｈ_inと水平出力信号Ｈ_out が一致するようになるため、そのときに装置が誤作動する可能性が高いからである。
【００９０】
制御信号出力部６３０は、選択誤謬の監視部６１０の出力と循環誤謬監視部６２０の出力をそれぞれ受け入れる２つの入力端子と読出フラグ発生回路５２０のイネーブル端子に接続される出力端子を有するオアゲート６３１からなる。前記制御信号出力部６３０の出力信号がローレベルである際には読出フラグ発生回路５２０がディスエーブルされる。従って、この場合には水平出力信号Ｈ_out が入力されても読出フラグ発生回路５２０の出力らローテートシフトがなされない。
【００９１】
一方、上記制御信号の出力部６３０の出力信号がハイレベルである場合には読出フラグ発生回路５２０がイネーブルされる。従って、この場合は水平出力信号Ｈ_out が入力されるときに、読出フラグ発生回路５２０の出力のローテートシフトがなされる。
【００９２】
図１１は図３に示されたメモリ管理回路７００の１つの実施形態を示している。図１１を参照すると明らかなように、記入／読出の制御部７１０はインバーター７１１、７１２、７１４、及び７１６とアンドゲート７１３、７１５、及び７１７とから構成される。
【００９３】
【表３】に示されたように、各メモリブロックで、まず、Ｗ Ｓｅｌ０＝‘Ｌ’、Ｗ Ｓｅｌ１＝‘Ｌ’であると、ラインメモリＬＭ０が記入イネーブル状態になってそれ以外のラインメモリらＬＭ１、ＬＭ２は読出イネーブル状態になる。次いで、Ｗ Ｓｅｌ０＝‘Ｌ’、Ｗ Ｓｅｌ０＝‘Ｈ’であると、ラインメモリＬＭ１が記入イネーブル状態になってそれ以外のラインメモリＬＭ０、ＬＭ２は読出イネーブル状態になる。最後に、Ｗ Ｓｅｌ０＝‘Ｈ’、Ｗ Ｓｅｌ０＝‘Ｌ’であると、ラインメモリＬＭ２が記入イネーブル状態になってそれ以外のラインメモリＬＭ０、ＬＭ１は読出イネーブル状態になる。
【００９４】
アドレス発生部７２０は水平同期信号Ｈ_inによって初期化され、且つ記入ドットクロックＷ Ｄｃｌｋに同期して記入動作用のアドレスＷ Ａｄｄを発生する記入アドレス発生部７２１と、水平出力信号Ｈ_out によって初期化され、且つ読出ドットクロックＲ Ｄｃｌｋに同期して読出動作用のアドレスＲ Ａｄｄを発生する読出アドレス発生部７２２からなる。前記記入アドレス発生部７２１と読出アドレス発生部７２２はアップカウンターからそれぞれ構成される。
【００９５】
アドレス選択部７３０は３つの２×１のマルチプレクサー７３１、７３２、７３３から構成される。各マルチプレクサーの２つの入力端子には記入アドレスＷ Ａｄｄ及び読出アドレス、Ｒ Ａｄｄがそれぞれ提供される。そして、前記マルチプレクサー７３１、７３２、及び７３３の出力は各メモリブロックのラインメモリＬＭ０、ＬＭ１、ＬＭ２にそれぞれ提供される。前記マルチプレクサー７３１、７３２、７３３の選択制御端子には記入／読出制御部７１０内のアンドゲート７１３、７１５、及び７１７の出力がそれぞれ提供される。記入及び読出アドレスＷ Ａｄｄ、Ｒ Ａｄｄは記入／読出制御部７１０によって選択され各メモリブロックのラインメモリＬＭ０、ＬＭ１、ＬＭ２のいずれかにそれぞれ提供される。
【００９６】
ドットクロック選択部７４０も３つの２×１マルチプレクサー７４１、７４２、及び７４３から構成される。各マルチプレクサーの２つの入力端子には記入及び読出ドットクロックＷ Ｄｃｌｋ、Ｒ Ｄｃｌｋがそれぞれ提供される。
【００９７】
上記マルチプレクサー７４１、７４２、７４３の出力は各メモリブロックのラインメモリＬＭ０、ＬＭ１、ＬＭ２にそれぞれ提供される。前記マルチプレクサー７４１、７４２、及び７４３の選択制御端子には記入／読出の制御部７１０内のアンドゲート７１３、７１５、７１７の出力がれぞれ提供される。記入及び読出ドットクロックＷ Ｄｃｌｋ、Ｒ Ｄｃｌｋは記入／読出制御部７１０によって選択的に各メモリブロックのラインメモリＬＭ０、ＬＭ１、ＬＭ２にそれぞれ提供される。
【００９８】
以上では、入力信号が８ビットのカラー信号の場合を例として用いて本発明を説明した。但し、本発明は必ずしもこれに制限されるものではない。つまり、この技術分野の通常の知識を有している者であれば、１６ビット又はそれ以上のカラー信号の場合についても本発明をそのまま適用できることは自明である。そして、そのような範囲における本発明の変更は、全て本発明の技術範囲に属するということをよく理解すべきである。
【００９９】
【発明の効果】
本発明の液晶表示装置は上記のように構成されているので、ＬＣＤが支援するモードの解像度より相対的に低い解像度のモード信号がＬＣＤに入力されたとしてもＬＣＤ画面の全体に映像が表示できる。
【図面の簡単な説明】
【図１】ＶＧＡモード信号がＸＧＡモードの液晶表示装置に提供される場合における、本発明による映像表示領域を示している図。
【図２】本発明による液晶表示制御装置の回路構成を示しているブロック図。
【図３】図２に示されたメモリブロックの周辺の回路構成を示しているブロック図。
【図４】図２に示された出力選択回路の実施形態を示しているブロック図。
【図５】ＶＧＡモード信号が本発明の液晶表示装置に提供される際に、各メモリブロック内で、記入動作が遂行されるラインメモリ及び読出動作が遂行されるラインメモリをそれぞれ順序通り時系列に沿って示している図。
【図６】ＳＶＧＡモード信号が本発明の液晶表示装置に提供される際に、各メモリブロック内で、記入動作が遂行されるラインメモリ及び読出動作が遂行されるラインメモリをそれぞれ順序通り時系列に沿って示している図。
【図７】図２に示された水平出力発生回路の実施形態を示している回路図。
【図８】垂直同期信号と水平出力信号のタイミング図。
【図９】図２に示されたフラグ回路の実施形態を示している回路図。
【図１０】図２に示されたメモリ選択制御回路の実施形態を示している回路図。
【図１１】記入動作に従って読出動作用のラインメモリが選択される課程を説明するためのタイミング図。
【図１２】図３に示されたメモリ管理回路の好ましい実施形態を示している回路図。
【図１３】アクティブマトリックス液晶表示装置の構成を概略的に示しているブロック図。
【図１４】従来の液晶表示装置の回路構成を示しているブロック図、
【図１５】ＶＧＡモード信号がＸＧＡモードの液晶表示装置に提供される場合の、従来の技術による映像表示領域を示している図。
【符号の説明】
１００ マイクロコンピューター
２００ ドットクロック発生回路
３００ 水平出力発生回路
４００ メモリ
５００ フラグ回路
６００ メモリ選択制御回路
７００ メモリ管理回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display (LCD), and more specifically to an LCD (LIQUID CRYSTAL DISPLAY WITH DISPLAY MODE CONVERSION FUNCTION) having a display mode conversion function.
[0002]
[Prior art]
As shown in FIG. 13, an active matrix liquid crystal display device in which each pixel is individually blinked (ON / OFF) by a switching element corresponding to each pixel (pixcl) is provided with an LCD controller 20 and an LCD panel 30. Including.
[0003]
The LCD panel 30 includes an LCD driving device 40. The LCD controller 20 converts an analog color signal provided from the host 10 such as a personal computer into a digital color signal, and outputs a horizontal output signal H._outAnd a dot clock signal Dclk. The digital color signal, the dot clock signal and the horizontal output signal respectively output from the LCD control device 20 are provided to an LCD drive circuit 40 mounted in the LCD panel 30.
[0004]
As apparent from FIG. 14, the conventional LCD control device 20 uses the horizontal synchronizing signal H._sync(horizontal synchronous signal) is input and the horizontal output signal H_outAnd a PLL circuit 21 that generates a dot clock signal Dclk, and an analog R (red), G (green), and B (blue) signal provided from the host are converted into digital R, G, and B signals, respectively, and the LCD. The ADC circuit 22 is provided to the drive circuit 40 of FIG. And the horizontal output signal H_outIs the horizontal synchronization signal H_syncThe frequency of the horizontal sync signal H_syncIs identical to that of
[0005]
The horizontal synchronizing signal H input to the PLL circuit 21 depending on the characteristics of the host._syncHowever, the PLL circuit 21 may use a horizontal output signal H having a predetermined polarity._outIs output.
[0006]
For example, a negative polarity horizontal output signal H_outIn the LCD having the drive circuit 40 that operates in synchronization with the horizontal synchronization signal H of positive polarity from the host to the PLL circuit 21._syncIs provided, the PLL circuit 21 does not output the horizontal output signal H having a negative polarity._outIs provided to the LCD drive circuit 40. As is well known, the PLL circuit 21 includes a phase detector, a VCO (Voltage Controlled Oscillator), a divider, and an output generator.
[0007]
In general, the LCD supports a single display mode. For example, only one of VGA (Video Graphics Array), SVGA (Super VGA), or XGA (Extended Graphics Array) mode is supported.
[0008]
Therefore, for example, when a signal for a VGA mode with a total resolution of 800 × 449 is provided to an LCD that supports an XGA mode with a total resolution of 1344 × 806, as shown in FIG. The video is displayed only in a part of the area A on the screen, and the video is not displayed in the other area B. The same applies when an SVGA mode signal with a total resolution of 1056 × 628 is provided to an XGA LCD.
[0009]
Thus, conventionally, when a low-resolution display mode signal is provided from a host that supports a low-resolution display mode, and when the LCD supports a high-resolution display mode, the video is displayed. There is a problem in that it is displayed only on a part of the LCD screen.
[0010]
[Problems to be solved by the invention]
Accordingly, an object of the present invention is to provide an LCD capable of displaying an image on the entire LCD screen even when a display mode signal having a resolution lower than that of the LCD display mode is input from a host.
[0011]
Another object of the present invention is to provide an LCD controller having a function of converting a low-resolution display mode signal from a host into a high-resolution display mode signal supported by the LCD.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, in the liquid crystal display device of the present invention, a horizontal synchronization signal and a vertical synchronization signal are input from the host, the support display mode of the host is discriminated from the input signal, and the frequency corresponding to the support display mode LCD control means for outputting a horizontal output signal and a dot clock signal and converting an analog color signal provided from the host into a digital color signal suitable for the display mode of the corresponding LCD panel, the horizontal output signal and the dot clock LCD driving means for inputting the signal to drive the LCD panel. With this configuration, the host support display mode signal is converted into a signal corresponding to the display mode of the LCD panel.
[0013]
The LCD control means of this apparatus receives the horizontal synchronizing signal and the vertical synchronizing signal, determines the host support display mode from the input, and follows the waveform of the horizontal output signal of the mode corresponding to the host support display mode. Display mode discriminating means for outputting a data signal, memory means for storing the digital color signal, input dot clock signal for inputting operation of the memory means by inputting a horizontal synchronizing signal, and reading of the memory means A dot clock generating means for generating a read dot clock signal for operation; a horizontal signal for inputting the data signal in response to the vertical synchronization signal and generating the horizontal output signal in synchronization with the read dot clock signal; An output generating means, and the horizontal synchronizing signal and the entry dot clock signal are inputted, and the entry operation of the memory means Controls, and the enter the horizontal output signal and said read dot clock signal and a memory control means for controlling the read operation of said memory means.
[0014]
The memory means of this apparatus selectively outputs the first to third memory blocks for storing the digital color signals and the color signals controlled by the memory control means and written in the memory blocks. Output selection means.
[0015]
Each memory block of the device includes at least three line memories.
[0016]
The memory control means of this device includes a flag means for generating a plurality of flags for designating a line memory for performing an entry operation and a read operation in a predetermined order among a number of line memories of each memory block; In response to the plurality of flags provided from the flag means, each of the line memories for which the entry operation and the read operation are performed while one line memory is not simultaneously selected for the entry operation and the read operation. Memory selection control means for generating first and second memory selection signals for selection, and the horizontal synchronization signal, the horizontal output signal, the entry dot clock signal, and the read dot clock signal are input, and the memory selection Memory manager for managing memory access for entry and read operations of the memory means while being controlled by the control means Including the door.
[0017]
The memory selection control means of this apparatus determines whether or not the line memory is selected for the next read operation before the completion of the write operation of the line memory that is currently being written according to the information provided from the flag means. And a selection error monitoring means for generating a read flag control signal for disabling the read flag generating means when it is determined that the line memory is selected for the next read operation. .
[0018]
The memory selection control means of this apparatus further comprises a circulation error monitoring means for generating a read flag control signal to enable the read flag generating means when the timing of the horizontal synchronizing signal and the horizontal output signal coincide with each other. Control signal output means for selectively providing any one of the control signals for the read flag to the read flag generating means.
[0019]
The memory management means of this apparatus includes an entry / read control means for controlling the entry and read operations of the line memory in each memory block in response to a first memory selection signal provided from the memory selection control means, and the horizontal Address generating means for receiving a synchronizing signal, the horizontal output signal, the dot clock signal for writing and reading, and the reading dot clock signal and generating a writing address and a reading address for a memory reading operation and a memory writing operation; Address selecting means controlled by the writing / reading control means for selecting the writing address and reading address and providing them to the line memories in the memory blocks, respectively, and the writing and reading dots controlled by the writing / reading control means Each clock signal is selected to select a line in each memory block. And a dot clock selection means for providing respective memory.
[0020]
The LCD panel of this apparatus supports the XGA mode, and provides an XGA mode signal to the LCD driving means even when a VGA mode signal is input to the LCD control means.
[0021]
Also, the LCD panel of this apparatus supports the XGA mode, and provides the XGA mode signal to the LCD drive means even if the SVGA mode signal is input to the LCD control means.
[0022]
Further, when color, horizontal and vertical synchronization signals for the low resolution mode are provided to the XGA mode LCD, the frequency of the dot clock signal and the frequency of the horizontal synchronization signal are increased. As a result, the video display area of the screen is expanded in the horizontal and vertical directions, and the video is displayed on the entire LCD screen.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of an LCD control device according to the present invention will be described in detail with reference to the accompanying drawings.
[0024]
First, when a VGA mode signal is input to the LCD controller of the present invention, the vertical synchronization signal V_syncThe horizontal sync signal H with the same frequency_syncAnd the frequency of the dot clock signal Dclk are increased by a factor of 0.6 as shown in Table 1. Thereby, even if the input signal is in the VGA mode, the image on the LCD screen can be displayed with almost the resolution of the XGA mode.
[0025]
[Table 1]

[0026]
The resolution in Table 1 indicates the active resolution, and the value in () indicates the total resolution.
[0027]
As shown in Table 1, for example, the resolution of 640 × 480 is converted to the resolution of 1024 × 768, so the resolution before conversion: resolution after conversion = 1: 1.6. According to this conversion method, color R, G, B signals for five lines from the host are converted into color R, G, B signals for eight lines.
[0028]
Next, when the SVGA mode signal is input to the LCD controller of this embodiment, the vertical synchronization signal V_syncThe frequency of the horizontal sync signal H remains the same._syncFrequency and
The frequency of the dot clock signal Dclk is increased about 0.25 times as shown in Table 2 below. As a result, even if the input signal is an SVGA mode signal, the video on the LCD screen can be displayed with almost the resolution of the XGA mode. This is shown in FIG.
[0029]
[Table 2]

[0030]
The resolution in [Table 2] indicates the normal resolution, and the value in () indicates the total resolution.
[0031]
As shown in Table 2, for example, since the resolution of 800 × 600 is converted to the resolution of 1000 × 750, the resolution before conversion: resolution after conversion = 1: 1.28. However, in this case, for the convenience of conversion, the resolution before conversion: resolution after conversion = 1: 1.25. According to this conversion method, color signals for four lines from the host are converted into color signals for five lines. In other words, in the present invention, the resolution of the input signal is increased by conversion so that a full screen image of the LCD can be displayed even when a low-resolution signal is input. This is achieved by increasing the number of analog input signals.
[0032]
FIG. 2 shows a circuit configuration of the LCD control device of the present invention for converting a VGA or SVGA mode signal into an XGA mode signal.
[0033]
Referring to FIG. 2, the horizontal synchronization signal H output from the host._syncAnd vertical sync signal V_syncIs input to the microcomputer 100. The microcomputer 100 uses a horizontal synchronization signal H_syncAnd vertical sync signal V_syncA display mode supported by the host (hereinafter referred to as “host support display mode”) is determined, and first and second mode display signals MD1 and MD2 indicating the result are generated.
[0034]
When the host support display mode is the SVGA mode, the microcomputer 100 outputs the high-level first mode display signal MD1 and the high-level second mode display signal MD2, and the host support display mode is the VGA mode. The low-level first mode display signal MD1 and the high-level second mode display signal MD2 are output. In addition, when the host support display mode is the XGA mode, the microcomputer 100 outputs a low-level second mode display signal MD2. Based on the change in the output signal, the host support display mode is determined, and the rate of dot clock signal increase to be performed later is made appropriate.
[0035]
Further, the microcomputer 100 outputs a horizontal output signal H which is a horizontal synchronization signal for the XGA mode._outA first data signal TA indicating the number of dots per cycle and the horizontal output signal H_outA second data signal PW indicating the pulse width is provided.
[0036]
The dot clock generation circuit 200 includes two PLL circuits 210 and 220. The PLL circuits 210 and 220 are input dot clock signals (W for a memory write operation and a read operation). Dclk) and readout dot clock signal (R Dclk) respectively.
[0037]
The horizontal output generation circuit 300 generates a vertical synchronization signal V provided from the host._syncAnd a horizontal output signal H based on the first and second data signals TA and PW provided from the microcomputer 100._outIs generated. At this time, the horizontal output signal H_outIs the horizontal sync signal (H_sync: ‘H’_inIt is generated in synchronization with ').
[0038]
As shown in FIG. 2, the apparatus of the present invention includes a memory 400 including three memory blocks 410a, 410b, 410c and an output selection unit 420 corresponding to R, G, and B signals, respectively. Each of the memory blocks 410a, 410b, and 410c includes at least three line memories. The reason why the number of line memories is three or more is that a memory for performing an entry operation at a certain moment, a memory for performing a read operation, and a memory on standby are necessary to increase the output signal. This point will be discussed in detail later.
[0039]
Horizontal sync signal H_inThe outputs of the dot clock generation circuit 200 and the horizontal output generation circuit 300 are provided to a memory control circuit including a memory management circuit 500, a memory selection control circuit 600, and a flag circuit 700. The horizontal synchronizing signal H is sent to the memory control circuits 500, 600, 700._inAnd dot clock signal W Dclk is input to control the writing operation of the memory 400. Also, the horizontal output signal H_outAnd read dot clock signal R Dclk is input to the memory control circuits 500, 600, and 700, whereby the read operation of the memory 400 is controlled.
[0040]
The flag circuit 500 provides a flag signal for designating a line memory in which a writing operation and a reading operation are performed in a predetermined order in each memory block.
[0041]
The memory selection control circuit 600 prevents the line operation and the read operation from being performed at the same time in any line memory of each memory block, and selects the line memory for performing the write operation and the read operation. Sel, R Provide Sel.
[0042]
The memory management circuit 700 receives instructions from the memory selection control circuit 600 and manages memory access as entry / read operations in the line memory in each memory block.
[0043]
Next, embodiments of the LCD control device according to the present invention will be described in more detail with reference to the accompanying drawings.
[0044]
As shown in FIG. 2, the memory 400 includes an output selection circuit 420 including three memory blocks 410a, 410b, and 410c and three 3 × 1 multiplexers 420a, 420b, and 420c corresponding to the memory blocks 410a, 410b, and 410c, respectively. ing.
[0045]
FIG. 3 shows a detailed configuration of the memory blocks 410a, 410b, and 410c, the multiplexers 420a, 420b, and 420c, and the memory management circuit 700 shown in FIG. The other two memory blocks not shown in FIG. 3 are also connected to the memory management circuit 700 in the same manner as the memory blocks shown in the drawing.
[0046]
As is apparent from FIG. 3, each of the memory blocks 410a, 410b, and 410c includes three line memories LM0, LM1, and LM2. Each line memory has a storage capacity of at least 1344 words × 8 bits.
[0047]
Next, FIG. 4 shows an embodiment of the output selection circuit 420 shown in FIG. As is apparent with reference to FIG. 4, the three input terminals of each of the three 3 × 1 multiplexers 420a, 420b, and 420c are connected to the data output ports of the line memories LM0, LM1, and LM2 in each memory block ( (Not shown).
[0048]
Each multiplexer has a read memory selection signal R provided from the memory selection control circuit 600. Sel0, R In response to Sel1, one of the data input from the line memories LM0, LM1, and LM2 of each memory block is selected and output. The output R of the multiplexers 420a, 420b, 420c_out, G_out, B_outIs provided to the LCD drive circuit.
[0049]
Reference is again made to FIG. The memory management circuit 700 includes an entry / read control unit 710, an address generation unit 720, an address selection unit 730, and a dot clock selection unit 740. The entry / read control unit 710 is an entry memory selection signal W provided from the memory selection control circuit 600. In response to Sel, the writing and reading operations performed in the line memory of each memory block are controlled.
[0050]
The address generator 720 generates a horizontal synchronization signal H_inAnd horizontal output signal H_outIn response to the write address W for the memory read operation and the memory write operation Add and read address R Add is generated. The address selection unit 730 is controlled by the entry / read control unit 710, and the entry address W Add and read address R Add is selected and provided to the line memories LM0, LM1, and LM2 of each memory block.
[0051]
The dot clock selection unit 740 is also controlled by the entry / read control unit 710, and the entry dot clock W Dclk and readout dot clock R Dclk is selected and provided to the line memories LM0, LM1, and LM2 of each memory block.
[0052]
When a mode signal having a resolution lower than the resolution of the LCD of this device is provided from the host to the control device, the writing and reading operations of the line memories LM0, LM1, and LM2 of the memory blocks 410a, 410b, and 410c are as follows. To be carried out.
[0053]
In relation to each color signal, the writing operation of the memory is the horizontal synchronization signal H_inThe memory read operation is performed in synchronization with the horizontal output signal H._outIt is performed synchronously. The memory write operation is started from the line memory LM0 of each memory block, and the memory read operation is started from the line memory LM2 of each memory block. Then, the line memory in which the writing / reading operation is performed in each memory block is selected in rotation.
[0054]
When the line memory read operation during the entry operation is required, the line memory read operation for which the read operation has been completed immediately before is performed once again. As a result, the writing operation and the reading operation are not performed simultaneously in the same memory.
[0055]
FIG. 5 is a diagram illustrating the passage of time in order in a line memory in which a write operation and a read operation are performed in a memory block when a VGA mode signal is provided from the host to the LCD of the present embodiment supporting the XGA mode. It shows along.
[0056]
Referring to FIG. 5, a 5-line VGA mode color signal is converted into an 8-line XGA mode color signal. When the signal conversion starts, a write operation is performed in the line memory LM0, and a read operation is performed in the line memory LM2.
[0057]
The read operation of the line memory LM0 must be performed after the read operation of the line memory LM2, but as shown in FIG. 5, at the time t1 when the read operation of the line memory LM2 is completed, the line memory LM0 It is placed while performing the filling operation. Therefore, after the read operation of the line memory LM2 is completed, the read operation of the line memory LM2 is repeated once more.
[0058]
Next, at the time t2 when the reading operation of the second line memory LM2 is completed, the line memory LM1 is placed during the execution of the writing operation. Accordingly, when the second read operation of the line memory LM2 is completed, the third read operation is performed in the line memory LM0.
[0059]
Next, after the third read operation in the line memory LM0, the read operation of the line memory LM1 should be performed, but even at the time t3 when the read operation of the fourth memory is started, the line memory LM1. The entry operation is continued. Therefore, after the third read operation is completed, the read operation of the line memory LM0 is repeated once more.
[0060]
Thereafter, as described above, the operation is performed so that the writing operation and the reading operation do not occur simultaneously in one line memory. As a result, at the time t4, the fifth memory entry operation is completed, and at the same time, the eighth memory read operation is completed. With the above operation, while a color signal corresponding to 5 lines is input to each memory block, a color signal corresponding to 8 lines is output from the corresponding memory block. This means that the ratio of the output signal to the input signal of the memory block is 1.6. Eventually, the GA mode signal, which is the input signal V of the memory block, is converted into an XGA mode signal.
[0061]
In FIG. 6, when the SVGA mode signal is provided to the liquid crystal display device of the present embodiment, the line memory in which the writing operation is performed and the line memory in which the reading operation is performed in each memory block are shown in order. Shown along the street in time series.
[0062]
Referring to FIG. 6, while a color signal corresponding to 4 lines is input from each memory block, a color signal corresponding to 5 lines is output from the corresponding memory block according to the memory writing / reading method described above. Is done. As a result, the 4-line SVGA mode color signal is converted into a 5-line XGA mode color signal.
[0063]
FIG. 7 shows an embodiment of the horizontal output generation circuit 300. Referring to FIG. 7, the horizontal output generation circuit 300 includes a down counter 301, two comparators 302 and 303, and a JK flip-flop 304.
[0064]
The down counter 301 converts the 11-bit first data signal TA <10: 0> provided from the microcomputer 100 into the vertical synchronization signal V._syncAnd read dot clock R The loaded value is down-counted each time at the rising edge of Dclk.
[0065]
When the output value of the down counter 301 becomes ‘0’, the down counter 301 loads the first data signal TA <10: 0> from the microcomputer 100. The comparator 302 outputs a high level signal when the first data signal TA <10: 0> and the output of the down counter 301 are the same. In this case, a low-level signal is output from the sub output terminal bar Q of the JK flip-flop 304 as shown in FIG.
[0066]
The comparator 303 outputs a high level signal when the output of the 3 low order bits of the down counter 301 is the same as the second data signal PW <2: 0> provided from the microcomputer 100. Output. In this case, as shown in FIG. 8, the output of the JK flip-flop 304 is inverted to a high level.
[0067]
Thereafter, each time the output of the lower 3 bits of the down counter 301 becomes the same as the second data signal PW <2: 0>, a high level signal is repeatedly output from the comparator 303. However, since the comparator 302 outputs a high level signal only when the first data signal TA <10: 0> is loaded into the down counter 301, as shown in FIG. 8, the JK flip-flop is output. The output of 304 is maintained at a low level.
[0068]
FIG. 9 shows an embodiment of the flag circuit 500 shown in FIG. Referring to FIG. 9, an entry flag generation circuit 510 that generates flags Fa, Fb, and Fc for an entry operation and a read flag generation circuit 520 that generates flags Fd, Fe, and Ff for the readout operation have the same configuration. Have. That is, each of the flag generation circuits 510 and 520 includes an AND gate and a rotate shift register composed of three D flip-flops.
[0069]
In this case, the horizontal synchronizing signal H is simply applied to one input terminal of the AND gate 511 of the entry flag generating circuit 510._inThe horizontal output signal H is supplied to one input terminal of the AND gate 521 of the read flag generation circuit 520._outIs provided.
[0070]
An active high enable signal (Enable) and an active low reset signal Reset are input from the microcomputer 100 to the flag generation circuits 510 and 520, respectively. The reset signal Reset is provided to the set terminals of the flip-flops 512 and 522 and the reset terminals of the other flip-flops 513, 514, 523, and 524, respectively.
[0071]
Therefore, when the reset signal Reset is at a low level, the flip-flops 512 and 522 are in the set state, and the other flip-flops 513, 514, 523, and 524 are in the reset state. At this time, the flags Fa and Ff are at a high level, and the other flags Fb, Fc, Fd, and Fe are at a low level.
[0072]
When the enable signal (Enable) is high level and the reset signal Reset is high level, the horizontal synchronization signal H_inAnd horizontal output signal H_outThe outputs of the flag generation circuits 510 and 520 at the leading edge are rotated and shifted, respectively. Thereby, in each memory block, the horizontal synchronization signal H_inAnd horizontal output signal H_outThe line memory for writing and the line memory for reading are respectively designated cyclically while being synchronized with each other.
[0073]
FIG. 10 shows an embodiment of the memory selection control circuit 600 as shown in FIG. Referring to FIG. 10, the memory selection control circuit 600 includes a selection error supervisor 610, a cyclic error supervisor 620, and a control signal output unit 630.
[0074]
The selection error monitoring unit 610 generates a horizontal output signal H_outInverter 611, D flip-flops 612, 613, and 614 that receive and latch read flags Ff, Fd, and Fe in synchronization with the output of inverter 611, and read flags Ff, Fd, and Fe It consists of AND gates 615, 616, 617 and NOR gates 618 that compare whether the entry flags Fa, Fb, Fc are the same.
[0075]
As shown in FIG. 10, the entry flags Fc and Fb are the entry memory selection signals W. Sel0 and W As Sel1, the read flag signals Ff and Fe are read memory selection signals R. Sel0 and R Each is used as Sel1.
[0076]
The entry memory selection signal W output from the monitoring unit 610 Sel0, W Sel1 and read memory selection signal R Sel0, R Sel1 is provided to the memory management circuit 700 and the output selection circuit 420, respectively.
[0077]
The following [Table 3] and [Table 4] are input memory selection signals W Sel0, W Sel1 and read memory selection signal R Sel0, R The line memories selected as the memory for writing and the memory for reading in each memory block according to the logic level of Sel1 are shown.
[0078]
[Table 3]

[0079]
[Table 4]

[0080]
On the other hand, the selection error monitoring unit 610 monitors the line memory that is currently in the write operation, and predicts whether the memory is selected for the next read operation before the completion of the memory write operation. When it is determined that the memory is selected for the next read operation, a read flag control signal RFC1 for disabling the read flag generating circuit 520 is generated.
[0081]
As can be seen from FIG. 11, the line memory for writing has a horizontal synchronizing signal H._inThe line memory for the next read operation is selected by the rising edge of the horizontal output signal H._outSelected by the falling edge.
[0082]
For example, the line memory for the write operation during the time interval t1 <t <t4 is determined at time t1, and the line memory for the read operation during the time interval t3 <t <t5 is determined at time t2.
[0083]
At time t2, if the line memory for the next read operation matches the line memory on which the current write operation is performed, the selection error monitoring unit 610 generates a low level read flag control signal RFC1. As a result, read flag generation circuit 520 is disabled and its output is not rotated. As a result, the line memory where the current read operation is being performed is used again for the next read operation.
[0084]
On the other hand, when the line memory for the next read operation does not coincide with the line memory for which the current write operation is performed at time t2, the selection error monitoring unit 610 generates the high level read flag control signal RFC1. As a result, the read flag generation circuit 520 is enabled and the output of the circuit 520 is rotated and shifted. As a result, the line memory in the next order of the line memories currently being read is used in the next read operation.
[0085]
As shown in FIG. 10, the circulation error monitoring unit 620 includes a counter circuit composed of D flip-flops 621, 622, and 623, and a counting range control circuit composed of an AND gate 624 and off gates 625 and 626. circuit), a reset circuit composed of an AND gate 627, and a read flag control circuit composed of a NOR gate 628.
[0086]
Counting range control circuits 624, 625, and 626 control the output ranges of the counter circuits 621, 622, and 623 in response to the first mode display signal MD1 provided from the microcomputer 100.
[0087]
The reset signal Reset from the microcomputer 100 and the second mode display signal MD2 are input to the reset circuit 627, and when the XGA mode signal is input to the LCD, the counter circuits 621, 622, and 623 are reset. . Read flag control circuit 628 generates read flag control signal RFC2 for enabling read flag generation circuit 520.
[0088]
When a VGA mode signal is input to the LCD of this embodiment, when the outputs of the counter circuits 621, 622, and 623 become '5', the read flag enable control circuit 628 causes the read flag generation circuit 520 to operate. A read flag control signal RFC2 for enabling is generated. When an SVGA mode signal is input, when the outputs of the counter circuits 621, 622, and 623 are '8', the read flag enable control circuit 628 causes the read flag generation circuit 520 to operate. A read flag control signal RFC2 for enabling is generated.
[0089]
As described above, the circulation error monitoring unit 620 forcibly enables the read flag generation circuit 520 whenever the output of the counter circuits 621, 622, and 623 becomes '5' when the VGA mode signal is input. . When the SVGA mode signal is input, the circulation error monitoring unit 620 forcibly enables the read flag generation circuit 520 every time the outputs of the counter circuits 621, 622, and 623 become “8”. The reason is that the horizontal synchronization signal H_inAnd horizontal output signal H_outThis is because there is a high possibility that the device will malfunction at that time.
[0090]
The control signal output unit 630 includes an OR gate 631 having two input terminals for receiving the output of the selection error monitoring unit 610 and the output of the circulation error monitoring unit 620, respectively, and an output terminal connected to the enable terminal of the read flag generation circuit 520. Become. When the output signal of the control signal output unit 630 is at a low level, the read flag generation circuit 520 is disabled. Therefore, in this case, the horizontal output signal H_outIs not rotated by the output of the read flag generation circuit 520.
[0091]
On the other hand, when the output signal of the control signal output unit 630 is at a high level, the read flag generation circuit 520 is enabled. Therefore, in this case, the horizontal output signal H_outIs rotated, the output of read flag generation circuit 520 is rotated.
[0092]
FIG. 11 shows one embodiment of the memory management circuit 700 shown in FIG. As apparent from FIG. 11, the entry / reading control unit 710 includes inverters 711, 712, 714, and 716 and AND gates 713, 715, and 717.
[0093]
As shown in Table 3, in each memory block, first, W Sel0 = ’L’, W When Sel1 = 'L', the line memory LM0 is in the write enable state, and the other line memories LM1, LM2 are in the read enable state. Then W When Sel0 = 'L' and W Sel0 = 'H', the line memory LM1 is in the write enable state, and the other line memories LM0, LM2 are in the read enable state. Finally, W Sel0 = ’H’, W When Sel0 = 'L', the line memory LM2 is in the write enable state, and the other line memories LM0 and LM1 are in the read enable state.
[0094]
The address generator 720 generates a horizontal synchronization signal H_inInitialized and filled in by dot clock W Address W for writing operation in synchronization with Dclk An entry address generator 721 for generating Add, and a horizontal output signal H_outAnd the read dot clock R Address R for read operation in synchronization with Dclk A read address generator 722 for generating Add is included. The entry address generator 721 and the read address generator 722 are each composed of an up counter.
[0095]
The address selection unit 730 includes three 2 × 1 multiplexers 731, 732, and 733. The input address W is at the two input terminals of each multiplexer. Add and read address, R Add is provided for each. The outputs of the multiplexers 731, 732, and 733 are provided to the line memories LM0, LM1, and LM2 of each memory block, respectively. The selection control terminals of the multiplexers 731, 732, and 733 are provided with outputs of AND gates 713, 715, and 717 in the entry / read control unit 710, respectively. Entry and reading address W Add, R Add is selected by the entry / read control unit 710 and provided to any of the line memories LM0, LM1, and LM2 of each memory block.
[0096]
The dot clock selector 740 is also composed of three 2 × 1 multiplexers 741, 742, and 743. The two input terminals of each multiplexer have a write and read dot clock W Dclk, R Each Dclk is provided.
[0097]
The outputs of the multiplexers 741, 742, and 743 are provided to the line memories LM0, LM1, and LM2 of the respective memory blocks. The selection control terminals of the multiplexers 741, 742, and 743 are provided with outputs of AND gates 713, 715, and 717 in the entry / reading control unit 710, respectively. Entry and readout dot clock W Dclk, R Dclk is selectively provided to the line memories LM0, LM1, and LM2 of each memory block by the entry / read control unit 710, respectively.
[0098]
In the above, the present invention has been described using the case where the input signal is an 8-bit color signal as an example. However, the present invention is not necessarily limited to this. That is, it is obvious that those who have ordinary knowledge in this technical field can apply the present invention as it is to a color signal of 16 bits or more. It should be well understood that all the modifications of the present invention within such a range belong to the technical scope of the present invention.
[0099]
【The invention's effect】
Since the liquid crystal display device of the present invention is configured as described above, an image can be displayed on the entire LCD screen even if a mode signal having a resolution lower than the mode resolution supported by the LCD is input to the LCD. .
[Brief description of the drawings]
FIG. 1 is a diagram showing a video display area according to the present invention when a VGA mode signal is provided to an XGA mode liquid crystal display device.
FIG. 2 is a block diagram showing a circuit configuration of a liquid crystal display control device according to the present invention.
3 is a block diagram showing a peripheral circuit configuration of the memory block shown in FIG. 2;
4 is a block diagram showing an embodiment of the output selection circuit shown in FIG. 2. FIG.
FIG. 5 shows a time series of a line memory in which a write operation is performed and a line memory in which a read operation is performed in each memory block when a VGA mode signal is provided to the liquid crystal display device of the present invention. The figure shown along.
FIG. 6 shows a time series of a line memory in which a write operation is performed and a line memory in which a read operation is performed in order in each memory block when an SVGA mode signal is provided to the liquid crystal display device of the present invention. The figure shown along.
7 is a circuit diagram showing an embodiment of the horizontal output generation circuit shown in FIG. 2;
FIG. 8 is a timing chart of a vertical synchronization signal and a horizontal output signal.
FIG. 9 is a circuit diagram showing an embodiment of the flag circuit shown in FIG. 2;
FIG. 10 is a circuit diagram showing an embodiment of the memory selection control circuit shown in FIG. 2;
FIG. 11 is a timing chart for explaining a process in which a line memory for a read operation is selected according to an entry operation.
12 is a circuit diagram illustrating a preferred embodiment of the memory management circuit shown in FIG. 3;
FIG. 13 is a block diagram schematically showing the configuration of an active matrix liquid crystal display device.
FIG. 14 is a block diagram showing a circuit configuration of a conventional liquid crystal display device;
FIG. 15 is a diagram showing an image display area according to a conventional technique when a VGA mode signal is provided to an XGA mode liquid crystal display device;
[Explanation of symbols]
100 microcomputer
200 dot clock generator
300 Horizontal output generator
400 memory
500 Flag circuit
600 Memory selection control circuit
700 Memory management circuit

Claims (10)

A horizontal synchronizing signal (Hsync) and a vertical synchronizing signal (Vsync) provided from the host are input, and the host support display mode is discriminated from this input, and a horizontal output signal (Hout) having a frequency corresponding to the discriminated mode. LCD control means for outputting a dot clock signal (R Dclk) and converting an analog color signal provided from the host into a digital color signal (Rin, Gin, Bin) suitable for the display mode of the corresponding LCD panel;
LCD driving means for driving the LCD panel by inputting the horizontal output signal and the dot clock signal,
Converting the host support display mode signal into the display mode signal of the corresponding LCD panel;
In the liquid crystal display device in which the frame rate of the support display mode of the host and the frame rate of the display mode of the corresponding LCD panel are the same,
The LCD control means receives a horizontal synchronization signal H in and a vertical synchronization signal V sync , and determines the host support display mode from the input, and outputs a horizontal output corresponding to the determined host support display mode. Display mode discrimination means (100) for outputting a data signal according to the waveform of the signal;
Memory means (400) for storing digital color signals (R in , G in , B in ), and input dot clock signal (WDclk) for receiving the horizontal synchronizing signal and for inputting operation of the memory means And a read dot clock signal (R for read operation of the memory means) Dot clock generation means (200) for generating Dclk);
Horizontal output signal generating means (300) for receiving the data signal in response to the vertical synchronization signal and generating the horizontal output signal in synchronization with the read dot clock signal;
Memory control for inputting the horizontal synchronizing signal and the writing dot clock signal and controlling the writing operation of the memory means, and for inputting the horizontal output signal and the reading dot clock signal to control the reading operation of the memory means. Means (500, 600, 700),
The data signal output from the display mode determining means includes a first data signal (TA) indicating a period of a horizontal output signal and a second data signal (PW) indicating a pulse width of the horizontal output signal,
The horizontal output signal generating means loads the first data signal (TA) in response to the vertical synchronizing signal V sync and reads the read dot clock signal (R A counter (301) that counts down the loaded value each time a leading edge of Dclk) occurs;
A first comparator that outputs a signal of a predetermined level when the first data signal TA and the output of the counter (301) are the same;
A second comparator that outputs the signal of the predetermined level when the lower n-bit signal of the first data signal (TA) and the second data signal (PW) are the same;
A liquid crystal display device including a JK flip-flop (304) for receiving the output of the first comparator and the output of the second comparator at a J input terminal and a K input terminal, respectively. A horizontal synchronizing signal (Hsync) and a vertical synchronizing signal (Vsync) provided from the host are input, and the host support display mode is discriminated from this input, and a horizontal output signal (Hout) having a frequency corresponding to the discriminated mode. LCD control means for outputting a dot clock signal (R Dclk) and converting an analog color signal provided from the host into a digital color signal (Rin, Gin, Bin) suitable for the display mode of the corresponding LCD panel;
LCD driving means for driving the LCD panel by inputting the horizontal output signal and the dot clock signal,
Converting the host support display mode signal into the display mode signal of the corresponding LCD panel;
In the liquid crystal display device in which the frame rate of the support display mode of the host and the frame rate of the display mode of the corresponding LCD panel are the same,
The LCD control means receives a horizontal synchronization signal Hin and a vertical synchronization signal Vsync, and determines the support display mode of the host from the input, and outputs a horizontal output signal corresponding to the determined support display mode of the host. Display mode discrimination means (100) for outputting a data signal according to the waveform;
Memory means (400) for storing digital color signals (Rin, Gin, Bin), input dot clock signal (WDclk) for inputting operation of the memory means and receiving the horizontal synchronizing signal, and the memory Dot clock generating means (200) for generating a read dot clock signal (R Dclk) for the reading operation of the means;
Horizontal output signal generating means (300) for receiving the data signal in response to the vertical synchronization signal and generating the horizontal output signal in synchronization with the read dot clock signal;
Memory control for inputting the horizontal synchronizing signal and the writing dot clock signal and controlling the writing operation of the memory means, and for inputting the horizontal output signal and the reading dot clock signal to control the reading operation of the memory means. Means (500, 600, 700),
The memory control means has a line memory in the memory block, and designates a line memory in which a write operation and a read operation are performed in a predetermined order from the line memory in each memory block. Flag means (500) for generating a plurality of flags,
Responsive to the plurality of flags provided from the flag means, a line memory in which the writing operation and the reading operation are performed is selected while one line memory is not simultaneously selected for the writing operation and the reading operation. The first memory selection signal (RSel) and the second memory selection signal (R (Sel) generating memory selection control means (600);
Memory management means for receiving a horizontal synchronization signal, horizontal output signal, entry dot clock signal and readout dot clock signal, and managing memory access for entry and readout operations of the memory means while being controlled by the memory selection control means (700)
Entry flag generating means (510) for generating entry flags (Fa, Fb, and Fc) for entry operation in synchronization with the horizontal synchronization signal (H sync );
And a read flag generating means (520) for generating a read flag (Fd, Fe, Ff) for the read operation in synchronization with the horizontal output signal (H out ). 3. A liquid crystal display device according to claim 2, wherein each flag generating means includes a rotate shift register. A horizontal synchronizing signal (Hsync) and a vertical synchronizing signal (Vsync) provided from the host are input, and the host support display mode is discriminated from this input, and a horizontal output signal (Hout) having a frequency corresponding to the discriminated mode. LCD control means for outputting a dot clock signal (R Dclk) and converting an analog color signal provided from the host into a digital color signal (Rin, Gin, Bin) suitable for the display mode of the corresponding LCD panel;
LCD driving means for driving the LCD panel by inputting the horizontal output signal and the dot clock signal,
Converting the host support display mode signal into the display mode signal of the corresponding LCD panel;
In the liquid crystal display device in which the frame rate of the support display mode of the host and the frame rate of the display mode of the corresponding LCD panel are the same,
The LCD control means receives a horizontal synchronization signal Hin and a vertical synchronization signal Vsync, and determines the support display mode of the host from the input, and outputs a horizontal output signal corresponding to the determined support display mode of the host. Display mode discrimination means (100) for outputting a data signal according to the waveform;
Memory means (400) for storing digital color signals (Rin, Gin, Bin), input dot clock signal (WDclk) for inputting operation of the memory means and receiving the horizontal synchronizing signal, and the memory Dot clock generating means (200) for generating a read dot clock signal (R Dclk) for the reading operation of the means;
Horizontal output signal generating means (300) for receiving the data signal in response to the vertical synchronization signal and generating the horizontal output signal in synchronization with the read dot clock signal;
Memory control for inputting the horizontal synchronizing signal and the writing dot clock signal and controlling the writing operation of the memory means, and for inputting the horizontal output signal and the reading dot clock signal to control the reading operation of the memory means. Means (500, 600, 700),
The memory control means has a line memory in the memory block, and designates a line memory in which a write operation and a read operation are performed in a predetermined order from the line memory in each memory block. Flag means (500) for generating a plurality of flags,
Responsive to the plurality of flags provided from the flag means, a line memory in which the writing operation and the reading operation are performed is selected while one line memory is not simultaneously selected for the writing operation and the reading operation. Memory selection control means (600) for generating a first memory selection signal (RSel) and a second memory selection signal (R Sel);
Memory management means for receiving a horizontal synchronization signal, horizontal output signal, entry dot clock signal and readout dot clock signal, and managing memory access for entry and readout operations of the memory means while being controlled by the memory selection control means (700)
The memory selection control means predicts whether or not the line memory is selected for the next read operation before the completion of the write operation of the line memory currently being written, and for the next read operation. A liquid crystal display including selection error monitoring means (610) for generating a read flag control signal (RFC1) for disabling the read flag generation means (520) when it is determined that the line memory is selected in apparatus. The memory selection control means generates a horizontal synchronization signal (H sync ) And horizontal output signal (H out ) A cyclic error monitoring means (620) for generating another read flag control signal (RFC2) in order to enable the read flag generation means (520) when the timings match,
  5. The control signal output means (630) for selectively providing any one of the read flag control signals (RFC1, RFC2) to the read flag generating means (520). Liquid crystal display device. The selection error monitoring means (610) generates a horizontal output signal (H out ) (612, 613, and 614) for latching the read flag (Ff, Fd, and Fe) in synchronization with
  5. The means (615, 616, 617, and 618) for comparing whether the read flag (Ff, Fd, Fe) and the entry flag (Fa, Fb, Fc) are the same. Liquid crystal display device. The circulation error monitoring means (620) includes counters (621, 622, and 623);
  Means (624, 625, 626) for controlling the output range of the counter in response to a mode display signal provided from the microcomputer (100);
  Reset signals provided from the microcomputer (100) ( Reset ) And means (627) for resetting the counter in response to the mode display signal;
  6. Flag control signal generating means (628) for receiving said output of said counter and generating said other one read flag control signal (RFC2) for enabling read flag generating means (520). The liquid crystal display device described. The control signal output means (630) receives input signals for read flags (RFC1, RFC2), respectively,
  The liquid crystal display device according to claim 5, further comprising an OR gate (631) having an output terminal connected to an enable terminal of the read flag generating means. In response to the first memory selection signal provided from the memory selection control means (600), the memory management means (700) records the line memory of each memory block. Entry / read control means (710) for controlling input and read operations;
  Horizontal sync signal (H sync ) Horizontal output signal (H out ), Dot clock signal (W Dclk) and the read dot clock signal (R Dclk) and an address generating means 720 for generating a write address (WAdd) and a read address (RAdd) for a memory read operation and a memory write operation;
  Controlled by the entry / read control means and the entry address (WAdd) and the read address (R Address selection means 730 for selectively providing (Add) to the line memories LM0, LM1, LM2 of each memory block,
  A dot clock signal (WDclk, R) controlled by the writing / reading control means and for writing and reading. 6. A liquid crystal display device according to claim 5, further comprising dot clock selection means 740 for selectively providing Dclk) to the line memories (LM0, LM1, LM2) of the respective memory blocks. Horizontal synchronization signal (H sync ) And vertical sync signal (V sync ) Is input, and the host's support display mode is determined from this input, and a horizontal output signal (H) having a frequency corresponding to the determined mode. out ) And dot clock signal (R Dclk), and an analog color signal provided from the host is converted into a digital color signal (R) adapted to the display mode of the corresponding LCD panel. in , G in , B in LCD control means for converting to
  LCD driving means for driving the LCD panel by inputting the horizontal output signal and the dot clock signal,
  Converting the host support display mode signal into the display mode signal of the corresponding LCD panel;
  In the liquid crystal display device in which the frame rate of the support display mode of the host and the frame rate of the display mode of the corresponding LCD panel are the same,
  The LCD control means controls the horizontal synchronization signal H in And vertical synchronization signal V sync And a display mode determination means (100) for determining the host support display mode from the input and outputting a data signal in accordance with the waveform of the horizontal output signal corresponding to the determined host support display mode. )When,
  Digital color signal (R in , G in , B in ) For storing the memory means (400), the horizontal sync signal and the input dot clock signal (WDclk) for the write operation of the memory means and the read dot for the read operation of the memory means Clock signal (R Dot clock generation means (200) for generating Dclk);
  Horizontal output signal generating means (300) for receiving the data signal in response to the vertical synchronization signal and generating the horizontal output signal in synchronization with the read dot clock signal;
  Memory control for inputting the horizontal synchronizing signal and the writing dot clock signal and controlling the writing operation of the memory means, and for inputting the horizontal output signal and the reading dot clock signal to control the reading operation of the memory means. Means (500, 600, 700),
  The memory selection control means generates a horizontal synchronization signal (H sync ) And horizontal output signal (H out ) A cyclic error monitoring means (620) for generating another read flag control signal (RFC2) in order to enable the read flag generation means (520) when the timings match,
  Control signal output means (630) for selectively providing any one of the read flag control signals (RFC1, RFC2) to the read flag generation means (520);
  The memory management means (700) is a write / read control means for controlling the line memory write and read operations of each memory block in response to the first memory selection signal provided from the memory selection control means (600). (710),
  Horizontal sync signal (H sync ) Horizontal output signal (H out ), Dot clock signal (W Dclk) and the read dot clock signal (R Dclk) and an address generating means 720 for generating a write address (WAdd) and a read address (RAdd) for a memory read operation and a memory write operation;
  Controlled by the entry / read control means and the entry address (WAdd) and reading Address (R Address selection means 730 for selectively providing (Add) to the line memories LM0, LM1, LM2 of each memory block,
  A dot clock signal (WDclk, R) controlled by the writing / reading control means and for writing and reading. And a dot clock selection means 740 for selectively providing Dclk) to the line memories (LM0, LM1, LM2) of the respective memory blocks.

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