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JP4094970B2 - Manufacturing method of capacitor for semiconductor device and electronic device using this capacitor - Google Patents
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JP4094970B2 - Manufacturing method of capacitor for semiconductor device and electronic device using this capacitor - Google Patents

Manufacturing method of capacitor for semiconductor device and electronic device using this capacitor Download PDF

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JP4094970B2
JP4094970B2 JP2003053123A JP2003053123A JP4094970B2 JP 4094970 B2 JP4094970 B2 JP 4094970B2 JP 2003053123 A JP2003053123 A JP 2003053123A JP 2003053123 A JP2003053123 A JP 2003053123A JP 4094970 B2 JP4094970 B2 JP 4094970B2
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capacitor
thin film
dielectric thin
forming
manufacturing
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JP2004006678A (en
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正 賢 李
ヨセプ 閔
永 眞 ▲曹▼
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69394—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing titanium, e.g. TiO2
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/69398—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides the material having a perovskite structure, e.g. BaTiO3
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
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    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
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Description

【０００１】
【発明の属する技術分野】
本発明は半導体デバイス用のキャパシタに係り、より詳細には、白金族元素で構成される上部電極及び下部電極と、前記上部電極と前記下部電極との間に形成された誘電体薄膜と、前記下部電極と前記誘電体薄膜との間に形成され、４族、１３族またはＴａの金属酸化物で構成されるバッファ層とを備えることを特徴とするキャパシタにおいて、誘電体薄膜の形成時に電極形成用の物質の酸化が効率よく抑えられた半導体デバイス用のキャパシタ及びその製造方法並びに該キャパシタを用いる電子デバイスに関する。
【０００２】
【従来の技術】
メモリの集積度が高くなるに伴い、データ記憶装置の単位セルのサイズ及びキャパシタの面積がますます小さくなってきている。このため、限られた面積に大きな静電容量を有するキャパシタを実現するために高誘電率のキャパシタ用誘電体を使おうとする研究が続いてきており、その結果、ＳｉＯ2、Ｓｉ3Ｎ4などの低誘電物質より高い誘電率を持つ酸化タンタル（Ｔａ2Ｏ5）やチタン酸ストロンチウム（ＳｒＴｉＯ3）などの高誘電物質に対する必要性が高まりつつある。
【０００３】
しかし、このような高誘電物質を使用するとしても、高容量のキャパシタを実現するためには、３次元構造のキャパシタが必要となる。このため、単原子層蒸着法（ＡＬＤ：Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ）が用いられている。
【０００４】
ＡＬＤ法は、まず、前駆体である有機金属化合物を基板上に化学的に吸着させた後、これを酸化雰囲気下で処理して目的とする金属酸化物誘電体薄膜を得る方法である。この方法は、時分割で前駆体及び酸化剤が導入され、強い酸化剤で前駆体の有機物が除去できるため、非常に有利である。
【０００５】
しかしながら、単原子層の蒸着に際し、誘電体薄膜の下部電極がＲｕのように酸化し易い物質よりなる場合には、後記する図１に示すように、Ｒｕ電極に変形が起きて誘電体薄膜の特性が劣化する。それゆえ、このような誘電体薄膜では、高度に集積化することが困難になる。
【０００６】
図１は、従来の技術によるＯ3の単原子層蒸着（ＡＬＤ）を用いて、Ｒｕ下部電極の上にＳｒＴｉＯ3薄膜を形成したキャパシタの断面構造を示す写真である。図１に示すように、キャパシタにおいて、Ｒｕ下部電極の突出現象が生じるということが確かめられる。
【０００７】
図２は、図１に示すキャパシタで使われるＲｕの活性度の温度依存性を示すグラフである。図２に示すように、Ｒｕは、酸素が存在する環境では、ＲｕＯ2またはＲｕＯ4に変わり易く、これによりＲｕ電極の変形が発生する。
【０００８】
【発明が解決しようとする課題】
本発明は、前記問題点を解決するためになされたものであって、その第１の目的は、誘電体薄膜の形成時に電極形成用の物質の酸化が効率よく抑えられた半導体デバイス用のキャパシタを提供することである。
【０００９】
また、本発明の第２の目的は、前記問題点を解決して、誘電体薄膜の形成時に電極形成用の物質の酸化を効率よく抑えることができる半導体デバイス用のキャパシタの製造方法を提供することである
【００１０】
さらに、本発明の第３の目的は、前記キャパシタを用いて、誘電体薄膜の高度な集積化が可能になる電子デバイスを提供することである。
【００１１】
【課題を解決するための手段】
（１）前記目的を達成するための本発明に係る半導体デバイス用のキャパシタは、白金族元素で構成される上部電極及び下部電極と、前記上部電極と前記下部電極との間に形成された誘電体薄膜と、
前記下部電極と前記誘電体薄膜との間に形成され、４族、１３族またはＴａの金属酸化物で構成されるバッファ層とを備えて構成される。
【００１２】
（２）本発明は、前記半導体デバイス用のキャパシタにおいて、前記４族、１３族またはＴａの金属酸化物が、ＴｉＯ２、Ａｌ２Ｏ３、Ｔａ２Ｏ５及びＨｆＯ２からなる群から選ばれた少なくとも１種で構成されることが望ましい。
【００１３】
（３）本発明は、前記半導体デバイス用のキャパシタにおいて、前記誘電体薄膜が、ＳｒＴｉＯ3、ＢａＴｉＯ3またはＰｂ（Ｚｒ，Ｔｉ）Ｏ3なる群から選ばれた少なくとも１種で構成されることが望ましい。
【００１４】
（４）本発明は、前記半導体デバイス用のキャパシタにおいて、前記白金族元素が、ルテニウム、オスミウム、イリジウム及び白金からなる群から選ばれた少なくとも１種で構成されることが望ましい。
【００１５】
（５）また、前記目的を達成するための本発明に係る第１の態様の半導体デバイス用のキャパシタの製造方法は、（ａ−１）白金族元素で構成される下部電極の上に、バッファ層形成用の前駆体を用いて単原子層蒸着を行い、バッファ層を形成する段階と、（ｂ−１）前記バッファ層の上に誘電体薄膜形成用の前駆体を用いて単原子層蒸着を行い、誘電体薄膜を形成する段階と、（ｃ−１）前記誘電体薄膜の上に白金族元素で構成される上部電極を形成する段階とを備えて構成される。
【００１６】
（６）本発明は、前記本発明に係る第１の態様の半導体デバイス用のキャパシタ製造方法において、前記段階（ａ−１）で、バッファ層形成用の前駆体が、Ｔｉ（ｉ−ＯＰｒ）2（ｔｍｈｄ）2、Ａｌ（ＣＨ3）3またはＨｆ（ＯＢｕ）4からなる群から選ばれた少なくとも１種で構成されることが望ましい。なお、本明細書において、前記ｉ−ＯＰｒは、イソプロポキシ（ｉｓｏｐｒｏｐｏｘｙ）、前記ｔｍｈｄは、テトラメチルヘプタンジオネート（ｔｅｔｒａｍｅｔｈｙｌｈｅｐｔａｎｅｄｉｏｎａｔｅ）、及び前記ＯＢｕはブトキシ（ｂｕｔｏｘｙ）を意味する。
【００１７】
（７）本発明は、前記前記本発明に係る第１の態様の半導体デバイス用のキャパシタ製造方法において、前記段階（ａ−１）で、単原子層蒸着の温度が、２００〜５００℃であることが望ましい。
【００１８】
（８）本発明は、前記前記本発明に係る第１の態様の半導体デバイス用のキャパシタ製造方法において、前記誘電体薄膜形成用の前駆体が、Ｓｒ（ｔｍｄｈ）2、Ｓｒ（ｍｅｔｈｄ）2、ＴｉＯ（ｔｍｈｄ）2及びＴｉ（ｉ−ＯＰｒ）2（ｔｍｈｄ）2からなる群から選ばれた少なくとも１種で構成されることが望ましい。なお、本明細書において、前記ｍｅｔｈｄは、メトキシエトキシテトラメチルヘプタンジオネート（ｍｅｔｈｏｘｙｅｔｈｏｘｙｔｅｔｒａｍｅｔｈｙｌｈｅｐｔａｎｅｄｉｏｎａｔｅ）を意味する。
【００１９】
（９）前記目的を達成するための本発明に係る第２の態様の半導体デバイス用のキャパシタの製造方法は、（ａ−２）白金族元素で構成される下部電極の上面に一酸化炭素ＣＯを吸着させる段階と、（ｂ−２）前記下部電極を還元雰囲気下に設置し、格子酸素を生成する段階と、（ｃ−２）前記格子酸素を用い、且つ、誘電体薄膜形成用の前駆体を用いて原子層蒸着を行い、誘電体薄膜を形成する段階と、（ｄ−２）前記誘電体薄膜の上に白金族元素で構成される上部電極を形成する段階とを備えて構成される。
【００２０】
（１０）本発明は、前記本発明に係る第２の態様の半導体デバイス用のキャパシタ製造方法において、前記誘電体薄膜形成用の前駆体が、Ｓｒ（ｔｍｄｈ）2、Ｓｒ（ｍｅｔｈｄ）2、ＴｉＯ（ｔｍｈｄ）2及びＴｉ（ｉ−ＯＰｒ）2（ｔｍｈｄ）2からなる群から選ばれた少なくとも１種で構成されることが望ましい。
【００２１】
（１１）本発明は、前記本発明に係る第２の態様の半導体デバイス用のキャパシタ製造方法において、前記段階（ｂ−２）で、還元雰囲気下における処理温度が、１００〜５００℃であることが望ましい。
【００２２】
（１２）前記目的を達成するための本発明に係る電子デバイスは、白金族元素で構成される上部電極及び下部電極と、前記上部電極と前記下部電極との間に形成された誘電体薄膜と、前記下部電極と前記誘電体薄膜との間に形成され、４族、１３族またはＴａの金属酸化物で構成されるバッファ層とを備えたキャパシタで構成される。
【００２３】
（１３）本発明は、前記電子デバイスにおいて、前記４族、１３族またはＴａの金属酸化物が、ＴｉＯ２、Ａｌ２Ｏ３、Ｔａ２Ｏ５及びＨｆＯ２からなる群から選ばれた少なくとも１種で構成されることが望ましい。
【００２４】
（１４）本発明は、前記電子デバイスにおいて、前記誘電体薄膜が、ＳｒＴｉＯ3、ＢａＴｉＯ3またはＰｂ（Ｚｒ，Ｔｉ）Ｏ3なる群から選ばれた少なくとも１種で構成されることが望ましい。
【００２５】
（１５）本発明は、前記電子デバイスにおいて、前記白金族元素が、ルテニウム、オスミウム、イリジウム及び白金からなる群から選ばれた少なくとも１種で構成されることが望ましい。
【００２６】
（１６）本発明は、前記電子デバイスが、ダイナミックランダムアクセスメモリ（ＤＲＡＭ）または不揮発性メモリ（ＦＲＡＭ）であることが望ましい。
【００２７】
【発明の実施の形態】
以下、添付した図面に基づき、本発明に係る半導体デバイス用のキャパシタの好ましい実施形態の各構成及び動作及び装置前記本発明に係る半導体デバイス用のキャパシタの製造方法並びに前記キャパシタを用いる電子デバイスについて詳細に説明する。
【００２８】
本発明において、誘電体薄膜の形成時に、電極の形成物質である白金族元素、特に、Ｒｕの酸化を防ぐために、前記誘電体薄膜と前記電極との間にバッファ層を形成する。ここで、前記バッファ層は、４族、１３族またはＴａの金属酸化物で構成され、ＴｉＯ２、Ａｌ２Ｏ３、Ｔａ２Ｏ５及びＨｆＯ２からなる群から選ばれた少なくとも１種で構成されることが望ましい。このようなバッファ層は、バッファ層形成用の前駆体の単原子蒸着により形成できる。前記バッファ層形成用の前駆体としては、基板に吸着して副生成物を生成しない材料が好ましく、具体的には配位子が小さい、あるいは基板への吸着時に容易に分解する有機金属化合物を使用することが望ましい。このような前記前駆体用の材料を用いて、前記電極の上部に充填密度の高い単原子層を形成することができる。
【００２９】
前記バッファ層としてＴｉＯ2膜を形成しようとする場合には、バッファ層形成用の金属前駆体として、Ｔｉ（ｉ−ＯＰｒ）4またはＴｉ（ｉ−ＯＰｒ）2を使用し、Ａｌ2Ｏ3膜を形成しようとする場合には、Ａｌ（ＣＨ3）3またはＡｌＣｌ3を使用し、Ｔａ2Ｏ5を形成しようとする場合には、Ｔａ（ＯＥｔ）5を使用し、そしてＨｆＯ2膜を形成しようとする場合にはＨｆＣｌ4またはＨｆ（ＯＢｕ）4などを使用することが望ましい。なお、ここで、ＯＥｔは、エトキシ（ｅｔｈｏｘｙ）を意味する。
【００３０】
そして、電極上に充填密度の高い原子層を形成すれば、誘電体薄膜の形成時にＲｕ電極の表面がＯ3またはＯ2と直接的に接触しなくなり、電極の酸化による電極の変形及び誘電体薄膜の特性劣化の問題は未然に防ぐことができる。
【００３１】
前記バッファ層形成用の前記前駆体の単原子層蒸着の温度は、各前駆体の特性により異なるが、２００〜５００℃であることが望ましい。もし、前記蒸着温度が２００℃未満である場合には、酸化剤として使われるＯ3との反応性が低下し、一方、５００℃を超える場合には、ＡＬＤ法では、前駆体が分解し、前記バッファ層が形成されなくなる。
【００３２】
以下、本発明に係るある半導体デバイス用のキャパシタの製造方法の望ましい１つの実施形態について詳細に説明する。
【００３３】
まず、白金族元素を用いて下部電極を形成する。この時、白金族元素としては、Ｒｕ、Ｏｓ、Ｉｒ及びＰｔからなる群から選ばれた少なくとも１種で構成されることが望ましい。
【００３４】
つぎに、前記下部電極の上にバッファ層形成用の前駆体を用いて単原子層蒸着を行い、バッファ層を形成する。
【００３５】
そして、この前記バッファ層の上に誘電体薄膜形成用の前駆体を用いた原子層蒸着を行い、誘電体薄膜を形成する。ここで、前記誘電体薄膜は、ＳｒＴｉＯ3、ＢａＴｉＯ3、Ｐｂ（Ｚｒ，Ｔｉ）Ｏ3からなる群から選ばれた少なくとも１種で構成されることが望ましい。ここで、前記誘電体薄膜がＳｒＴｉＯ3である場合には、Ｓｒ源として、Ｓｒ（ｔｍｄｈ）2またはＳｒ（ｍｅｔｈｄ）2を用い、一方、Ｔｉ源として、ＴｉＯ（ｔｍｈｄ）2またはＴｉ（ｉ−ＯＰｒ）2（ｔｍｈｄ）2を用いて、これらを組み合わせて混合することにより、前記誘電体薄膜を形成するための原料とする。つぎに、酸素ガスまたは熱源を用いて単原子層蒸着を行う。この時、単原子層蒸着の温度は、３００〜５００℃であることが望ましい。
【００３６】
それから、前記誘電体薄膜の上に白金族元素を用いて、上部電極を形成することにより、本発明の半導体デバイス用のキャパシタが完成する。
【００３７】
また、本発明において、誘電体薄膜の形成時に使われる酸化剤として、電極形成用の物質内に吸着された一酸化炭素（ＣＯ）から得られる格子酸素を用いることができる。
【００３８】
図３は、本発明に係る半導体デバイス用のキャパシタの製造方法において、Ｒｕ電極を用いた場合に格子酸素を生成する過程を模式的に示す図面である。図３に示すように、まず、ＣＯが、還元雰囲気下でＲｕ電極上に吸着する。そして、ＣＯの炭素がＣＨ4として除去されるため、Ｒｕ電極の表面には格子酸素のみが残る。この格子酸素を酸化剤として用いて、誘電体薄膜が、後続するプロセスの単原子層蒸着により形成される。
【００３９】
つぎに、本発明に係る半導体デバイス用のキャパシタの製造方法において、前記格子酸素を用いてキャパシタを製造する方法を詳細に説明する。
【００４０】
まず、白金族元素で構成される下部電極の上面にＣＯを吸着させる。つぎに、前記のＣＯが吸着した下部電極を還元雰囲気下に設置して、格子酸素を生成させる。この時、還元雰囲気下における処理温度は、１００〜５００℃に保持されることが望ましい。これは、前記処理温度が１００℃未満である場合には、ＣＯの還元反応が困難であり、一方、５００℃を超える場合には、ＣＯが、初めに、前記下部電極の表面から脱着してしまうからである。ここで、還元雰囲気は、水素などの還元性ガスを用いて作ることができる。
【００４１】
つぎに、前記格子酸素を用い、且つ、誘電体薄膜形成用の前駆体を用いて原子層の蒸着を行い、誘電体薄膜を形成する。ここで、誘電体薄膜の形成材料及びその形成方法は、前記した通りである。
【００４２】
そして、本発明に係る半導体デバイスのキャパシタが、前記誘電体薄膜の上に白金族元素で構成される上部電極を形成することにより完成する。
【００４３】
前記キャパシタは、各種の電子デバイスに適用できる。このような電子デバイスの具体例としては、ＤＲＡＭ素子やＦＲＡＭ素子が挙げられる。
【００４４】
図４Ａ及び図４Ｂは、本発明に係る実施形態のキャパシタを用いた各種メモリ素子の構造を模式的に示す断面図である。なお、図４Ａ及び図４Ｂにおいて、同一符号には同一の構成要素を対応させてある。すなわち、符号４０はシリコン基板を、符号４１は活性領域を、符号４２は非活性領域を、符号４３は下部構造を、符号４４はゲート電極を、符号４５はポリシリコン膜を、符号４６は下部電極を、符号４７はバッファ層を、符号４８はＳｒＴｉＯ３誘電体薄膜を、符号５０は上部電極を、そして符号５２はキャパシタを、各々示すものとする。
【００４５】
図４Ａは、本発明に係る第１実施形態のキャパシタを用いた単一トランジスタ型メモリ素子の構造を模式的に示す断面図である。また、図４Ｂは、本発明に係る第２実施形態のキャパシタを用いた１Ｔｒ−１Ｃ型メモリ素子の構造を模式的に示す断面図である。
【００４６】
前記図４Ａ及び図４Ｂにメモリ素子の各種の実施の形態を示したが、誘電体薄膜を用いる他の電子デバイスにも適用可能であるということは言うまでもない。
【００４７】
以下、本発明を以下の各実施形態を挙げて詳細に説明するが、本発明が下記の各実施形態にのみ限定されるものではない。
【００４８】
（第１実施形態）
まず、バッファ層形成用の前駆体として、テトラヒドロフラン（ＴＨＦ）を溶媒とする０．１Ｍ／Ｔｉ（ｉ−ＯＰｒ）2（ｔｍｈｄ）2を含む溶液を用い、酸化剤としてＯ3を用い、約３２５℃において単原子層蒸着を行い、第１のＲｕ電極の上にＴｉＯ2バッファ層を形成した。それから、前記バッファ層の上にＳｒ（ｍｅｔｈｄ）2及びＴｉ（ｉ−ＯＰｒ）2（ｔｍｈｄ）2を前駆体として４００℃で、Ｏ3を酸化剤として用い、単原子層蒸着を行い、ＳｒＴｉＯ3誘電体薄膜を形成した。そして、前記ＳｒＴｉＯ3誘電体薄膜の上にＲｕ電極を形成することにより、第１実施形態のキャパシタを製造した（図４Ａ参照）。
【００４９】
（第２実施形態）
バッファ層形成用の前駆体として、Ａｌ（ＣＨ3）3を用い、酸化剤としてＯ3を用いて約４００℃において原子層の蒸着を行い、Ｒｕ電極の上にＡｌ2Ｏ3バッファ層を形成したことを除いては、前記した、第２実施形態の方法と同様にして、第２実施形態のキャパシタを製造した（図４Ｂ参照）。
【００５０】
（第３実施形態）
Ｒｕ電極の上にＣＯを吸着させた後、これを水素ガス雰囲気下で約４００℃において処理して格子酸素を生成した。つぎに、第１実施形態の方法と同様にしてＳｒＴｉＯ３誘電体薄膜を形成した。つぎに、前記ＳｒＴｉＯ３誘電体薄膜の上にＲｕ電極を形成して、第３実施形態のキャパシタを製造した。
【００５１】
図５は、本発明に係る第１実施形態のキャパシタにおけるＲｕ薄膜の上に形成されたＳｒＴｉＯ3薄膜の断面の透過電子顕微鏡（ＴＥＭ：Ｔｒａｎｓｍｉｓｓｉｏｎ Ｅｌｅｃｔｒｏｎ Ｍｉｃｒｏｓｃｏｐｅ）による写真である。図５に示すように、まず、ＳｒＴｉＯ3薄膜の下部にＴｉＯ2バッファ層が形成されており、そして、その下部にＲｕ電極が配置されている。また、Ｒｕ電極の突出による障害はないということが分かる。
【００５２】
図６は、本発明に係る第２実施形態のキャパシタにおけるＲｕ薄膜の上に形成されたＳｒＴｉＯ3薄膜の断面の透過電子顕微鏡（ＴＥＭ）による写真である。図６に示すように、バッファ層を用いることにより、ＳｒＴｉＯ3の蒸着後にもＲｕの酸化による突起や表面粗さの増加が起きなかったということが分かる。
【００５３】
図７Ａ及び図７Ｂは、それぞれ、本発明に係る第３実施形態に基づいて製造されたキャパシタの電気的な特性を測定した結果を示すグラフである。
【００５４】
図７Ａは、本発明に係る第３実施形態に基づいて製造されたキャパシタの電圧と電流密度との関係を示すグラフである。図７Ａにおいて、グラフの□-□のプロットは、電圧を負（−）の値から正（＋）の値に変化させた場合の電流密度の変化を表わし、また、■−■のプロットは、電圧を正（＋）の値から負（−）の値に変化させた場合の電流密度の変化を表わす。
【００５５】
図７Ａに示すように、通常、ＤＲＡＭの規格である１Ｖで１０-7Ａ／ｃｍ2が確保できているということが分かった。
【００５６】
そして、図７Ｂは、本発明に係る第３実施形態に基づいて製造されたキャパシタのバイアス電圧とｔｏｘ（ＳｉＯ2の厚さ）との関係を示すグラフである。図７Ｂにおいて、グラフの□-□のプロットは、ｔｏｘを表わし、■−■のプロットは誘電損失因子であるｔａｎδを表わす。ここで、ｔｏｘは、下記の数式で表わせる。
【００５７】
【数１】
ｔｏｘ＝ＳｉＯ2の厚さ＝｛（ＳｉＯ2の誘電定数×上部電極の面積）｝／（キャパシタのキャパシタンス） …（１）
【００５８】
ここで、ｔｏｘの値が小さいほど、誘電膜の特性はより優れたものとなる。図７Ｂに示すように、ｔｏｘは、蒸着後に、６．８Åであり、１６ＧＢ級以上のＤＲＡＭにおいて必要とされる誘電膜７Åの厚さが確保されていることが分かる。
【００５９】
【発明の効果】
以上説明した通りに構成された本発明によれば、以下の効果を奏する。すなわち、本発明に係る半導体デバイス用のキャパシタ及びその製造方法並びにこのキャパシタを用いる電子デバイスによれば、誘電体薄膜の形成時に、Ｏ3などの強い酸化剤を用いて単原子層蒸着を行っても、下部電極であるＲｕ電極の酸化を抑えることができ、さらにＲｕ電極の変形及び誘電体薄膜の特性の劣化を防止できる。よって、本発明に係るキャパシタは、高集積度のメモリにおいて要求される優れた電子的な特性を有した誘電体特性が確保でき、ＤＲＡＭなどの電子デバイス素子に有用である。
【図面の簡単な説明】
【図１】従来の技術によるＯ３の単原子層蒸着（ＡＬＤ）を用いて、Ｒｕ下部電極の上にＳｒＴｉＯ３薄膜を形成したキャパシタの断面構造を示す写真である。
【図２】図１に示すキャパシタで使われるＲｕの活性度の温度依存性を示すグラフである。
【図３】本発明に係る半導体デバイス用のキャパシタの製造方法において、Ｒｕ電極を用いた場合に格子酸素を生成する過程を模式的に示す図面である。
【図４Ａ】本発明に係る第１実施形態のキャパシタを用いた単一トランジスタ型メモリ素子の構造を模式的に示す断面図である。
【図４Ｂ】本発明に係る第２実施形態のキャパシタを用いた１Ｔｒ−１Ｃ型メモリ素子の構造を模式的に示す断面図である。
【図５】本発明に係る第１実施形態のキャパシタにおけるＲｕ薄膜の上に形成されたＳｒＴｉＯ３薄膜の断面の透過電子顕微鏡（ＴＥＭ）による写真である。
【図６】本発明に係る第２実施形態のキャパシタにおけるＲｕ薄膜の上に形成されたＳｒＴｉＯ３薄膜の断面の透過電子顕微鏡（ＴＥＭ）による写真である。
【図７Ａ】本発明に係る第３実施形態に基づいて製造されたキャパシタの電圧と電流密度との関係を示すグラフである。
【図７Ｂ】本発明に係る第３実施形態に基づいて製造されたキャパシタのバイアス電圧とｔｏｘ（ＳｉＯ２の厚さ）との関係を示すグラフである。
【符号の説明】
４０ シリコン基板
４１ 活性領域
４２ 非活性領域
４４ ゲート電極
４６ 下部電極
４７ バッファ層
４８ ＳｒＴｉＯ３誘電体薄膜
５０ 上部電極
５２ キャパシタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor for a semiconductor device, and more specifically, an upper electrode and a lower electrode made of a platinum group element, a dielectric thin film formed between the upper electrode and the lower electrode, The capacitor is formed between the lower electrode and the dielectric thin film, and includes a buffer layer made of a metal oxide of Group 4, 13 or Ta , and the electrode is formed when the dielectric thin film is formed. The present invention relates to a capacitor for a semiconductor device in which oxidation of a material for use is efficiently suppressed, a manufacturing method thereof, and an electronic device using the capacitor.
[0002]
[Prior art]
As the degree of integration of memories increases, the size of unit cells and the area of capacitors in data storage devices are becoming smaller. For this reason, research to use a dielectric for a capacitor having a high dielectric constant in order to realize a capacitor having a large capacitance in a limited area has continued, and as a result, SiO 2 , Si 3 N 4, etc. There is a growing need for high dielectric materials such as tantalum oxide (Ta 2 O 5 ) and strontium titanate (SrTiO 3 ) having a higher dielectric constant than other low dielectric materials.
[0003]
However, even if such a high dielectric material is used, a capacitor having a three-dimensional structure is required to realize a high-capacity capacitor. For this reason, a monolayer deposition method (ALD: Atomic Layer Deposition) is used.
[0004]
The ALD method is a method in which an organometallic compound as a precursor is first chemically adsorbed on a substrate and then treated in an oxidizing atmosphere to obtain a target metal oxide dielectric thin film. This method is very advantageous because the precursor and the oxidizing agent are introduced in a time-sharing manner, and the organic substances of the precursor can be removed with a strong oxidizing agent.
[0005]
However, when the lower electrode of the dielectric thin film is made of a material that easily oxidizes, such as Ru, during the deposition of the monoatomic layer, the Ru electrode is deformed, as shown in FIG. Characteristics deteriorate. Therefore, it is difficult to highly integrate such a dielectric thin film.
[0006]
FIG. 1 is a photograph showing a cross-sectional structure of a capacitor in which a SrTiO 3 thin film is formed on a Ru lower electrode using O 3 monoatomic layer deposition (ALD) according to the prior art. As shown in FIG. 1, it is confirmed that a protrusion phenomenon of the Ru lower electrode occurs in the capacitor.
[0007]
FIG. 2 is a graph showing the temperature dependence of the activity of Ru used in the capacitor shown in FIG. As shown in FIG. 2, Ru is easily changed to RuO 2 or RuO 4 in an environment where oxygen is present, which causes deformation of the Ru electrode.
[0008]
[Problems to be solved by the invention]
The present invention has been made to solve the above problems, and a first object of the present invention is to provide a capacitor for a semiconductor device in which oxidation of a material for electrode formation is efficiently suppressed during formation of a dielectric thin film. Is to provide.
[0009]
In addition, a second object of the present invention is to provide a method for manufacturing a capacitor for a semiconductor device that solves the above-mentioned problems and can efficiently suppress oxidation of a substance for forming an electrode when forming a dielectric thin film. [0010]
Furthermore, a third object of the present invention is to provide an electronic device that enables highly integrated dielectric thin films using the capacitor.
[0011]
[Means for Solving the Problems]
(1) A capacitor for a semiconductor device according to the present invention for achieving the above object includes an upper electrode and a lower electrode made of a platinum group element, and a dielectric formed between the upper electrode and the lower electrode. Body thin film,
A buffer layer formed between the lower electrode and the dielectric thin film and made of a metal oxide of Group 4, 13 or Ta is configured.
[0012]
(2) The present invention provides the semiconductor device capacitor, wherein the Group 4, 13 or Ta metal oxide is selected from the group consisting of TiO 2 , Al 2 O 3 , Ta 2 O 5 and HfO 2. It is desirable that it is composed of at least one kind.
[0013]
(3) According to the present invention, in the capacitor for a semiconductor device, the dielectric thin film is composed of at least one selected from the group consisting of SrTiO 3 , BaTiO 3 or Pb (Zr, Ti) O 3. desirable.
[0014]
(4) In the capacitor for a semiconductor device according to the present invention, the platinum group element is preferably composed of at least one selected from the group consisting of ruthenium, osmium, iridium and platinum.
[0015]
(5) Moreover, the manufacturing method of the capacitor for semiconductor devices of the 1st aspect based on this invention for achieving the said objective is a buffer on the lower electrode comprised by (a-1) platinum group element. Performing monoatomic layer deposition using a precursor for layer formation to form a buffer layer; and (b-1) monoatomic layer deposition using a precursor for forming a dielectric thin film on the buffer layer. And forming a dielectric thin film, and (c-1) forming an upper electrode made of a platinum group element on the dielectric thin film.
[0016]
(6) According to the present invention, in the capacitor manufacturing method for a semiconductor device according to the first aspect of the present invention, in the step (a-1), the precursor for forming the buffer layer is Ti (i-OPr). It is desirable to be composed of at least one selected from the group consisting of 2 (tmhd) 2 , Al (CH 3 ) 3 or Hf (OBu) 4 . In the present specification, the i-OPr means isopropoxy, the tmhd means tetramethylheptanedionate, and the OBu means butoxy.
[0017]
(7) The present invention provides the method for manufacturing a capacitor for a semiconductor device according to the first aspect of the present invention, wherein the temperature of the monolayer deposition is 200 to 500 ° C. in the step (a-1). It is desirable.
[0018]
(8) The present invention provides the method for manufacturing a capacitor for a semiconductor device according to the first aspect of the present invention, wherein the precursor for forming the dielectric thin film is Sr (tmdh) 2 , Sr (methd) 2 , It is desirable to be composed of at least one selected from the group consisting of TiO (tmhd) 2 and Ti (i-OPr) 2 (tmhd) 2 . In the present specification, the methd means methoxyethoxytetramethylheptanedionate.
[0019]
(9) A method for manufacturing a capacitor for a semiconductor device according to the second aspect of the present invention for achieving the above object includes: (a-2) carbon monoxide CO on the upper surface of a lower electrode composed of a platinum group element. (B-2) placing the lower electrode in a reducing atmosphere to generate lattice oxygen; and (c-2) using the lattice oxygen and a precursor for forming a dielectric thin film. Forming a dielectric thin film by performing atomic layer deposition using a body, and (d-2) forming an upper electrode made of a platinum group element on the dielectric thin film. The
[0020]
(10) The present invention is the method of manufacturing a capacitor for a semiconductor device according to the second aspect of the present invention, wherein the precursor for forming the dielectric thin film is Sr (tmdh) 2 , Sr (methd) 2 , TiO 2 . It is desirable to be composed of at least one selected from the group consisting of (tmhd) 2 and Ti (i-OPr) 2 (tmhd) 2 .
[0021]
(11) The present invention is the method of manufacturing a capacitor for a semiconductor device according to the second aspect of the present invention, wherein, in the step (b-2), the processing temperature in a reducing atmosphere is 100 to 500 ° C. Is desirable.
[0022]
(12) An electronic device according to the present invention for achieving the object includes an upper electrode and a lower electrode made of a platinum group element, a dielectric thin film formed between the upper electrode and the lower electrode, And a capacitor having a buffer layer formed between the lower electrode and the dielectric thin film and made of a metal oxide of Group 4, 13 or Ta .
[0023]
(13) In the electronic device, the group 4, 13 or Ta metal oxide is at least one selected from the group consisting of TiO 2 , Al 2 O 3 , Ta 2 O 5 and HfO 2. It is desirable to be composed of seeds.
[0024]
(14) According to the present invention, in the electronic device, the dielectric thin film is preferably composed of at least one selected from the group consisting of SrTiO 3 , BaTiO 3, and Pb (Zr, Ti) O 3 .
[0025]
(15) In the electronic device according to the aspect of the invention, it is preferable that the platinum group element is composed of at least one selected from the group consisting of ruthenium, osmium, iridium, and platinum.
[0026]
(16) In the present invention, it is preferable that the electronic device is a dynamic random access memory (DRAM) or a nonvolatile memory (FRAM).
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, based on the attached drawings, each configuration and operation of a preferred embodiment of a capacitor for a semiconductor device according to the present invention, and an apparatus, a method for manufacturing a capacitor for a semiconductor device according to the present invention, and an electronic device using the capacitor will be described in detail. Explained.
[0028]
In the present invention, when the dielectric thin film is formed, a buffer layer is formed between the dielectric thin film and the electrode in order to prevent oxidation of the platinum group element which is the electrode forming material, particularly Ru. Here, the buffer layer is composed of a Group 4, 13 or Ta metal oxide, and is composed of at least one selected from the group consisting of TiO 2 , Al 2 O 3 , Ta 2 O 5 and HfO 2. It is desirable that Such a buffer layer can be formed by single atom deposition of a precursor for forming the buffer layer. The precursor for forming the buffer layer is preferably a material that does not adsorb on the substrate and generates a by-product. Specifically, an organic metal compound that has a small ligand or that easily decomposes when adsorbed on the substrate is used. It is desirable to use it. Using such a precursor material, a monoatomic layer having a high packing density can be formed on the electrode.
[0029]
When a TiO 2 film is to be formed as the buffer layer, Ti (i-OPr) 4 or Ti (i-OPr) 2 is used as a metal precursor for forming the buffer layer, and an Al 2 O 3 film is used. When using Al (CH 3 ) 3 or AlCl 3 , Ta (OEt) 5 is used when forming Ta 2 O 5 , and an HfO 2 film is formed. When trying to do so, it is desirable to use HfCl 4 or Hf (OBu) 4 . Here, OEt means ethoxy.
[0030]
If an atomic layer having a high packing density is formed on the electrode, the surface of the Ru electrode does not come into direct contact with O 3 or O 2 during the formation of the dielectric thin film. The problem of deterioration of the characteristics of the thin film can be prevented beforehand.
[0031]
The temperature of the monolayer deposition of the precursor for forming the buffer layer varies depending on the characteristics of each precursor, but is preferably 200 to 500 ° C. If the deposition temperature is less than 200 ° C., the reactivity with O 3 used as an oxidant decreases, whereas if it exceeds 500 ° C., the ALD method decomposes the precursor, The buffer layer is not formed.
[0032]
Hereinafter, a preferred embodiment of a method for manufacturing a capacitor for a semiconductor device according to the present invention will be described in detail.
[0033]
First, a lower electrode is formed using a platinum group element. At this time, the platinum group element is preferably composed of at least one selected from the group consisting of Ru, Os, Ir, and Pt.
[0034]
Next, monoatomic layer deposition is performed on the lower electrode using a precursor for forming a buffer layer to form a buffer layer.
[0035]
Then, atomic layer deposition using a precursor for forming a dielectric thin film is performed on the buffer layer to form a dielectric thin film. Here, the dielectric thin film is preferably composed of at least one selected from the group consisting of SrTiO 3 , BaTiO 3 , and Pb (Zr, Ti) O 3 . Here, when the dielectric thin film is SrTiO 3 , Sr (tmdh) 2 or Sr (methd) 2 is used as the Sr source, while TiO (tmhd) 2 or Ti (i−) is used as the Ti source. OPr) 2 (tmhd) 2 is used as a raw material for forming the dielectric thin film by combining and mixing them. Next, monoatomic layer deposition is performed using oxygen gas or a heat source. At this time, the temperature of monoatomic layer deposition is preferably 300 to 500 ° C.
[0036]
Then, an upper electrode is formed on the dielectric thin film using a platinum group element, thereby completing the capacitor for a semiconductor device of the present invention.
[0037]
In the present invention, lattice oxygen obtained from carbon monoxide (CO) adsorbed in a material for electrode formation can be used as an oxidant used when forming a dielectric thin film.
[0038]
FIG. 3 is a drawing schematically showing a process of generating lattice oxygen when a Ru electrode is used in the method for manufacturing a capacitor for a semiconductor device according to the present invention. As shown in FIG. 3, first, CO is adsorbed on the Ru electrode in a reducing atmosphere. Since carbon of CO is removed as CH 4 , only lattice oxygen remains on the surface of the Ru electrode. Using this lattice oxygen as an oxidant, a dielectric thin film is formed by monolayer deposition in a subsequent process.
[0039]
Next, in the method for manufacturing a capacitor for a semiconductor device according to the present invention, a method for manufacturing the capacitor using the lattice oxygen will be described in detail.
[0040]
First, CO is adsorbed on the upper surface of the lower electrode made of a platinum group element. Next, the lower electrode on which the CO is adsorbed is placed in a reducing atmosphere to generate lattice oxygen. At this time, the treatment temperature in a reducing atmosphere is desirably maintained at 100 to 500 ° C. This is because when the treatment temperature is less than 100 ° C., the reduction reaction of CO is difficult, whereas when it exceeds 500 ° C., CO is first desorbed from the surface of the lower electrode. Because it ends up. Here, the reducing atmosphere can be made using a reducing gas such as hydrogen.
[0041]
Next, an atomic layer is deposited using the lattice oxygen and a precursor for forming a dielectric thin film to form a dielectric thin film. Here, the dielectric thin film forming material and the forming method thereof are as described above.
[0042]
Then, the capacitor of the semiconductor device according to the present invention is completed by forming an upper electrode made of a platinum group element on the dielectric thin film.
[0043]
The capacitor can be applied to various electronic devices. Specific examples of such electronic devices include DRAM elements and FRAM elements.
[0044]
4A and 4B are cross-sectional views schematically showing structures of various memory elements using the capacitor according to the embodiment of the present invention. 4A and 4B , the same components are associated with the same reference numerals. That is, reference numeral 40 denotes a silicon substrate, reference numeral 41 denotes an active region, reference numeral 42 denotes an inactive region, reference numeral 43 denotes a lower structure, reference numeral 44 denotes a gate electrode, reference numeral 45 denotes a polysilicon film, and reference numeral 46 denotes a lower part. an electrode, numeral 47 is a bus Ffa layer, reference numeral 48 is a SrTiO 3 dielectric thin film, reference numeral 50 is an upper electrode, and reference numeral 52 denote respectively a capacitor.
[0045]
FIG. 4A is a cross-sectional view schematically showing the structure of a single transistor type memory device using the capacitor of the first embodiment according to the present invention. FIG. 4B is a cross-sectional view schematically showing the structure of the 1Tr-1C type memory element using the capacitor of the second embodiment according to the present invention.
[0046]
Although various embodiments of the memory element are shown in FIGS. 4A and 4B , it is needless to say that the present invention can be applied to other electronic devices using a dielectric thin film.
[0047]
Hereinafter, the present invention will be described in detail with reference to the following embodiments, but the present invention is not limited to the following embodiments.
[0048]
(First embodiment)
First, as a precursor for forming a buffer layer, a solution containing 0.1 M / Ti (i-OPr) 2 (tmhd) 2 using tetrahydrofuran (THF) as a solvent is used, and O 3 is used as an oxidizing agent. Monoatomic layer deposition was performed at 0 ° C. to form a TiO 2 buffer layer on the first Ru electrode. Then, at 400 ℃ Sr (methd) 2 and Ti a (i-OPr) 2 (tmhd ) 2 as a precursor on the buffer layer, using O 3 as an oxidizing agent, performs single atomic layer deposition, SrTiO 3 A dielectric thin film was formed. Then, a Ru electrode was formed on the SrTiO 3 dielectric thin film, thereby manufacturing the capacitor of the first embodiment (see FIG. 4A).
[0049]
(Second Embodiment)
An Al 2 O 3 buffer layer is formed on the Ru electrode by depositing an atomic layer at about 400 ° C. using Al (CH 3 ) 3 as a precursor for buffer layer formation and O 3 as an oxidant. Except for this, the capacitor of the second embodiment was manufactured in the same manner as the method of the second embodiment described above (see FIG. 4B).
[0050]
(Third embodiment)
After CO was adsorbed on the Ru electrode, it was treated at about 400 ° C. in a hydrogen gas atmosphere to generate lattice oxygen. Next, a SrTiO 3 dielectric thin film was formed in the same manner as in the first embodiment. Next, a Ru electrode was formed on the SrTiO 3 dielectric thin film to manufacture the capacitor of the third embodiment .
[0051]
FIG. 5 is a photograph taken by a transmission electron microscope (TEM) of a cross section of the SrTiO 3 thin film formed on the Ru thin film in the capacitor of the first embodiment according to the present invention. As shown in FIG. 5, first, a TiO 2 buffer layer is formed under the SrTiO 3 thin film, and a Ru electrode is disposed under the TiO 2 buffer layer. Moreover, it turns out that there is no obstacle by protrusion of Ru electrode.
[0052]
FIG. 6 is a transmission electron microscope (TEM) photograph of the cross section of the SrTiO 3 thin film formed on the Ru thin film in the capacitor of the second embodiment according to the present invention. As shown in FIG. 6, it can be seen that the use of the buffer layer did not cause an increase in protrusion or surface roughness due to oxidation of Ru even after the deposition of SrTiO 3 .
[0053]
7A and 7B are graphs showing the results of measuring the electrical characteristics of the capacitor manufactured according to the third embodiment of the present invention.
[0054]
FIG. 7A is a graph showing the relationship between the voltage and current density of a capacitor manufactured according to the third embodiment of the present invention. In FIG. 7A, a □-□ plot in the graph represents a change in current density when the voltage is changed from a negative (−) value to a positive (+) value. It represents a change in current density when the voltage is changed from a positive (+) value to a negative (−) value.
[0055]
As shown in FIG. 7A, it has been found that 10 −7 A / cm 2 is normally secured at 1 V, which is the DRAM standard.
[0056]
FIG. 7B is a graph showing the relationship between the bias voltage of the capacitor manufactured according to the third embodiment of the present invention and tox (the thickness of SiO 2 ). In FIG. 7B, the □-□ plot of the graph represents tox, and the ■-■ plot represents tan δ which is a dielectric loss factor. Here, tox can be expressed by the following mathematical formula.
[0057]
[Expression 1]
tox = thickness of SiO 2 = {(dielectric constant of SiO 2 × area of upper electrode)} / (capacitance of capacitor) (1)
[0058]
Here, the smaller the value of tox, the better the characteristics of the dielectric film. As shown in FIG. 7B, tox is 6.8 mm after vapor deposition, and it can be seen that the thickness of the dielectric film 7 mm required for a DRAM of 16 GB or higher is secured.
[0059]
【The invention's effect】
According to the present invention configured as described above, the following effects can be obtained. That is, according to the capacitor for a semiconductor device and the method for manufacturing the same according to the present invention and the electronic device using the capacitor, monoatomic layer deposition is performed using a strong oxidizing agent such as O 3 when forming the dielectric thin film. However, the oxidation of the Ru electrode as the lower electrode can be suppressed, and further the deformation of the Ru electrode and the deterioration of the characteristics of the dielectric thin film can be prevented. Therefore, the capacitor according to the present invention can secure dielectric characteristics having excellent electronic characteristics required in a highly integrated memory, and is useful for an electronic device element such as a DRAM.
[Brief description of the drawings]
FIG. 1 is a photograph showing a cross-sectional structure of a capacitor in which a SrTiO 3 thin film is formed on a Ru lower electrode using O 3 monoatomic layer deposition (ALD) according to the prior art.
FIG. 2 is a graph showing temperature dependence of the activity of Ru used in the capacitor shown in FIG. 1;
FIG. 3 is a drawing schematically showing a process of generating lattice oxygen when a Ru electrode is used in the method for manufacturing a capacitor for a semiconductor device according to the present invention.
FIG. 4A is a cross-sectional view schematically showing the structure of a single transistor type memory device using the capacitor according to the first embodiment of the present invention.
FIG. 4B is a cross-sectional view schematically showing the structure of a 1Tr-1C type memory device using the capacitor according to the second embodiment of the present invention.
FIG. 5 is a transmission electron microscope (TEM) photograph of a cross section of a SrTiO 3 thin film formed on a Ru thin film in the capacitor according to the first embodiment of the present invention.
FIG. 6 is a transmission electron microscope (TEM) photograph of a cross section of an SrTiO 3 thin film formed on an Ru thin film in the capacitor according to the second embodiment of the present invention.
FIG. 7A is a graph showing a relationship between voltage and current density of a capacitor manufactured according to the third embodiment of the present invention.
FIG. 7B is a graph showing a relationship between a bias voltage of a capacitor manufactured according to the third embodiment of the present invention and tox (a thickness of SiO 2 ).
[Explanation of symbols]
40 a silicon substrate 41 active region 42 inactive region 44 gate electrode 46 lower electrode 47 bar Ffa layer 48 SrTiO 3 dielectric thin film 50 upper electrode 52 capacitor

Claims (7)

（ａ−１）白金族元素で構成される下部電極の上に、バッファ層形成用の前駆体を用いて単原子層蒸着を行い、バッファ層を形成する段階と、
（ｂ−１）前記バッファ層の上に誘電体薄膜形成用の前駆体を用いて単原子層蒸着を行い、誘電体薄膜を形成する段階と、
（ｃ−１）前記誘電体薄膜の上に白金族元素で構成される上部電極を形成する段階と、
を備え、
前記誘電体薄膜形成用の前駆体は、Ｓｒ（ｔｍｄｈ） ２ 、Ｓｒ（ｍｅｔｈｄ） ２ 、ＴｉＯ（ｔｍｈｄ） ２ 及びＴｉ（ｉ−ＯＰｒ） ２ （ｔｍｈｄ） ２ からなる群から選ばれた少なくとも１種で構成されることを特徴とする半導体デバイス用のキャパシタの製造方法。(A-1) On the lower electrode composed of a platinum group element, performing a monoatomic layer deposition using a precursor for forming a buffer layer to form a buffer layer;
(B-1) performing monoatomic layer deposition on the buffer layer using a precursor for forming a dielectric thin film to form a dielectric thin film;
(C-1) forming an upper electrode composed of a platinum group element on the dielectric thin film;
Equipped with a,
The precursor for forming the dielectric thin film is at least one selected from the group consisting of Sr (tmdh) 2 , Sr (methd) 2 , TiO (tmhd) 2 and Ti (i-OPr) 2 (tmhd) 2. The manufacturing method of the capacitor for semiconductor devices characterized by comprising by these . 前記段階（ａ−１）において、バッファ層形成用の前駆体は、Ｔｉ（ｉ−ＯＰｒ）２（ｔｍｈｄ）２、Ａｌ（ＣＨ３）３またはＨｆ（ＯＢｕ）４からなる群から選ばれた少なくとも１種で構成されることを特徴とする請求項１に記載の半導体装置のキャパシタの製造方法。In the step (a-1), the precursor for forming the buffer layer is at least selected from the group consisting of Ti (i-OPr) 2 (tmhd) 2 , Al (CH 3 ) 3, or Hf (OBu) 4. The method of manufacturing a capacitor of a semiconductor device according to claim 1 , wherein the capacitor is configured of one type. 前記段階（ａ−１）において、単原子層蒸着の温度は、２００〜５００℃であることを特徴とする請求項１に記載の半導体デバイス用のキャパシタの製造方法。2. The method of manufacturing a capacitor for a semiconductor device according to claim 1 , wherein in the step (a-1), the temperature of monoatomic layer deposition is 200 to 500 ° C. 3. （ａ−２）白金族元素で構成される下部電極の上面に一酸化炭素ＣＯを吸着させる段階と、
（ｂ−２）前記下部電極を還元雰囲気下に設置し、格子酸素を生成する段階と、
（ｃ−２）前記格子酸素を用い、且つ、誘電体薄膜形成用の前駆体を用いて原子層蒸着を行い、誘電体薄膜を形成する段階と、
（ｄ−２）前記誘電体薄膜の上に白金族元素で構成される上部電極を形成する段階と、
を備えることを特徴とする半導体デバイス用のキャパシタの製造方法。(A-2) adsorbing carbon monoxide CO on the upper surface of the lower electrode composed of a platinum group element;
(B-2) installing the lower electrode in a reducing atmosphere to generate lattice oxygen;
(C-2) performing atomic layer deposition using the lattice oxygen and a precursor for forming a dielectric thin film to form a dielectric thin film;
(D-2) forming an upper electrode composed of a platinum group element on the dielectric thin film;
The manufacturing method of the capacitor for semiconductor devices characterized by the above-mentioned. 前記誘電体薄膜形成用の前駆体は、Ｓｒ（ｔｍｄｈ）２、Ｓｒ（ｍｅｔｈｄ）２、ＴｉＯ（ｔｍｈｄ）２及びＴｉ（ｉ−ＯＰｒ）２（ｔｍｈｄ）２からなる群から選ばれた少なくとも１種で構成されることを特徴とする請求項４に記載の半導体デバイス用のキャパシタの製造方法。The precursor for forming the dielectric thin film is at least one selected from the group consisting of Sr (tmdh) 2 , Sr (methd) 2 , TiO (tmhd) 2 and Ti (i-OPr) 2 (tmhd) 2. The method for manufacturing a capacitor for a semiconductor device according to claim 4 , comprising: 前記段階（ｂ−２）において、還元雰囲気下における処理温度は、１００〜５００℃であることを特徴とする請求項４に記載の半導体装置のキャパシタの製造方法。5. The method for manufacturing a capacitor of a semiconductor device according to claim 4 , wherein in the step (b-2), a processing temperature in a reducing atmosphere is 100 to 500 ° C. 5. 請求項１から６のいずれか１項に記載の製造方法によって製造された半導体デバイス用のキャパシタを用いて、ダイナミックランダムアクセスメモリ（ＤＲＡＭ）または不揮発性メモリ（ＦｅＲＡＭ）として構成したことを特徴とする電子デバイス。 A capacitor for a semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 6, and configured as a dynamic random access memory (DRAM) or a non-volatile memory (FeRAM). Electronic devices.
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