JP4096271B2 - Information processing device, information storage device, information processing method, and information processing program - Google Patents

Description

  The present invention relates to an information processing device such as a memory device that operates by supplying a required synchronous clock and other devices, an information storage device, an information processing method, and an information processing program, and is particularly suitable even when the frequency of the synchronous clock changes. The present invention relates to an information processing device, an information storage device, an information processing method, and an information processing program for realizing a simple signal processing operation.

  Electronic devices such as personal computers and PDAs (Personal Digital Assistance) have multiple LSIs (Large-Scale Integrated Circuits) as their system configuration, and synchronize clocks for input / output and signal processing of these LSI signals. What is being used is widely used. In general, the place where the synchronous operation is performed is configured such that the overall operation speed is determined in proportion to the frequency of the signal. As an element for performing such a synchronous operation, a CPU (Central Processing Unit), a memory, a north Examples include bridges.

  On the other hand, there is also known an example in which the operating frequency of the apparatus is variable instead of the constant operating frequency. For example, electronic devices such as personal computers, PDAs, and cellular phones have been devised to perform only necessary operations according to usage conditions. For example, the operating frequency is controlled to be low during standby or sleep mode. Accordingly, there are an increasing number of systems that achieve low-power consumption and realize high-speed arithmetic processing by increasing the operating frequency during a call or video signal processing (see, for example, Patent Document 1).

JP 2000-163965 A

  In such a system in which the operating frequency is variable, the region where the variable operating frequency is supplied as a clock is usually separated from the fixed frequency portion where the frequency should not be changed, and the operating frequency is changed. Even in such a case, it is configured such that no adverse effect appears in the region operating at a fixed frequency.

  However, in an information processing apparatus that uses the above-described variable operating frequency signal as a synchronization signal as it is, it is required that a stable operation is realized at a high frequency or a low frequency. In other words, when the operation is designed to guarantee operation even with a short clock interval and when the operation is performed at a low frequency, the signal processing performance is proportional to the decreased frequency. Although a simple reduction in operating speed can reduce the power consumption, it is difficult to say that the control is optimized and higher performance control is required.

  Therefore, in view of the above technical problems, the present invention provides an information processing apparatus, an information storage apparatus, and an information processing apparatus that can realize optimum signal processing without causing a decrease in performance even when a variable operating frequency is used. It is an object to provide a method and an information processing program.

One aspect of the present invention provides a clock signal whose frequency is variable, frequency control means for outputting frequency information indicating the frequency of the clock signal, and the clock signal output from the frequency control means is a control clock signal. supplied as comprising an information processing means for executing a plurality of information processing latency are different from each other, and a timing control means for calculating a waiting time against the one of the information processing on the basis of the frequency information, the timing control means The information processing apparatus is used for standby processing for the execution of one information processing in the information processing means .

The frequency information may be information indicating a frequency of a clock signal output from the frequency control means at the present time or after the present time.

  The frequency information may be information in which the frequency of the clock signal is coded.

It said timing control means, the frequency information that is addition processing signal period corresponding to the frequency indicated, it is possible to calculate the waiting time against the one of the information processing.

In another aspect of the present invention, an information processing means for executing a plurality of information processing with different waiting times supplied with a clock signal output with a variable frequency as a control clock signal, and a frequency indicating the frequency of the clock signal and a timing control means for calculating a waiting time against the one of the information processing on the basis of the information, the waiting process the waiting time calculated by said timing control means for executing one of said information processing in said information processing means It is the information processing apparatus used for .

The frequency information may be information indicating a frequency of a clock signal output at the present time or after the present time.

  The frequency information may be information in which the frequency of the clock signal is coded.

It said timing control means, the frequency information that is addition processing signal period corresponding to the frequency indicated, it is possible to calculate the waiting time against the one of the information processing.

One aspect of the present invention provides a clock signal having a variable frequency, frequency control means for outputting frequency information indicating the frequency of the clock signal, and information for a memory cell capable of storing information by accumulating charges. read or to write, against a plurality of different processing latency to each other, and information storage means for executing the clock signal as a control clock signal output from said frequency control means, into one of the processing on the basis of the frequency information A timing control means for calculating a waiting time , wherein the waiting time calculated by the timing control means is an information storage device used for a standby process for execution of one of the processes in the information storage means .

The frequency information may be information indicating a frequency of a clock signal output from the frequency control means at the present time or after the present time.

  The frequency information may be information in which the frequency of the clock signal is coded.

It said timing control means, the frequency information that is addition processing signal period corresponding to the frequency indicated, it is possible to calculate the waiting time against the one of the processing.

According to another aspect of the present invention, a plurality of processes with different waiting times related to reading or writing of information with respect to a memory cell capable of storing information by accumulating electric charges, and a clock signal output with a variable frequency as a control clock and information storing means for executing a signal, and a timing control means for calculating a waiting time against the one of the process based on the frequency information indicating the frequency of the clock signal, the waiting time calculated by said timing control means Is an information storage device used for standby processing for execution of one of the processes in the information storage means .

The frequency information may be information indicating a frequency of a clock signal output at the present time or after the present time.

  The frequency information may be information in which the frequency of the clock signal is coded.

It said timing control means, the frequency information that is addition processing signal period corresponding to the frequency indicated, it is possible to calculate the waiting time against the one of the processing.

One aspect of the present invention, a clock signal whose frequency is variable, and outputs the frequency information indicating the frequency of the clock signal, based on the frequency information is performed the clock signal as a control clock signal, Information processing including a step of calculating a waiting time for one of the plurality of information processings having different waiting times and performing a waiting process for execution of the one information processing using the calculated waiting time Is the method.

  The information processing includes processing related to reading or writing of the information with respect to a plurality of memory cells capable of storing information by accumulating charges, and an operation for extracting charges from a part of the memory cells to the amplifier, It is possible to include at least one of an input / output operation and an operation of accumulating charges from the amplifier to the memory cell.

According to another aspect of the present invention, based on frequency information indicating a frequency of a clock signal output with a variable frequency, the clock signal is executed as a control clock signal, and a plurality of information processing with different waiting times is performed. An information processing method including a step of calculating a waiting time for one of the information processings and performing a waiting process for execution of the one information processing using the calculated waiting time .

  The information processing includes processing related to reading or writing of the information with respect to a plurality of memory cells capable of storing information by accumulating charges, and an operation for extracting charges from a part of the memory cells to the amplifier, It is possible to include at least one of an input / output operation and an operation of accumulating charges from the amplifier to the memory cell.

One aspect of the present invention, a clock signal whose frequency is variable, and outputs the frequency information indicating the frequency of the clock signal, based on the frequency information is performed the clock signal as a control clock signal, Calculating a waiting time for one of the plurality of information processings having different waiting times, and performing a waiting process for execution of the one information processing using the calculated waiting time. It is a characteristic information processing program.

  The information processing includes processing related to reading or writing of the information with respect to a plurality of memory cells capable of storing information by accumulating charges, and an operation for extracting charges from a part of the memory cells to the amplifier, It is possible to include at least one of an input / output operation and an operation of accumulating charges from the amplifier to the memory cell.

According to another aspect of the present invention, based on frequency information indicating a frequency of a clock signal output with a variable frequency, the clock signal is executed as a control clock signal, and a plurality of information processing with different waiting times is performed. The information processing program includes a step of calculating a waiting time for one of the information processing, and performing a waiting process for the execution of the one information processing using the calculated waiting time .

  The information processing includes processing related to reading or writing of the information with respect to a plurality of memory cells capable of storing information by accumulating charges, and an operation for extracting charges from a part of the memory cells to the amplifier, It is possible to include at least one of an input / output operation and an operation of accumulating charges from the amplifier to the memory cell.

In one aspect of the present invention, a clock signal having a variable frequency and frequency information indicating the frequency of the clock signal are output , the clock signal is supplied as a control clock signal, and a plurality of pieces of information having different waiting times. processing is executed, the waiting time against the one of the information processing on the basis of the frequency information is calculated, the calculated wait time is used in the standby processing for execution of a processing.

In another aspect of the present invention, a clock signal output with a variable frequency is supplied as a control clock signal, a plurality of information processing with different waiting times is executed, and based on frequency information indicating the frequency of the clock signal wait against the one of the information processing Te is calculated, the calculated wait time is used in the standby processing for execution of a processing.

  According to the aspect of the present invention, the frequency information Infq is used for arithmetic processing such as time waiting calculation when the clock frequency changes. For this reason, extremely high-speed processing without extra waiting time will be realized.In other words, while realizing high-speed operation, the power consumption is conversely suppressed during periods such as standby and sleep modes. Will be able to. Therefore, when used in a PDA or personal computer, both high speed operation and low power consumption can be realized.

  An example of a memory device that is an information storage device as an example of the information processing device of the present invention will be described with reference to the drawings. The memory device according to the present embodiment mainly includes a memory 11 made of SDRAM (Synchronous Dynamic Random Access Memory), a memory controller 12 for controlling the memory 11, and a frequency control unit 13 that outputs frequency information Infq. .

  In the present embodiment, the memory 11 is a synchronous (synchronous) DRAM. When a read start address is first input, data can be continuously output in synchronization with the clock signal CLKv. High-speed data transmission is possible. In particular, in the present embodiment, the clock signal CLKv is variable, and by way of example, a clock frequency of 10 MHz, 33 MHz, 50 MHz, 100 MHz, 133 MHz, or the like is used and the information processing apparatus is mounted. It is comprised so that it may switch according to the state of an electronic device. The variable clock signal CLKv may be a so-called base clock that is an external clock of the CPU of the system, or may be a clock signal generated exclusively for controlling the memory 11. The variable clock signal CLKv is transmitted from the frequency control unit 13, but may be directly supplied from another frequency generation circuit system. Although a specific structure example of the memory 11 will be described later, the memory 11 and the memory controller 12 may be configured as separate chips. The memory 11 is a memory core and is the same as the memory controller 12. It may be provided in the chip. The memory 11 is supplied with such a variable clock signal CLKv, and is connected with a control signal Sig from the memory controller 12 and signal lines such as a row address, a column address, and data input / output (not shown). In this embodiment, the memory 11 is a synchronous DRAM, but it may be a normal DRAM, a first page DRAM, an EDO DRAM (Extended Data Out Dynamic Random Access Memory), etc., and the SDRAM is a DDR SDRAM (Double SDRAM). It may be a Date Rate Synchronous Dynamic Random Access Memory) or a memory such as DRDRAM (Direct Rambus Dynamic Random Access Memory). Furthermore, the memory 11 is not limited to DRAM, but may be SRAM (Static Random Access Memory), ROM (Read-Only Memory), flash memory, or the like. Further, in this specification, the memory device or information processing device including a memory may be a microcomputer having a memory unit or other signal processing chip.

  The memory controller 12 is a device for outputting a control signal Sig for controlling the operation of the memory 11, and the control signal Sig is CS (chip select), RAS (row address strobe), CAS (column address strobe), WE. (Write enable), CKE, and other signals are generic names and mean a signal group composed of a plurality of signals. The memory controller 12 is also supplied with a variable clock signal CLKv so that the output timing of the control signal Sig is synchronized. Further, in the memory controller 12, the frequency information Infq from the frequency control unit 13 is input, and the frequency information Infq includes frequency information regarding the clock signal CLKv. The frequency information Infq can be information on the current clock signal CLKv, but it may be frequency information Infq on the clock signal CLKv on the time axis. As an example, the frequency information Infq is coded, and a coding example will be described later. Further, the frequency information Infq may be variable clock signal CLKv itself or linearly converted information thereof. In the memory controller 12, calculation processing is performed using the input frequency information Infq, and optimal control of the memory 11 reflecting calculation results as described later is performed.

  The frequency control unit 13 is a circuit unit that outputs frequency information Infq. In the present embodiment, the frequency control unit 13 is configured to output a variable clock signal CLKv from the frequency control unit 13. The frequency control unit 13 is configured to change the frequency of the clock signal CLKv to be generated in accordance with a command from the CPU or the like. For example, the operation clock is lowered at the time of soft-off, standby, sleep mode, etc. It becomes possible to reduce power consumption. The frequency control unit 13 may be configured to be the same chip as the memory 11 or the memory controller 12 or may be a separate chip.

  FIG. 2 is a time chart for explaining the operation of the memory device according to the present embodiment. FIG. 2A is a diagram showing a read (read) operation of the memory 11 at a fixed frequency of 100 MHz. (B) of FIG. 2 is a diagram showing the operation of the comparative example, and is a diagram showing a process in the case of operating at a timing fixed to a variable frequency as it is, and (C) of FIG. 2 is a control method for calculating from frequency information It is an example. In FIGS. 2A to 2C, the signal CLK is a fixed clock signal, the signal CLKv is a variable clock signal, “A” is an activation operation, and “R” is a command signal portion. The read operation and “P” indicate the command issue period of the precharge operation.

  In SDRAM control, normally, Tras (RAS activation time), which is the time from the activation operation to the precharge operation, Trcd (RAS-CAS delay time), which is the time from the activation operation to the read operation, and activation from the precharge operation There are parameters such as Trp (precharge time) that is the time until the operation, and it is necessary to wait for at least these times before issuing a command. If it does not wait, the operation is not guaranteed.

  Here, before describing the operation according to the clock signal of variable frequency in this embodiment, the case of a fixed frequency where the frequency does not change will be briefly described. When the frequency of the operation clock is fixed to a predetermined frequency, Optimization is relatively easy. That is, as shown in FIG. 2A, when operating at a fixed frequency of 100 MHz, the SDRAM time parameters {Tras, Trcd, Trp} are {40 ns, 20 ns, 20 ns}, and the CAS latency is 2. In some cases, the RAS activation time Tras is 4 clocks, the RAS-CAS delay time Trcd is 2 clocks, and the precharge time Trp is 2 clocks, and the operation at a fixed frequency of 100 MHz is optimally controlled. .

  However, if the frequency of the operating clock is variable and the fixed frequency control method is used as it is, an extra time wait occurs in the low frequency part where the period of one clock is long, and this is an overall performance problem. Bring about a decline. That is, as shown in FIG. 2B, the RAS activation time Tras that starts at the rising edge of the command issue clock of the first activation operation (“A”) remains a period of 4 clocks. In (B), since the frequency of the first two clocks is a half clock frequency of 50 MHz, the RAS activation time Tras that is just two clocks of 100 MHz is long, although the waiting time originally required has passed. End up. The RAS activation time Tras of the next activation operation (“A”) becomes a RAS activation time Tras that is longer by 3 clocks of 100 MHz. Similarly, the RAS-CAS delay time Trcd and the precharge time Trp also cause extra waiting time depending on the change of the operation clock frequency.

  Therefore, in the memory device of the present embodiment, even when the frequency of the operation clock changes, the frequency information Infq is used to perform an accurate calculation process, and as shown in FIG. Corresponding signal processing is performed. That is, the frequency information Infq is transmitted as data from the frequency controller 13 to the memory controller 12 as shown in FIG. 1, and the memory controller 12 can calculate the cycle of the clock signal. Therefore, when the command issue timing is excessively waited, a command is issued from the memory controller 12 to the memory 13 before that, and high-speed processing without waste is realized. Referring to FIG. 2C, the memory controller 12 reads information indicating that the frequency information Infq is 50 MHz following the end of issuing the command for the activation operation (“A”) from the frequency control unit 13 (“ R ") command is issued at least one clock prior to the timing of command issuance, and the next operation is continuously performed following the clock for issuing the command for the activation operation (" A ") based on the frequency information Infq. Read command ("R") command issue timing follows. If the memory device of this embodiment is not used, the timing of issuing a read operation ("R") command is separated by one clock, as shown in FIGS. In the case of the memory device of the present embodiment, the command for the activation operation (“A”) and the command for the next read operation (“R”) are issued by the frequency information Infq from the frequency control unit 13. It has already been recognized by the memory controller 12 that the necessary operation is ensured even if the timing is continuous. Therefore, continuous command issuance is performed to optimally control the memory 11, and an extra waiting time can be omitted to increase the overall speed.

The memory controller has at least a wait time required based on the frequency information Infq from the end of issuing the command for the activation operation ("A") to the end of issuing the command for the next read operation ("R"). When the CAS delay time Trcd is satisfied, a read operation ("R") command may be issued. Alternatively, assuming that the frequency during which the command for the read operation ("R") is issued is 100 MHz, RAS-, which is the required wait time, based on the frequency information Infq until the command for the read operation ("R") is issued. When the CAS delay time Trcd is satisfied, a read operation ("R") command may be issued. Similarly, the memory controller fulfills the necessary wait time based on the frequency information Infq, and activates ("A") command and precharge so that the precharge time Trp and RAS activation time Tras are shortened optimally. Issue operation ("P") command.

  Here, the fact that the memory controller 12 has already recognized that the necessary operation is ensured will be further described. In FIG. 2C, the second clock is recognized as 50 MHz by the frequency information Infq, and the cycle is 20 ns. To be calculated. Here, it can be seen that the RAS-CAS delay time Trcd is 20 ns in this SDRAM, and is secured if the clock period is 20 ns. Therefore, the memory controller 12 performs control using the issue operation command ("A") command and the next read operation command ("R") as a continuous clock, and an extra waiting time is issued by issuing this continuous command. The overall speed-up is realized.

  Next, the frequency information Infq will be described in more detail with reference to FIGS. As an example, the frequency information Infq can be a data bit indicating the frequency of the variable clock signal CLKv. The frequency information Infq may indicate the current frequency of the operation clock signal CLKv as shown in FIG. 3A, or the frequency information Infq of the operation clock signal CLKv as shown in FIG. The frequency of the next clock may be indexed prior to the change in frequency. Although not shown in the figure, the signal may be a signal indicating only the frequency change point, and the future operation clock signal CLKv is not limited to that of the next clock, but a frequency after a predetermined number of multiple clocks. May be used as an index.

  As a method of indexing the clock frequency, information coded as frequency information Infq can be used and decoded. Although FIG. 4 shows two types of encoding methods in a table format, the encoding method is not limited to these methods, and other encoding methods may be used. The encoding method in FIG. 4A is an example in which 2-bit data is allocated in accordance with the frequency of the variable clock signal CLKv. In this example, {00} is assigned when the frequency of the clock signal CLKv is 10 MHz, {01} is assigned when the frequency is 33 MHz, {10} is assigned when the frequency is 50 MHz, and {00} when the frequency is 100 MHz. 11} is assigned. In this method, even if the frequency changes 10 times, for example, even when the frequency of the clock signal changes from 10 MHz to 100 MHz, the data length remains 2 bits, and the decoding process and circuit configuration are not complicated. Can be processed.

  The encoding method in FIG. 4B is an example in which data is allocated in accordance with the reciprocal of the frequency of the variable clock signal CLKv. The reciprocal of the frequency of the clock signal CLKv corresponds to the period of one clock at each frequency. In this example, {10} is assigned when the frequency of the clock signal CLKv is 10 MHz, {3} is assigned when the frequency is 33 MHz, {2} is assigned when the frequency is 50 MHz, and {10} when the frequency is 100 MHz. 1} is assigned. In these data, since the value represented by the data corresponds to a cycle of one clock, a waiting time can be formed by simple multiplication. That is, when the frequency of the clock signal CLKv is 10 MHz, 33 MHz, 50 MHz, and 100 MHz, the clock period is 100 ns, 30 ns, 20 ns, and 10 ns, and these can be easily calculated by multiplying the previous data value by 10 ns. Become.

  Next, the memory device of the present embodiment will be described in more detail with reference to FIGS. FIG. 5 shows a memory controller 30 and a memory unit 31. In this embodiment, frequency information Infq is input to the memory controller 30, and optimization is performed even when the frequency of the operation clock signal changes. Perform the specified action.

  First, the memory controller 30 receives the frequency information Infq from the frequency controller as described above, and issues a command at a predetermined timing. FIG. 6 is an example of a correspondence table between signals and commands, and bar symbols are omitted for simplicity. When the CS (chip select) signal becomes “L” (low level), the memory unit 31 is selected. The commands for the activation operation “A”, read operation “R”, and precharge operation “P” as described above are formed by a combination of RAS (row address strobe), CAS (column address strobe), and WE (write enable). The Specifically, a command for the activation operation is composed of a combination of the RAS signal at the “L” level, the CAS signal at the “H” level, and the WE signal at the “H” level, the RAS signal is at the “H” level, and the CAS signal is A combination of the "L" level and the WE signal is at the "H" level constitutes a read (read) operation command. The RAS signal is at the "H" level, the CAS signal is at the "L" level, and the WE signal is at the "L" level. The command for the write (write) operation is composed of the combination, and the command for the precharge operation is composed of the combination of the RAS signal at the “L” level, the CAS signal at the “H” level, and the WE signal at the “L” level. Therefore, for example, as described above, when the frequency of the clock signal CLKv changes, as in the second clock in FIG. 2C, the command issuance for the read operation from the issuance of the command for the activation operation. If the RAS signal is "L" level and the CAS signal is "H" level, the RAS signal is shifted to "H" level and the CAS signal is shifted to "L" level. This level shift is performed based on the calculation result based on the frequency information Infq from the frequency control unit.

  The memory unit 31 includes a memory bank 55, a sense amplifier 56 that amplifies the charged electric charge of each cell, and other peripheral circuits. The memory bank 55 actually stores data and includes a plurality of cells 55a. Each cell 55a has a capacitor-like configuration, and the charge state of each cell 55a is set by setting each cell 55a to a charged state or not being charged according to the data. Data is stored in accordance with the pattern. In this case, 8 × 8 cells 55a are provided for one memory bank 55, but it goes without saying that the number of cells 55a is other than this. Also good.

  A group of cells 55a for each row on the memory bank 55 is particularly called a page 55b. Further, when a refresh signal is input to the memory bank 55 from a refresh timing generator (not shown) of the refresh control circuit or a read signal is input from the row selector 53, a page corresponding to the row to which the signal is input. The charge of each cell 55a is transferred to the sense amplifier 56 in units of 55b. In FIG. 3, numbers (0 to 7) displayed in the vertical and horizontal directions of the memory bank 55 are the row indicating the vertical position of each cell 55a of the memory bank 55 and the example indicating the horizontal position, respectively. The number is shown.

  When the data of the cell 55a of the page 55b designated by the row selector 53 is transferred, the sense amplifier 56 receives it, further amplifies it to a predetermined potential, and transfers it again to the original page 55b. At this time, when a read signal is input from the column selector 57 while the charge is accumulated, the sense amplifier 56 reads the specified column data and outputs it to the output amplifier 58. To do.

  In FIG. 5, the sense amplifier 56 is configured to amplify only the charge of the cell 55a for one page 55b. For this reason, since only one page of the refresh process or the read process can be processed, the refresh signal generated from the self-refresh timing generator or the read signal generated from the row selector 53 is These processes are controlled by a CPU (not shown) so as to be generated at the timing to be executed for any row. In addition, a plurality of sense amplifiers 56 may be provided for a plurality of pages (rows) so that a refresh process or a read process can be simultaneously performed in parallel.

  When the column address latch 52 receives the CAS signal input from the memory controller 30, the column address latch 52 turns on the operation state and outputs the column information of the address indicating the position of the cell 55 a on the memory bank 55 to the column selector 57. The column selector 57 outputs a data read signal on the sense-up 56 corresponding to the column input from the column address latch 52 to the sense-up 56 and causes the output amplifier 58 to read it. The output amplifier 58 further doubles the input charge and outputs data to the CPU via the memory controller 30.

  Next, an operation in which the memory controller 30 reads data from the cell 55a of the memory bank 55 according to a command from the CPU will be described. For example, when the memory controller 30 tries to read the data in the cell 55a in the sixth row and the fourth row of the DRAM memory bank 55 in response to a command from the CPU, the CPU sends the memory controller 30 to the sixth row and the fourth column. Command to read the data in the cell 55a. When the control signal generator of the memory controller 30 receives this command, it outputs a RAS signal to the row address latch 51 and then outputs a corresponding address signal to the row address latch 51 and the column address latch 52. When the row address latch 51 receives the RAS signal from the control signal generator, the row address latch 51 turns on the operation, and outputs the row information of the address information received subsequently to the row selector 53. Therefore, in this case, the information “sixth row” is output to the row selector 53.

  Based on the row information input from the row address latch 51, the row selector 53 outputs a read signal for transferring the charge of the cell 55a of the page 55b corresponding to the row to the sense amplifier 56. Then, in this case, the charge of the cell 55a of the page 55b in the sixth row surrounded by the solid line in the drawing on the memory bank 55 is output to the sense amplifier 56. The sense amplifier 56 amplifies the transferred charge amount to a predetermined value.

  At this time, the control signal generator outputs a CAS signal to the column address latch 52 and outputs an address signal to the row address latch 51 and the column address latch 52. When the column address latch 52 receives the CAS signal from the control signal generation unit, the column address latch 52 turns on the operation and outputs the column information of the address information received subsequently to the column selector 53. Therefore, in this case, information “fourth column” is output to the column selector 57.

  The column selector 57 outputs a read signal for transferring the charge amplified by the sense amplifier 56 corresponding to the column to the output amplifier 58 based on the input column information. That is, in this case, the sense amplifier 56 outputs the charge of the cell 55a in the fourth column surrounded by the solid line in the drawing to the output amplifier 58 based on this read signal. The output amplifier 58 amplifies the transferred charge amount to a predetermined value necessary for transfer, and then outputs data to the CPU via the memory controller 30. After this, the sense amplifier 56 returns the amplified charge of the page 55b in the sixth row to the original cell 55a on the memory bank 55 again. Therefore, the eight cells 55a on the page 55b from which data has been read (in this case, the sixth row) have the charge amount returned to the original state (full charge state).

  Next, an example of a PDA (Personal Digital Assistance) equipped with the memory device of the present invention will be described with reference to FIG. The PDA has a PDA core unit 60 connected to a liquid crystal display unit or a touch panel (not shown). The PDA core unit 60 is provided with a CPU 61 and a coprocessor 62 for performing a required information processing procedure. Yes. The CPU 61 is connected to a bus line 66, and via this bus line 66, a bus bridge 67 serving as a connection to a low-speed circuit unit, a graphic engine 63 that realizes high-speed drawing, and a camera that captures an image. A camera interface 65 for connection, an LCD (Liquid Crystal Display) controller 64 that transmits and receives signals to the liquid crystal display unit, and the like are connected.

  The bus bridge 67 is connected to a circuit such as a USB (Universal Serial Bus) controller 81, an I / O bus 82 for I / O, a touch panel interface 83, an interface 84 such as a keyboard, jog dial, and light emitting diode, and further a clock signal. A frequency controller 76 that outputs CLKv and its frequency information Infq is also connected to the bus bridge 67.

  An embedded DRAM (eDRAM) 71 and a DRAM controller 72, which are information storage devices, are connected to the bus line 66, and an external memory controller 73 is also connected. The DRAM controller 72 is a circuit unit that sends a control signal to the embedded DRAM 71. In particular, in the present embodiment, for example, the frequency information Infq of the clock signal CLKv that is variable is supplied from the frequency control unit 76. The DRAM controller 72 performs arithmetic processing such as decoding using the frequency information Infq, and performs optimum processing of the embedded DRAM 71 even when the frequency of the clock signal CLKv changes. In the memory system 41 including the embedded DRAM 71 and the DRAM controller 72, when the frequency of the clock signal CLKv is changed, high-speed processing can be performed without extra waiting time by processing according to the frequency information Infq.

  Further, not only the memory system 41 but also the external memory controller 73 can be supplied with variable frequency information Infq of the clock signal CLKv. The external memory controller 73 is a circuit that sends control signals to the ROM 74 and the SDRAM 75 connected via the external memory bus. This external memory controller 73 also uses the frequency information Infq to perform arithmetic processing such as decoding, and when the frequency of the clock signal CLKv changes, optimal processing is performed with no extra waiting time in the ROM 74 or SDRAM 75. A memory system is configured by the controller unit 42 including the external memory controller 73 and the memory unit 43 including the ROM 74 and the SDRAM 75, and high-speed processing is realized in the same manner as the memory system 41 described above. In the above configuration example, both the DRAM controller 72 and the external memory controller 73 perform high-speed processing that eliminates an extra waiting time by using the frequency information Infq. The speed information may be increased using the frequency information Infq. Further, the ROM 74 and the SDRAM 75 are only examples as memories connected to the external memory controller 73, and may be other memories, other signal processing elements, or the like. Further, the frequency information Infq supplied to the external memory controller 73 and the DRAM controller 72 may be the same, and different frequency information Infq may be used when different clock signals are used.

  Next, an information processing method in the memory device according to the present embodiment will be described with reference to FIGS. Such an information processing method shows an example of the hardware operation of the memory controller, for example, and further, for example, when the information processing apparatus of the present invention is in the form of a microcomputer or the like, the required medium format It is also possible to read and execute the program supplied in (1) into a predetermined controller.

  First, before explaining the flow of FIG. 8 which is the main program flow, the flow of the subroutine # 1 of FIG. 9 will be explained. After subroutine # 1 is started, it is determined in step S21 whether or not the corresponding restriction has already been satisfied. The applicable limit is, for example, a limit that depends on the performance of the memory, but if the SDRAM time parameters {Tras, Trcd, Trp} are {40ns, 20ns, 20ns}, the command is issued. It is determined whether such time has already passed. If the corresponding restriction has already been satisfied (YES), the subroutine # 1 returns to the program routine of FIG.

  In step S21, when the corresponding restriction has not been satisfied (NO), the process proceeds to step S22 and the waiting time register is reset. After the waiting time register is reset, in step S23, for example, the value of the period of the next clock frequency state or a value proportional thereto is added to the register value. Here, frequency information Infq is used for the addition processing. By this addition process, a waiting time register reflecting the frequency state of the next clock is formed, and it is determined in the next step S24 whether or not the value of the waiting time register satisfies the waiting time for command issuance. . If the value of the waiting time register satisfies the waiting time for issuing a command in step S24 (YES), the process returns from subroutine # 1 to the program routine of FIG. 8 in the same manner as in step S21 described above. When the value of the waiting time register does not satisfy the waiting time for issuing the command (NO) in step S24, the process proceeds to step S25 and waits for one clock. After waiting for this one clock, the process returns to step S23, and the same processing is performed again by adding, for example, the value of the period of the current frequency state or a value proportional to the value to the register.

  In this way, each procedure of subroutine # 1 in FIG. 9 is compared with the time parameter which is the limit of the memory to be controlled, and in the state where the limit is satisfied, the signal processing proceeds without waiting for the next clock. It will be. Therefore, high-speed processing without extra waiting time is possible. In the process in step S23, the period value of the current frequency state or a numerical value proportional thereto is added, and the frequency information Infq is effectively used for the addition process.

  FIG. 8 is a diagram showing the main program flow in the controller. Assume that the controller receives a request from the CPU after the program starts (step S11). Then, in step S12, the next read or write address and the current state of the corresponding sense amplifier in the DRAM are checked, and a jump is made to start a different process according to the result.

  If data of another row address is stored in the sense amplifier in step S12, the process proceeds to step S13, and the process related to the RAS activation time Tras is advanced. For the processing related to the RAS activation time Tras, subroutine # 1 shown in FIG. 9 is used. Basically, the subroutine # 1 in FIG. 9 is a routine for waiting for time, and when the waiting for the required time is completed, the process proceeds to step S14 and issues a precharge command. On the DRAM side, a precharge command is received, and data existing in the sense amplifier is charged to each predetermined memory cell.

  After issuing the precharge command, the process proceeds to step S15, and the process related to the precharge time Trp is advanced. The subroutine # 1 shown in FIG. 9 is also used for the processing relating to the precharge time Trp. Similarly, subroutine # 1 is a time waiting routine, and when the time waiting for the required time is completed, the process proceeds to step S16 and issues an activation command. On the DRAM side, in response to an activation command, data of each memory cell corresponding to a predetermined address is read and amplified by a sense amplifier.

  After issuing this activation command, the process proceeds to step S17, and the processing related to the RAS-CAS delay time Trcd is advanced. The subroutine # 1 shown in FIG. 9 is also used for the processing related to the RAS-CAS delay time Trcd. Since the subroutine # 1 is a routine for waiting for time, the process proceeds to step S18 when the waiting for the required time is completed, and a read or write command is issued. On the DRAM side, a read or write command is received, and data of each memory cell corresponding to a predetermined address is read from the node of the sense amplifier or written to the node of the sense amplifier. This signal is read or written. Subsequently, the process proceeds to step S19 to enter a standby state for the next request.

  If no data is stored in the sense amplifier in step S12, the precharge operation is not necessary. Therefore, step S13 is skipped, and issuance of precharge (step S14) is also omitted. If no data is stored in the sense amplifier, the process proceeds from step S12 to step S15, from which the processing relating to the precharge time Trp and the processing relating to the RAS-CAS delay time Trcd are subroutines for waiting for time as described above. Each one is advanced using 1. Finally, the process proceeds to step S19 to enter a standby state for the next request, as in the case where data of another row address is stored in the sense amplifier in step S12.

  Finally, if the row address of the data stored in the sense amplifier in step S12 matches the row address of the data related to the read or write operation, not only the precharge operation but also the activation operation is not necessary. Therefore, steps S13 to S16 are skipped, and the issuance of precharge (step S14) and the issuance of activation (step S16) are also omitted. Accordingly, the process proceeds from step S12 to step S17, and the processing related to the RAS-CAS delay time Trcd is advanced using subroutine # 1 which is a time-waiting routine. Note that finally proceeding to step S19 to enter a standby state for the next request is the same as when another row address data is stored in the sense amplifier in step S12.

  As described above, in the information processing apparatus according to the present embodiment, the address for reading or writing is compared with the address of the data remaining in the sense amplifier, and if they match, the data is used as it is. Thus, high-speed reading and writing are realized. In addition, the time waiting program shown in FIG. 9 is used for command issue timing control, and the frequency information Infq is used for the calculation of the time waiting. Will be realized. In other words, while realizing high-speed operation, it operates reliably even with a slow clock during periods such as standby or sleep mode, and conversely, it can sufficiently reduce power consumption as a whole. It will be possible. The series of processes described above can be executed by hardware, but can also be executed by software.

  In the above-described embodiment, the description has been given mainly assuming that the controller of the storage element such as the memory is provided with a mechanism for reading the frequency information Infq and adjusting the control. It may be a case where a variable clock is supplied to a processing element or circuit, etc., and a circuit that performs information processing optimized by calculation of necessary waiting time by calculating the frequency information of the variable clock signal It may be.

  In the above-described embodiment, processing such as calculation of the waiting time is performed based on the frequency state of the next clock. However, as shown in FIG. In such a case, the calculation may be performed in advance. That is, as shown in FIG. 10A, when the frequency information (for example, 20 ns) of the (n + 2) th clock is obtained at the time of the nth clock, the frequency information of the (n + 2) th clock. Can be calculated using. Further, in the flowcharts of FIGS. 8 and 9 described above, whether or not the next clock is available is determined at the previous clock using the current frequency information. Whether or not the clock (n + 2) is available may be determined in advance using the frequency information for the next clock (n + 1) when the clock is two clocks ahead. For example, as shown in FIG. 10B, when Tras = 40 ns, whether or not this period is satisfied is determined by using the frequency information for the next clock (n + 1) at the time of the previous clock (n It is also possible to make a determination in advance at the second clock). Further, whether or not the next clock can be used may be determined in advance using frequency information for the next clock. Furthermore, in the case where (m-1) (m is a natural number) a request ahead of a clock can be received in advance and frequency information of (m-1) a clock ahead can be obtained in advance, a few clocks before You may make it judge.

  Furthermore, in the above-described embodiment, the configuration unit that acquires the frequency information Infq has been described as the frequency control unit. You may make it do. In addition, an electronic device in which this embodiment is mounted is not limited to a PDA or a personal computer, but is a printer, a facsimile, a peripheral device for a personal computer, a telephone, a television receiver, an image display device, a communication device, a mobile phone, a camera, Radio, audio video equipment, electric fan, refrigerator, hair dryer, iron, pot, vacuum cleaner, rice cooker, electromagnetic cooker, lighting equipment, toys such as game consoles and radio controlled cars, electric tools, medical equipment, measuring equipment, on-vehicle installation Equipment, office equipment, health and beauty equipment, electronically controlled robots, clothing-type electronic equipment, various types of electric equipment, vehicles for transportation such as vehicles, ships, aircraft, etc. It can be mounted on other electronic devices.

It is a block diagram which shows an example of the information processing apparatus of this invention. It is a time chart explaining the operation of the memory device, (A) is the operation in the case of a fixed clock, (B) is the operation in the case of operating at a fixed timing to a signal of a variable clock frequency, (C) is It is each a time chart of the operation | movement in the case of calculating from frequency information. It is a time chart which shows the example of frequency information, (A) is a time chart in case frequency information shows the frequency of the present operation clock signal CLKv, (B) is frequency information of the frequency of the operation clock signal CLKv. It is a time chart when indexing the frequency of the next clock prior to the change. It is a table which shows the example of the encoding method of frequency information, Comprising: (A) is an example indexed by 2 bits, (B) is an example using the data of a value proportional to a period. FIG. 2 is a block diagram when a memory controller and SDRAM are used as an example of the information processing apparatus of the present invention. 6 is a table showing an example of a correspondence table between signals and commands of the SDRAM of FIG. 5. 1 is a block diagram illustrating an example in which a memory controller and a memory are incorporated in a PDA as an example of an information processing apparatus of the present invention. FIG. 5 is a flowchart for processing while looking at the coincidence of addresses related to data of a sense amplifier in an SDRAM as an example of the information processing method of the present invention. As an example of the information processing method of the present invention, it is a flowchart showing an example of a subroutine in the case of performing waiting time calculation processing based on frequency information. It is a time chart which shows the example of the other information processing method in an example of the information processing apparatus of this invention.

Explanation of symbols

  11 memory, 12 memory controller, 13 frequency controller, 30 memory controller, 31 memory unit, 61 CPU, 66 bus line, 71 embedded DRAM, 72 DRAM controller, 73 external memory controller, 74 ROM, 75 SDRAM, 76 frequency controller , Infq frequency information, CLKv variable clock signal

Claims (24)

A clock signal whose frequency is variable, and a frequency control means for outputting frequency information indicating the frequency of the clock signal;
The clock signal output from the frequency control means is supplied as a control clock signal, and information processing means for executing a plurality of information processing with different waiting times;
And a timing control means for calculating a waiting time against the one of the information processing on the basis of the frequency information,
An information processing apparatus in which the waiting time calculated by the timing control means is used for standby processing for execution of one information processing in the information processing means . The information processing apparatus according to claim 1, wherein the frequency information is information indicating a frequency of a clock signal output from the frequency control unit at the present time or after the present time. The information processing apparatus according to claim 1, wherein the frequency information is information in which a frequency of the clock signal is coded. It said timing control means, the frequency information that is addition processing signal period corresponding to the frequency indicated, the information processing apparatus according to claim 1 for calculating the waiting time against the one of the information processing. An information processing means for supplying a clock signal output with a variable frequency as a control clock signal and executing a plurality of information processing with different waiting times;
And a timing control means for calculating a waiting time against the one of the information processing on the basis of the frequency information indicating the frequency of said clock signal,
An information processing apparatus in which the waiting time calculated by the timing control means is used for standby processing for execution of one information processing in the information processing means . The information processing apparatus according to claim 5, wherein the frequency information is information indicating a frequency of a clock signal output at the present time or after the present time. The information processing apparatus according to claim 5, wherein the frequency information is information in which a frequency of the clock signal is coded. It said timing control means, the frequency information that is addition processing signal period corresponding to the frequency indicated, the information processing apparatus according to claim 5 for calculating a waiting time against the one of the information processing. A clock signal whose frequency is variable, and a frequency control means for outputting frequency information indicating the frequency of the clock signal;
Information storage for executing a plurality of processes with different waiting times on reading or writing of information with respect to a memory cell capable of storing information by accumulating electric charges, using the clock signal output from the frequency control means as a control clock signal Means,
And a timing control means for calculating a waiting time against the one of the processing based on the frequency information,
An information storage device in which the waiting time calculated by the timing control means is used for standby processing for execution of one of the processes in the information storage means. The information storage device according to claim 9, wherein the frequency information is information indicating a frequency of a clock signal output from the frequency control unit at the present time or after the present time. The information storage device according to claim 9, wherein the frequency information is information in which a frequency of the clock signal is coded. It said timing control means, the frequency information that is addition processing signal period corresponding to the frequency indicated, the information storage device according to claim 9 for calculating a waiting time against the one of the processing. Information storage means for executing a plurality of processes with different waiting times for reading or writing information to / from a memory cell capable of storing information by accumulating electric charges, using a clock signal output with a variable frequency as a control clock signal ; ,
And a timing control means for calculating a waiting time against the one of the process based on the frequency information indicating the frequency of said clock signal,
An information storage device in which the waiting time calculated by the timing control means is used for standby processing for execution of one of the processes in the information storage means. The information storage device according to claim 13, wherein the frequency information is information indicating a frequency of a clock signal output at the present time or after the present time. The information storage device according to claim 13, wherein the frequency information is information in which a frequency of the clock signal is coded. It said timing control means, the frequency information that is addition processing signal period corresponding to the frequency indicated, the information storage device according to claim 13 for calculating the waiting time against the one of the processing. A clock signal having a variable frequency, and output frequency information indicating the frequency of the clock signal ;
On the basis of the frequency information, the executed clock signal as a control clock signal, it calculates the waiting time for one of the information processing of the latency plurality of different information processing,
An information processing method including a step of performing standby processing for execution of one of the information processing using the calculated waiting time . The information processing includes processing related to reading or writing of the information with respect to a plurality of memory cells capable of storing information by accumulating charges, and an operation for extracting charges from a part of the memory cells to the amplifier, The information processing method according to claim 17, comprising at least one of an input / output operation and an operation of accumulating electric charge from the amplifier to the memory cell. Based on the frequency information indicating the frequency of the clock signal that is output with a variable frequency, the clock signal is executed as the control clock signal, and waiting for one of the plurality of information processing with different waiting times is performed. Calculate time,
An information processing method including a step of performing standby processing for execution of one of the information processing using the calculated waiting time . The information processing includes processing related to reading or writing of the information with respect to a plurality of memory cells capable of storing information by accumulating charges, and an operation for extracting charges from a part of the memory cells to the amplifier, The information processing method according to claim 19, comprising at least one of an input / output operation and an operation of accumulating electric charge from the amplifier to the memory cell. A clock signal having a variable frequency, and output frequency information indicating the frequency of the clock signal ;
On the basis of the frequency information, the executed clock signal as a control clock signal, it calculates the waiting time for one of the information processing of the latency plurality of different information processing,
An information processing program comprising a step of performing standby processing for execution of one of the information processing using the calculated waiting time . The information processing includes processing related to reading or writing of the information with respect to a plurality of memory cells capable of storing information by accumulating charges, and an operation for extracting charges from a part of the memory cells to the amplifier, The information processing program according to claim 21, comprising at least one of an input / output operation and an operation of accumulating electric charge from the amplifier to the memory cell. Based on the frequency information indicating the frequency of the clock signal that is output with a variable frequency, the clock signal is executed as the control clock signal, and waiting for one of the plurality of information processing with different waiting times is performed. Calculate time,
An information processing program comprising a step of performing standby processing for execution of one of the information processing using the calculated waiting time . The information processing includes processing related to reading or writing of the information with respect to a plurality of memory cells capable of storing information by accumulating charges, and an operation for extracting charges from a part of the memory cells to the amplifier, The information processing program according to claim 23, comprising at least one of an input / output operation and an operation for accumulating electric charge from the amplifier to the memory cell.

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