JP4096722B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device used for a power converter or the like, and more particularly to a method for manufacturing a punch-through IGBT using an FZ wafer.
[0002]
[Prior art]
There is an IGBT as a semiconductor device used for a power conversion device or the like. The IGBT extends from the emitter region in a blocking mode (an off state in a turn-off process in which a predetermined voltage (voltage less than the rated voltage) is applied between the emitter and the collector and a voltage higher than the threshold voltage is not applied to the gate). A non-punch-through IGBT (hereinafter referred to as NPT-IGBT) with a thick drift layer so that the depletion layer does not extend to the collector layer, and a buffer layer provided between the drift layer and the collector layer so that the depletion layer is the collector There is a punch-through type IGBT (hereinafter referred to as PT-IGBT) that prevents extension to a layer. In general, the NPT-IGBT is manufactured using an inexpensive FZ wafer. On the other hand, an epitaxial wafer is used for PT-IGBT.
[0003]
FIG. 10 is a longitudinal sectional view showing a configuration of a conventional NPT-IGBT. In the NPT-IGBT, as shown in FIG. ^- P base region 12 and n on one main surface (hereinafter referred to as surface) side of drift layer 11 ⁺ An emitter region 13 is provided, and p is formed on the other main surface (hereinafter referred to as the back surface) side. ⁺ A collector layer 14 is provided. A gate electrode 16 is formed on the base region 12 via a gate oxide film 15 that is a gate insulating film, and an emitter electrode 18 is further formed thereon via an interlayer insulating film 17. A collector electrode 19 is formed on the surface of the collector layer 14.
[0004]
In the NPT-IGBT having the configuration shown in FIG. 10, when a positive voltage is applied to the collector electrode 19 and a positive voltage is applied to the gate electrode 16, a channel is formed on the IGBT surface, and an electron current flows in the drift layer 11. When electrons reach the collector layer 14, holes are injected into the drift layer 11. Thereby, the drift layer 11 is in a high injection state, and the resistance is drastically reduced, so that a low on-voltage is realized. However, in the NPT-IGBT having this configuration, since the drift layer 11 is sufficiently thick, the resistance is correspondingly increased. high As a result, the amount of voltage drop in the on state of the IGBT increases, and the amount of accumulated carriers in the drift layer 11 increases, resulting in a large loss at turn-off.
[0005]
FIG. 11 is a longitudinal sectional view showing a configuration of a conventional PT-IGBT. In PT-IGBT, as shown in FIG. ⁺ N on the collector layer 24 ⁺ Buffer layers 20 and n ^- A drift layer 21 is provided in order. These three layers (collector layer 24, buffer layer 20 and drift layer 21) grow a high-concentration n-type epitaxial layer on a high-concentration p-type silicon substrate, and further grow a low-concentration n-type epitaxial layer thereon. It is constituted by a wafer. n ^- The surface portion of the drift layer 21 has ap base region 22 and n ⁺ An emitter region 23 is provided. Further, a gate oxide film 25, a gate electrode 26, an interlayer insulating film 27, and an emitter electrode 28, which are gate insulating films, are formed thereon. A collector electrode 29 is formed on the back surface of the collector layer 24.
[0006]
In the PT-IGBT having the configuration shown in FIG. 11, since the extension of the depletion layer in the blocking mode is stopped by the buffer layer 20, a high breakdown voltage can be obtained even if the drift layer 21 is thin. For this reason, it has an advantage that the amount of voltage drop in the on state is small compared to the NPT-IGBT having the same breakdown voltage. However, since the amount of holes injected from the collector layer 24 at the time of forward conduction is extremely large, there is a disadvantage that the turn-off loss is large. Further, since the epitaxial wafer is expensive, there is a disadvantage that the cost is increased as compared with the NPT-IGBT.
Therefore, PT-IGBT using an FZ wafer (hereinafter referred to as I-type drift layer PT-IGBT) is known. FIG. 12 is a longitudinal sectional view showing the configuration of the I-type drift layer PT-IGBT. As shown in FIG. 12, the I-type drift layer PT-IGBT is made of an FZ wafer. ^- P on the back side of the drift layer 31 ⁺ Collector layer 34 and n ⁺ The buffer layer 30 is formed by an ion implantation method, and a collector electrode 39 is provided. n ^- On the surface side of the drift layer 31, the p base region 32, n ⁺ An emitter region 33, a gate oxide film (gate insulating film) 35, a gate electrode 36, an interlayer insulating film 37 and an emitter electrode 38 are formed.
[0007]
In the I-type drift layer PT-IGBT having the configuration shown in FIG. 12, since the extension of the depletion layer in the blocking mode is stopped by the buffer layer 30, a high breakdown voltage can be obtained even if the drift layer 31 is thin. For this reason, it has an advantage that the amount of voltage drop in the on state is small compared to the NPT-IGBT having the same breakdown voltage. Further, since the collector layer 34 has a low concentration, the amount of hole injection during forward conduction is small. Therefore, there is an advantage that the turn-off loss is small.
Generally, it is desirable to make the drift layer as short as possible in order to reduce the loss of the IGBT. However, if the drift layer is shortened, the breakdown voltage is lowered. FIG. 13 is a graph showing the state of the electric field distribution generated in the IGBT in the blocking mode. In this graph, the integrated value of the electric field distribution when the maximum electric field strength at the PN junction of each IGBT reaches the critical electric field strength, that is, the area of each electric field distribution represents the breakdown voltage of each IGBT. The larger the area, the higher the pressure resistance characteristics. Therefore, in order to obtain a high breakdown voltage characteristic with a short drift layer, a rectangular electric field can be obtained by reducing the gradient of the electric field distribution in the drift layer as much as possible as in the “I-type drift layer PT-IGBT” shown by a solid line in FIG. It can be seen that the distribution should be realized. In order to reduce the gradient of the electric field distribution in the drift layer, the impurity concentration of the drift layer may be made extremely low to form the I layer.
[0008]
However, when the drift layer is changed to the I layer, there is a problem that intense vibration accompanied by a very high surge voltage is generated at the time of turn-off. The reason why this vibration occurs is as follows. In the IGBT with a buffer layer, the stored carriers in the drift layer are swept out by the electric field of the depletion layer at the time of turn-off, and shift to the blocking mode. The collector-emitter voltage during switching is about half of the rated breakdown voltage of the IGBT. When the depletion layer reaches the buffer layer at the time of turn-off, there is no excess carrier in the drift layer, and the IGBT becomes a capacitor having a capacity ε / W. Here, ε is the dielectric constant of silicon, and W is the drift layer width. Since the LC circuit is constituted by the capacitance of the IGBT and the parasitic inductance of the wiring, vibration occurs.
[0009]
In addition, when the drift layer is formed as an I layer, the depletion layer easily reaches the side surface (dicing surface) of the element. Since the physical strain after dicing remains on the side surface of the element, the carrier life is very short. Therefore, when the depletion layer reaches the side surface of the element, a very large current flows, and there is a problem that a sufficient breakdown voltage cannot be obtained. Therefore, in practice, it is necessary to increase the impurity concentration of the drift layer to such an extent that the depletion layer does not reach the side surface of the device when the rated voltage is applied, so it is extremely difficult to make the drift layer an I layer. .
In order to solve this, Japanese Patent Application No. 2001-158612 has reported a semiconductor device constituting an I-type drift layer PT-IGBT with a buffer layer having an I-layered drift layer using an FZ wafer and a manufacturing method thereof. ing.
[0010]
The contents will be described in detail. FIG. 14 is a longitudinal sectional view showing an example of the configuration of the I-type drift layer PT-IGBT constituting this semiconductor device. As shown in FIG. 14, this I-type drift layer PT-IGBT has n ^- Drift layer 41, p base region 42, n ⁺ Emitter region 43, p ⁺ Collector layer 44, gate oxide film 45 which is a gate insulating film, gate electrode 46, interlayer insulating film 47, emitter electrode 48, collector electrode 49, n ⁺ Buffer layers 40 and n ⁺ A separation region 51 is provided. In FIG. 14, n ^- Although only one P base region 42 is formed in the drift layer 41, a plurality of p base regions 42 can be formed. N for each p base region 42 ⁺ An emitter region 43, a gate oxide film 45, a gate electrode 46, and an interlayer insulating film 47 can also be provided.
[0011]
The drift layer 41 is composed of an FZ wafer. The base region 42 is formed on the surface portion of the drift layer 41. The emitter region 43 is formed on the surface portion of the base region 42. The gate oxide film 45 is formed on the surface of the portion that becomes the channel region of the base region 42, and the gate electrode 46 is formed thereon. The emitter electrode 48 is electrically connected to the emitter region 43 and the base region 42 while being insulated from the gate electrode 46 and the drift layer 41 by the interlayer insulating film 47. The collector layer 44 and the collector electrode 49 are formed on the back surface portion of the drift layer 41. The buffer layer 40 is provided between the collector layer 44 and the drift layer 41. The isolation region 51 is provided so as to reach the buffer layer 40 from the surface of the drift layer 41 along the element side surface.
[0012]
Here, the drift layer 41 has an extremely low impurity concentration and is formed into an I layer. Further, as shown in FIG. 15, the buffer layer 40 has a long buffer layer width and is set to a lower concentration. This prevents the depletion layer from extending in the buffer layer 40 during turn-off. Further, since the buffer layer concentration is low, excess carriers exist further on the collector side than the position where the depletion layer is blocked. In general, vibration is generated at turn-off in the I-type drift layer PT-IGBT because the excess carriers in the drift layer are depleted. In this I-type drift layer PT-IGBT, vibration at the time of turn-off is suppressed by excess carriers present on the collector side in the buffer layer 40.
[0013]
Here, assuming that the electron concentration in the buffer layer 40 during forward conduction is N, a high injection state occurs when the average doping concentration of the buffer layer 40 is N or less, and excess carriers exist. Therefore, when the thickness of the buffer layer 40 is x, the total impurity concentration in the buffer layer 40 needs to be x · N or less. On the other hand, in order to prevent the depletion layer in the buffer layer 40, a critical electric field in the buffer layer 40, for example, 2 × 10 ^Five V / cm needs to be zero. Therefore, if the dielectric constant in silicon is Eps and the elementary charge is q, 2 × 10 ^Five <Q · (total impurity concentration in the buffer layer) / Eps needs to be established. When a constant is calculated for this equation, x · N> (total impurity concentration in the buffer layer)> 1.3 × 10 6 ¹² Is obtained.
[0014]
When the rated breakdown voltage is V and the impurity concentration of the drift layer 41 is ND, the depletion layer width in the vertical direction is given by √ ((2 · Eps · V) / (q · ND)). If the width of the depletion layer in the horizontal direction is, for example, six times the width of the depletion layer in the vertical direction, the width of the depletion layer in the horizontal direction is 6√ ((2 · Eps · V) / (q · ND)). When this is calculated, the width of the depletion layer in the lateral direction is √ (4.68 × 10 ⁸ V / ND).
In this case, between the rated breakdown voltage V, the impurity concentration ND of the drift layer 41 and the breakdown voltage structure width W, W ² <4.68 × 10 ⁸ The relationship V / ND is established. That is, the breakdown voltage structure width W is shorter than the lateral depletion layer width. Therefore, assuming that there is no isolation region 51, the depletion layer extends to the side surface of the element in the blocking mode, and the leakage current increases. In order to prevent this, the separation region 51 is provided. That is, since the depletion layer is prevented from reaching the device side surface by the isolation region 51, the leakage current is suppressed to the same level or lower than that of the conventional IGBT. Note that there is no problem in characteristics even if the isolation region 51 is provided when the breakdown voltage structure width W is longer than the lateral depletion layer width.
[0015]
Next, a manufacturing process of the I-type drift layer PT-IGBT having the configuration shown in FIG. 14 will be described. 16 to 21 are vertical cross-sectional views showing the main parts of the I-type drift layer PT-IGBT during manufacture. As an example, the breakdown voltage of this IGBT is set to 1200V. First, for example, a mask 61 is selectively formed on the surface of an FZ (floating zone) wafer having a specific resistance of 1000 Ωcm and a thickness of 500 μm with an interval of, for example, 100 μm (FIG. 16). Then, n-type impurities are ion-implanted from the wafer surface. As a result, an impurity implantation region 62 is formed in a region of the wafer surface that is not covered with the mask 61 (FIG. 17).
[0016]
Subsequently, the n-type impurity in the impurity implantation region 62 is selectively diffused to a depth of, for example, 110 μm by heat treatment to form the isolation region 51 (FIG. 18). After removing the thermal oxide film 63 on the wafer surface, a base region 42, an emitter region 43, a gate oxide film 45, and a gate electrode 46 are formed between adjacent isolation regions 51 and 51. Then, after forming an interlayer insulating film 47 on the surface, aluminum is deposited and patterned to form an emitter electrode 48 (FIG. 19). Thereafter, the FZ wafer is ground from the back surface, and the thickness of the silicon region is set to 95 μm, for example (FIG. 20).
Subsequently, after irradiating the back surface of the wafer with boron ions, annealing is performed at 300 ° C. to 500 ° C. to activate boron atoms, thereby forming a collector layer 44 having a thickness of 0.5 μm, for example. Subsequently, after irradiating the back surface of the wafer with protons or oxygen ions, annealing is performed at 300 ° C. to 500 ° C., for example, the peak concentration is 5 × 10 5. ¹⁵ cm ^-3 A buffer layer 40 having a width of 20 μm is formed (FIG. 21). At this time, the width of the drift layer 41 is, for example, 75 μm. Finally, if the collector electrode 49 is formed on the back surface of the wafer and diced, the I-type drift layer PT-IGBT shown in FIG. 14 is completed. In FIG. 14 and FIGS. 16 to 21, the dicing surface is indicated by a broken line.
[0017]
By manufacturing as described above, the buffer layer 40 prevents the extension of the depletion layer in the blocking mode from reaching the collector layer 44, and also prevents the buffer layer 40 from extending in the state of preventing the extension of the depletion layer. Since excess carriers exist in a region near the collector layer, it is possible to prevent vibration from occurring at turn-off in the IGBT having the drift layer 41 formed into the I layer. FIG. 22 shows turn-off waveforms for the I-type drift layer PT-IGBT of the embodiment and the conventional I-type drift layer PT-IGBT (see FIG. 12). According to the embodiment, it can be seen that no vibration is generated at the time of turn-off.
[0018]
Further, if manufactured as described above, the isolation region 51 prevents the extension of the depletion layer in the blocking mode from reaching the device side surface, so that the breakdown voltage structure width is shorter than the lateral depletion layer width. But the leakage current can be suppressed. Therefore, a semiconductor device that constitutes a high breakdown voltage I-type drift layer PT-IGBT that does not generate vibration at turn-off can be obtained.
Further, in the above-described manufacturing, with respect to the excess carrier distribution during forward conduction, the excess carrier concentration at the middle position of the drift layer is not less than the excess carrier concentration at the boundary between the drift layer 41 and the buffer layer 40 and not more than 5 times. Good. In this way, the trade-off between on-voltage versus turn-off loss can be optimized. For this, a trench gate structure may be adopted. FIG. 23 shows the I-type drift layer PT-IGBT according to the embodiment, the I-type drift layer PT-IGBT employing a trench gate structure, and the conventional I-type drift layer PT-IGBT (when the rated breakdown voltage is 1200 V). FIG. 12) and the trade-off between the conventional NPT-IGBT (see FIG. 10). Also, the trade-off between on-voltage and withstand voltage is improved.
[0019]
Although different from the above, oxygen is added to silicon at a high temperature of 700 ° C. at a high temperature of 700 ° C. using a low pressure CVD (Chemical Vapor Deposition) method on the surface of the semiconductor region that maintains the breakdown voltage. ⁷ -10 ¹³ There is a structure in which a high-resistance semiconductive film of Ω · cm is formed to ensure stable breakdown voltage. However, if oxygen is mixed into the semiconductive film from the outside during the cooling process (the process of returning from 700 ° C. to room temperature), hot electrons enter the semiconductive film, causing disturbance in the electric field in the device and causing breakdown voltage degradation. It is disclosed that the semiconductive film is covered with a polysilicon conductive film to suppress the entry of oxygen from the outside during the cooling process to stabilize the breakdown voltage (see, for example, Patent Document 1).
[0020]
[Patent Document 1]
JP 2000-312012 A
[0021]
[Problems to be solved by the invention]
However, in order to form a low-concentration and wide buffer layer by the ion implantation method as described above, a special expensive ion implantation apparatus capable of ion implantation of protons or oxygen is required, and after the ion implantation step, A long annealing process is required. As described above, if ion implantation is performed for a long time, the semiconductor substrate is damaged, the leakage current of the device increases, the carrier mobility decreases, the on-voltage increases, and the device characteristics deteriorate. Further, if such ion implantation is performed after the wafer thickness is reduced, wafer cracking occurs, the yield rate decreases, and the manufacturing cost increases. Further, if the acceleration voltage for ion implantation is excessively increased in order to shorten the implantation time, there arises a disadvantage that it is difficult to shield a portion where ion implantation is not performed.
[0022]
An object of the present invention is to solve the above-described problems and provide a method for manufacturing a semiconductor device that can form a low-concentration and wide buffer layer at low cost without deteriorating device characteristics.
[0023]
[Means for Solving the Problems]
To achieve the above objective, A first conductivity type drift layer; a second conductivity type base region formed on a surface of the first conductivity type drift layer; and a first conductivity type formed on a surface of the second conductivity type base region. Of the first conductivity type buffer layer and the second conductivity type collector layer formed on the back surface of the first conductivity type drift layer, and comprising an FZ wafer. A process of diffusing oxygen from both sides of the semiconductor substrate at a high temperature and removing oxygen from the surface layer of the semiconductor substrate by a high temperature heat treatment The region from which oxygen is removed on one side is referred to as the drift layer. And a step of the semiconductor substrate The other Process to reduce the thickness to less than half and the oxygen remaining on the semiconductor substrate to be donor by heat treatment The buffer layer And a manufacturing method including the step.
Also, A first conductivity type drift layer; a second conductivity type base region formed on a surface of the first conductivity type drift layer; and a first conductivity type formed on a surface of the second conductivity type base region. Of the first conductivity type buffer layer and the second conductivity type collector layer formed on the back surface of the first conductivity type drift layer, and comprising an FZ wafer. Diffusion of oxygen at high temperature from both sides of the semiconductor substrate Shiso Oxygen diffusion depth is shallower than half the thickness of the semiconductor substrate Forming process and , Removing the oxygen in the surface layer of the semiconductor substrate by a high-temperature heat treatment and removing the oxygen on one surface as the drift layer; and not reaching the oxygen diffusion depth on the one surface side A method of grinding the other surface of the semiconductor substrate, and a step of converting oxygen remaining in the semiconductor substrate into a donor by heat treatment to form the buffer layer; and To do.
Also, Using a semiconductor substrate made of an FZ wafer, A second conductivity type high impurity concentration base region formed on one main surface of the first conductivity type low impurity concentration drift layer; a first conductivity type emitter region formed on a surface layer of the base region; An emitter electrode electrically connected to both the emitter region and the base region; a gate electrode formed on the base region via a gate insulating film; and a first electrode formed on the other main surface of the drift layer. A collector layer of two conductivity types, a collector electrode electrically connected to the collector layer, and formed between the drift layer and the collector layer, and prevents the depletion layer from extending in the blocking mode. A first conductivity type buffer layer having excess carriers in a region near the collector at the time of turn-off, from one main surface of the drift layer to the buffer layer, FZ First conductivity extending along the cut surface when cutting individual elements formed on the wafer Type In a method for manufacturing a semiconductor device having a high impurity concentration isolation region,
Oxygen is removed by high-temperature and long-time heat treatment in an oxygen atmosphere. FZ Diffuse into the wafer and then In an oxygen-free atmosphere By heat treatment in FZ Oxygen from the wafer surface Forming a relief oxygen concentration gradient region, grinding the other surface of the FZ wafer until reaching the separation region, For low temperature heat treatment More of the oxygen gradient region In the manufacturing method, the buffer layer is formed by converting oxygen into a donor.
[0024]
A step of diffusing oxygen into the semiconductor wafer by first heat treatment at a predetermined temperature in an oxygen atmosphere from both sides of the FZ wafer; In an oxygen-free atmosphere Oxygen is released from the surface of the semiconductor wafer by a second heat treatment at a predetermined temperature and a oxygen concentration gradient is formed, and oxygen is converted into a donor by a third heat treatment at a low temperature. Riba A step of forming a buffer layer, a step of selectively forming a high impurity concentration separation region on one main surface side of the wafer, and a wafer surface between adjacent separation regions, Base area, A step of forming an emitter region, a gate insulating film, a gate electrode and an emitter electrode, and the other main surface of the wafer; To reach the separation area A manufacturing method includes a grinding step, a step of forming a collector layer on the other main surface of the wafer after grinding the wafer, and a step of forming a collector electrode on the collector layer.
[0025]
The temperature of the first heat treatment is preferably in the range of 1150 ° C to 1350 ° C.
The temperature of the second heat treatment is preferably in the range of 1150 ° C to 1350 ° C.
The temperature of the third heat treatment is 350 ° C. to 550 ° C. of It is good that it is a range. [Action]
Oxygen introduced into silicon at a high temperature of 1150 ° C. to 1350 ° C. is interspersed between silicon atomic lattices in an atomic state. When this is heat-treated in the range of 350 ° C. to 550 ° C., the scattered oxygen gathers to form a cluster state. At this time, the electrons possessed by oxygen jump out, so this cluster acts as a donor. When the temperature exceeds 550 ° C., the clusters are precipitated in the silicon crystal, the emission of electrons is eliminated, and the donor function is lost. On the other hand, if the temperature is lower than 350 ° C., a cluster functioning as a donor is not formed.
[0026]
Therefore, the temperature at which oxygen introduced into the silicon crystal acts as a donor is between 350 ° C. and 550 ° C., and the temperature range where the effect is high is 400 ° C. to 500 ° C.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
1 to 3 show a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Each figure (a) is a cross-sectional view of a main part manufacturing process shown in the order of steps, and each figure (b) is each figure (a ) Is a profile diagram of oxygen concentration or impurity concentration. The vertical axis of the profile diagram is a LOG scale, and FIG. 3B is a profile of the impurity concentration of the YY line in FIG.
A thermal oxide film 101 having a thickness of 1.6 μm is formed on an n-type FZ wafer 100 having a specific resistance of 1000 Ω · cm and a thickness of 500 μm. Thereafter, the thermal oxide film 101 on the planned scribe portion is etched to form an opening 102 to expose silicon. Then POCl _Three Gas is allowed to flow in an oxygen atmosphere at 1200 ° C. for 2 hours, and phosphorus is doped on the silicon in the opening 102. Then, oxygen atmosphere (O ₂ About 12 liters / minute, H ₂ Is driven at 1300 ° C. for 100 hours to form an n-type isolation region 103 having a diffusion depth of 120 μm. At the same time, oxygen is diffused into the FZ wafer 100. The diffusion length (distance at which the concentration is 37%) is about 200 μm. The oxygen diffusion layer 104 extends over the entire area of the FZ wafer 100. Although not shown, the surface is covered with a phosphorous glass film (FIG. 1). Next, without removing the thermal oxide film 101 and the phosphor glass film (not shown), a nitrogen atmosphere (N ₂ In an atmosphere of 12 liters / minute), heat treatment is performed at 1150 ° C. for 24 hours to release oxygen from the wafer surface (extraction: outward diffusion). As a result, the oxygen residual layer 105 is formed, and the oxygen concentration can be changed. At this time, even if a thermal oxide film exists on the surface of the FZ wafer 100, oxygen in the silicon is absorbed by the oxide film and used for the growth of the oxide film, or escapes through the oxide film to the outside. Oxygen inside 100 escapes (extracts) from the silicon out of the silicon. When the thermal oxide film 101 and the phosphor glass film (not shown) are removed and oxygen in the silicon is removed, phosphorus is diffused outward from the separation layer 103, and the phosphor is diffused again into the silicon to form a device formation region. Therefore, it is better not to remove the thermal oxide film 101 and the phosphor glass film (not shown). In the figure, L0 is the thickness of the donor-scheduled layer (FIG. 2).
[0028]
Next, the thermal oxide film 101 and the phosphor glass film (not shown) are removed, and the structure on the surface side of the IGBT cell (that is, base region 106, emitter region 107, gate electrode 108 and And the FZ wafer 100 is ground from the back surface until the separation layer 103 is exposed (see FIG. 2A), and the wafer is 90 μm thick (the thickness of the A portion). To. Thereafter, boron ions are implanted into the back surface and annealed at 450 ° C. for 5 hours. By this low temperature annealing, boron is activated and the p-type collector layer 111 is formed. At the same time, oxygen in the donor-scheduled layer is converted into a donor, and the peak concentration is 5 × 10 5. ¹⁵ cm ^-3 As a result, an n-type buffer layer 110 having a thickness W of about 20 μm is formed. In the figure, L is the thickness of the donor layer, and 120 is n. ^- It is a drift layer of the layer (FIG. 3).
[0029]
Thereafter, the FZ wafer 100 is cut along a scribe line (not shown) to complete a PT-type IGBT chip with an I-type drift layer having a relatively low concentration and a thick buffer layer.
4 to 6 show a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Each figure (a) is a sectional view of a main part manufacturing process shown in the order of steps, and each figure (b) is each figure (a). ) Is a profile diagram of oxygen concentration or impurity concentration. The vertical axis of the profile diagram is a LOG scale, and FIG. 6B is a profile of the impurity concentration of the Y-Y line in FIG.
[0030]
The difference from FIGS. 1 to 3 is only that the specific resistance of the FZ wafer is small (impurity concentration is high), and the others are the same.
The n-type FZ wafer 200 having a specific resistance of 60 Ω · cm and a thickness of 500 μm is heat-treated at 1300 ° C. for 100 hours in an oxygen atmosphere under the same conditions as in the first embodiment, and as shown in FIG. The oxygen concentration profile is completed. After that, when heat treatment is performed at 1150 ° C. for 24 hours in a nitrogen atmosphere under the same conditions as described above to release oxygen from the surface of the FZ wafer 200, an oxygen concentration gradient as shown in FIG.
[0031]
As in FIG. 3, the structure on the front surface side of the IGBT cell is formed on the surface of the FZ wafer 200 by the conventional method, and the FZ wafer 200 is ground from the back surface to have a thickness of 140 μm. Boron ions are implanted into the back surface and annealed at 450 ° C. for 5 hours. By this low temperature annealing, boron is activated and the collector layer 111 is formed, and at the same time, oxygen becomes a donor and the peak concentration becomes 5 × 10 5. ¹⁵ cm ^-3 As a result, the buffer layer 110 as shown in FIG. 6 having a thickness W of about 20 μm is formed. In FIG. 6, 130 is n. ^- It is the drift layer of the layer. Thereafter, cutting along the scribe line of the FZ wafer 200, a PT type IGBT chip with an I type drift layer having a relatively low concentration and a thick buffer layer is completed.
[0032]
In the oxygen introduction process of the first and second embodiments, the higher the diffusion temperature, the higher the oxygen diffusion coefficient, and a predetermined diffusion distance can be obtained in a shorter time. However, when the temperature exceeds 1350 ° C. and approaches the melting point of silicon (1414 ° C.), the crystallinity of silicon is disturbed and device characteristics are deteriorated. On the other hand, when the diffusion temperature is lower than 1150 ° C., the diffusion coefficient becomes too small and it takes time to diffuse. The diffusion coefficient of oxygen at 1300 ° C. is about 1 × 10 ^-9 cm ² / Sec, but at 1150 ° C., about 1 × 10 times that of 1/10 ^-Ten m ² / Sec. For example, it can diffuse only about 60 μm at 1150 ° C. for 100 hours. Therefore, it takes 300 hours or more to diffuse 200 μm at 1150 ° C., and heat treatment for a longer time than this is not practical.
[0033]
In addition, the above temperature range is preferable because the step of removing (releasing) oxygen from the silicon surface also utilizes thermal diffusion of oxygen.
Therefore, both the temperature for diffusing oxygen into silicon and the temperature for extracting oxygen from silicon are set to 1150 ° C. or higher and 1350 ° C. or lower. In order to diffuse oxygen effectively, or to extract oxygen effectively, the temperature is preferably 1250 ° C. or higher and 1320 ° C. or lower.
Also, oxygen donor formation proceeds most efficiently at 450 ° C. If the temperature exceeds 550 ° C., the number of donors decreases, and if it is less than 350 ° C., donor formation hardly occurs. Therefore, 350 for oxygen donor conversion ℃ The temperature range is 550 ° C. or lower. More preferably, the range of 400 ° C. or higher and 500 ° C. is effective.
[0034]
Depending on the combination of the diffusion conditions for oxygen introduction (diffusion temperature and time) and the heat treatment conditions for releasing oxygen (heat treatment temperature and time), various n ⁺ A buffer layer profile can be formed.
FIGS. 7 to 9 show a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Each figure (a) is a cross-sectional view of a main part manufacturing process shown in the order of steps, and each figure (b) is each figure (a). ) Is a profile diagram of oxygen concentration or impurity concentration. The vertical axis of the profile diagram is a LOG scale.
The time for diffusing oxygen is shortened, and oxygen is diffused from the front and back surfaces of the FZ wafer 400 to about 70 μm to form the oxygen diffusion layer 404 (FIG. 7). Next, this oxygen is extracted by heat treatment to form an oxygen residual layer 405 (FIG. 8). Then, after grinding the back surface, by converting this oxygen into a donor, a wide n is formed at the center of the thinned wafer. ⁺ A buffer layer 410 is formed (FIG. 9). In this way, n ^- Drift layer 420 / n ⁺ Buffer layer 410 / n ^- N like the drift layer 420 ^- N in the center of the drift layer ⁺ A profile having a buffer layer can be formed. By applying such a diffusion profile to the drift layer of an IGBT or pin diode, vibration of the voltage waveform in the blocking mode can be suppressed.
[0035]
【The invention's effect】
In this invention, oxygen is introduced into the semiconductor substrate by a long-time heat treatment, and this is again diffused out by the heat treatment. Remove oxygen from the surface layer and convert oxygen remaining in the semiconductor substrate into a donor Since the buffer layer is formed, a low-concentration and wide buffer layer can be easily formed.
In addition, since the buffer layer is formed by heat treatment, damage that becomes a problem when the buffer layer is formed by ion implantation does not occur and the device characteristics are not deteriorated.
Further, since the buffer layer is formed with a thick wafer, cracking of the wafer does not occur when the buffer layer is formed by ion implantation with a thin wafer. Therefore, the yield rate can be improved and the manufacturing cost can be reduced.
[Brief description of the drawings]
1A and 1B are diagrams showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a cross-sectional view of a manufacturing process of a main part, and FIG.
FIGS. 2A and 2B are views showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention, following FIG. 1, in which FIG. 2A is a cross-sectional view of the main part manufacturing process, and FIG.
FIG. 3 shows a manufacturing method of the semiconductor device according to the first embodiment of the present invention continued from FIG. 2, in which (a) is a cross-sectional view of a main part manufacturing process, and (b) is a YY view of (a). Profile diagram of impurity concentration in line
FIGS. 4A and 4B are diagrams showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, where FIG. 4A is a cross-sectional view of the main part manufacturing process, and FIG. 4B is a profile diagram of oxygen concentration;
FIGS. 5A and 5B are views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, following FIG. 4, where FIG. 5A is a cross-sectional view of the main part manufacturing process, and FIG.
6 is a diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention, continued from FIG. 5, in which (a) is a cross-sectional view of a main part manufacturing process, and (b) is a Y- Y-line impurity concentration profile
7A and 7B are diagrams showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention, where FIG. 7A is a cross-sectional view of a manufacturing process of a main part, and FIG. 7B is a profile diagram of oxygen concentration.
FIGS. 8A and 8B are diagrams illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention following FIG. 7, wherein FIG. 8A is a cross-sectional view of a main part manufacturing process, and FIG.
FIGS. 9A and 9B are diagrams illustrating a method of manufacturing a semiconductor device according to a third embodiment of the invention, in which FIG. 9A is a cross-sectional view of a manufacturing process of main parts, and FIG.
FIG. 10 is a longitudinal sectional view showing a configuration of a conventional NPT-IGBT.
FIG. 11 is a longitudinal sectional view showing a configuration of a conventional PT-IGBT.
FIG. 12 is a longitudinal sectional view showing another configuration of a conventional PT-IGBT.
FIG. 13 is a graph showing the electric field distribution generated in the IGBT in the blocking mode.
FIG. 14 is a longitudinal sectional view showing an example of the configuration of an I-type drift layer PT-IGBT constituting the semiconductor device according to the invention.
15 is a diagram for explaining the existence of excess carriers in the buffer layer in the I-type drift layer PT-IGBT having the configuration shown in FIG. 14;
16 is a longitudinal sectional view showing the main part in the middle of manufacturing the I-type drift layer PT-IGBT having the configuration shown in FIG. 14;
17 is a longitudinal sectional view showing the main part in the middle of manufacturing the I-type drift layer PT-IGBT having the configuration shown in FIG. 14;
18 is a longitudinal sectional view showing the main part in the middle of manufacturing the I-type drift layer PT-IGBT having the configuration shown in FIG. 14;
19 is a longitudinal sectional view showing the main part in the middle of manufacturing the I-type drift layer PT-IGBT having the configuration shown in FIG. 14;
20 is a longitudinal sectional view showing the main part in the middle of manufacturing the I-type drift layer PT-IGBT having the configuration shown in FIG. 14;
FIG. 21 is a longitudinal sectional view showing an essential part in the middle of manufacturing the I-type drift layer PT-IGBT having the configuration shown in FIG.
FIG. 22 is a waveform diagram showing turn-off waveforms for the I-type drift layer PT-IGBT of FIG. 14 and the conventional I-type drift layer PT-IGBT.
FIG. 23 is a diagram showing on-voltage versus turn-off loss trade-off for various I-type drift layers PT-IGBT including FIG.
[Explanation of symbols]
100 FZ wafer (n-type / 1000Ω · cm)
101, 401 Thermal oxide film
102 opening
103 separation region
104, 404 Oxygen diffusion layer
105, 405 Oxygen residual layer
106 Base area
107 Emitter region
108 Gate electrode
109 Emitter electrode
110 Buffer layer
111 Collector layer
112 Collector electrode
120 drift layer
130 Drift layer
200 FZ wafer (n-type / 60Ω · cm)
400 FZ wafer
L0 Thickness of the donor layer
L thickness of the donor layer
W Buffer layer thickness

Claims (7)

A first conductivity type drift layer; a second conductivity type base region formed on a surface of the first conductivity type drift layer; and a first conductivity type formed on a surface of the second conductivity type base region. And a first conductive type buffer layer and a second conductive type collector layer formed on the rear surface of the first conductive type drift layer, and a semiconductor substrate made of an FZ wafer. A step of diffusing oxygen at a high temperature from both sides of the substrate, a step of removing oxygen on a surface layer of the semiconductor substrate by a high-temperature heat treatment and removing a region of oxygen on one surface as the drift layer, and the other of the semiconductor substrate A method for manufacturing a semiconductor device, comprising: a step of grinding the surface of the semiconductor substrate to reduce the thickness to half or less; and a step of converting oxygen remaining in the semiconductor substrate into a donor by heat treatment to form the buffer layer . A first conductivity type drift layer; a second conductivity type base region formed on a surface of the first conductivity type drift layer; and a first conductivity type formed on a surface of the second conductivity type base region. And a first conductive type buffer layer and a second conductive type collector layer formed on the rear surface of the first conductive type drift layer, and a semiconductor substrate made of an FZ wafer. sided diffused oxygen at high temperature from the diffusion depth of the oxygen, said a step of from shallow half the thickness of the semiconductor substrate, one face to remove oxygen at a high temperature heat treatment of the surface layer of said semiconductor substrate A region where oxygen is removed is used as the drift layer, the other surface of the semiconductor substrate is ground so as not to reach the oxygen diffusion depth on the one surface side, and oxygen remaining in the semiconductor substrate The buff is converted into a donor by heat treatment The method of manufacturing a semiconductor device which comprises the steps of a layer, a. Using a semiconductor substrate made of an FZ wafer, a second conductivity type high impurity concentration base region formed on one main surface of the first conductivity type low impurity concentration drift layer and a surface layer of the base region An emitter region of a first conductivity type; an emitter electrode electrically connected to both the emitter region and the base region; a gate electrode formed on the base region via a gate insulating film; A second conductivity type collector layer formed on the other main surface; a collector electrode electrically connected to the collector layer; and a depletion layer formed in the blocking mode between the drift layer and the collector layer. And a buffer layer of a first conductivity type having excess carriers in a region near the collector at the time of turn-off and one main surface of the drift layer. To § layer, in the manufacturing method of a semiconductor device including an isolation region of a first conductivity type high impurity concentration extending along the cutting plane when dividing off individual elements that are formed on the FZ wafer,
A step of diffusing oxygen into the FZ wafer by high-temperature and long-time heat treatment in an oxygen atmosphere , and then releasing oxygen from the surface of the FZ wafer by heat treatment in an oxygen-free atmosphere to form an oxygen concentration gradient region; the method of manufacturing a semiconductor device comprising: the step of grinding to the other surface reaches the isolation region, and forming the buffer layer by donors more oxygen of the oxygen gradient region to a low temperature heat treatment. Oxygen is diffused into the semiconductor wafer from both surfaces of the FZ wafer by a first heat treatment at a predetermined temperature in an oxygen atmosphere, and oxygen is supplied from the semiconductor wafer surface by a second heat treatment at a predetermined temperature in an oxygen-free atmosphere. relief, oxygen and forming a concentration gradient, forming a Riva Ffa layer by the thereby donors oxygen by the third heat treatment cold, selectively high impurity on one main surface of the wafer forming a concentration of isolation area, on the wafer surface between the isolation region adjacent the base region, an emitter region, a gate insulating film, forming a gate electrode and an emitter electrode, the separation of the other main surface of the wafer form a step of grinding to reach the region, after the grinding of the wafer, forming a collector layer on the other main surface of the wafer, a collector electrode on said collector layer The method of manufacturing a semiconductor device, which comprises a step, the to. 5. The method of manufacturing a semiconductor device according to claim 4, wherein a temperature of the first heat treatment is in a range of 1150 ° C. to 1350 ° C. 6. 5. The method of manufacturing a semiconductor device according to claim 4, wherein a temperature of the second heat treatment is in a range of 1150 ° C. to 1350 ° C. 6. 5. The method of manufacturing a semiconductor device according to claim 4, wherein a temperature of the third heat treatment is in a range of 350 ° C. to 550 ° C. 6.

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